TECHNIQUES TO ENABLE DISAGGREGATION OF PHYSICAL MEMORY RESOURCES IN A COMPUTE SYSTEM

Abstract

Various embodiments are generally directed to an apparatus, method and other techniques enable disaggregation of physical memory resources from physical compute resources. For example, embodiments may include a memory interface coupled with the memory controller and a memory module. The memory interface may receive data in parallel via a bus, and convert the received parallel data to send to a memory module of a memory expander sled in serial via a high speed serial link, and receive data in serial via the high speed serial link from the memory module of the memory expander sled, and convert the received serial data to send in parallel to the memory controller via the bus.

Description

RELATED CASES

This application claims priority to U.S. Provisional Patent Application No. 62/365,969, filed Jul. 22, 2016, U.S. Provisional Patent Application No. 62/376,859, filed Aug. 18, 2016, and U.S. Provisional Patent Application No. 62/427,268, filed Nov. 29, 2016, each of which are hereby incorporated by reference in their entirety.

TECHNICAL FIELD

Embodiments described herein generally include determining and communicating metric for physical resources in a data center environment.

BACKGROUND

A computing data center may include one or more computing systems including a plurality of compute nodes or sleds that may include various compute structures and may be physically located on multiple racks. These sleds may include a number of physical resources and provide processing and storage capabilities.

From time-to-time these physical resources may need to be replaced and updated due to failures and newer equipment. Typically, processing resources and memory resources on a sled are replaced at the same time because it is difficult to disaggregate the memory resources from processing resources. This significantly increases the total cost of maintaining the data center since the cost of memory resources occupies a large percentage of the total cost of a sled. Thus, embodiments are directed to solving these others problem.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

FIG. 1 illustrates an example of a data center.

FIG. 2 illustrates an example of a rack.

FIG. 3 illustrates an example of a data center.

FIG. 4 illustrates an example of a data center.

FIG. 5 illustrates an example of a switching infrastructure.

FIG. 6 illustrates an example of a data center.

FIG. 7 illustrates an example of a sled.

FIG. 8 illustrates an example of a data center.

FIG. 9 illustrates an example of a data center.

FIG. 10 illustrates an example of a sled.

FIG. 11 illustrates an example of a data center.

FIG. 12 illustrates an example of a compute system.

FIG. 13 illustrates an example of a compute system.

FIG. 14 illustrates an example of a compute system.

FIG. 15 illustrates an example of logic flow diagrams.

FIG. 16 illustrates an example of logic flow diagrams.

FIG. 17 illustrates an example of a logic flow diagram.

DETAILED DESCRIPTION

Various embodiments may be generally directed to enabling disaggregation of physical compute resources from physical memory resources. As previously discussed, physical compute resources, such as processors, and physical memory resources are typically replaced at the same time because of their integration on the same sled or node. Thus, embodiments are directed to disaggregation solutions to decouple physical compute resources and physical memory resources such that when physical compute resources are replaced, the physical memory resources may be reused. Some of the solutions discussed herein may include physical memory resources incorporated on a memory expander sled coupled with the physical compute resources on a different sled via a high speed link. The memory expander sled may come in various form factors, such as the dual in-line memory module (DIMM) form factor or a solid state drive (SSD) form factor to reduce the overall size and footprint of the memory expander sled.

In one example, the physical memory resources may be implemented in a memory expander sled in a SSD form factor, as previously mentioned. In this example, the SSD form factor may enable a reduction in pin count, but maintain high speed serial links between the physical memory resources and the physical compute resources.

In another example, the physical memory resources may be in a memory expander sled having DIMM form factor and coupled with the physical compute resources via a pig tail connector. The pig tail connector may couple with the physical compute resources via a high serial speed link and include circuitry to convert parallel data to serial data to send data to the physical memory resources. The expander sled may also include circuitry to convert serial data back to parallel data at the physical memory resources for communication with the memory modules. During read operations, the expander sled including the circuitry may convert data read from memory devices from parallel data to serial data to communicate to the physical compute resources via the high serial speed link and pig tail connector. The pig tail connector may receive the data and convert it from serial data back to parallel data to communicate to the physical compute resources. The parallel data may be data communicated in parallel via a bus or link and the serial data may be data communicated in serial via a bus or link.

In a third example, the physical memory resources may be incorporated in a memory expander sled, and asled including the physical compute resources may be coupled with the memory expander sled via a high speed serial link. In this example, the sled having the physical compute resources may have one or more memory controllers and serialization/deserialization (SerDes) circuitry to convert parallel data to serial data for communication with the physical memory resources in the memory expander sled. In some instances, the memory controllers may be integrated memory controllers with the processor or part of a different chipset of the sled with the physical compute resources. Further, the memory expander sled may also include SerDes circuitry to convert the serial data to parallel data for communication with the memory modules.

In a fourth example, the physical memory resources of a memory expander sled may be shared between a number of physical compute resources and may be in a single or individual sleds. The memory expander sled the physical compute resources sled(s) may be coupled via a high speed serial link and each may include circuitry to convert data between parallel data and serial data. Further, the memory expander sled may include a circuit switch to enable the sharing of the physical memory resources with the physical compute resources. These and other details will become more apparent in the following description.

Reference is now made to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding thereof. It may be evident, however, that the novel embodiments can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate a description thereof. The intention is to cover all modifications, equivalents, and alternatives consistent with the claimed subject matter.

FIG. 1 illustrates a conceptual overview of a data center 100 that may generally be representative of a data center or other type of computing network in/for which one or more techniques described herein may be implemented according to various embodiments. As shown in FIG. 1, data center 100 may generally contain a plurality of racks, each of which may house computing equipment comprising a respective set of physical resources. In the particular non-limiting example depicted in FIG. 1, data center 100 contains four racks 102A to 102D, which house computing equipment comprising respective sets of physical resources (PCRs) 105A to 105D. According to this example, a collective set of physical resources 106 of data center 100 includes the various sets of physical resources 105A to 105D that are distributed among racks 102A to 102D. Physical resources 106 may include resources of multiple types, such as—for example—processors, co-processors, accelerators, field-programmable gate arrays (FPGAs), memory, and storage. The embodiments are not limited to these examples.

The illustrative data center 100 differs from typical data centers in many ways. For example, in the illustrative embodiment, the circuit boards (“sleds”) on which components such as CPUs, memory, and other components are placed are designed for increased thermal performance. In particular, in the illustrative embodiment, the sleds are shallower than typical printed circuit boards (PCBs). In other words, the sleds are shorter from the front to the back, where cooling fans are located. This decreases the length of the path that air must to travel across the components on the PCB. Further, the components on the sled are spaced further apart than in typical PCBs, and the components are arranged to reduce or eliminate shadowing (i.e., one component in the air flow path of another component). In the illustrative embodiment, processing components such as the processors are located on a top side of a sled while memory modules are located on a bottom side of the sled. As a result of the enhanced airflow provided by this design, the components may operate at higher frequencies and power levels than in typical systems, thereby increasing performance. Furthermore, the sleds are configured to blindly mate with power and data communication cables in each rack 102A, 102B, 102C, 102D, enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. Similarly, individual components located on the sleds, such as processors, accelerators, memory, and data storage drives, are configured to be easily upgraded due to their increased spacing from each other. In the illustrative embodiment, the components additionally include hardware attestation features to prove their authenticity.

Furthermore, in the illustrative embodiment, the data center 100 utilizes a single network architecture (“fabric”) that supports multiple other network architectures which may be in accordance to standards, such as Institute of Electrical and Electronics Engineers (IEEE) 802.3-2015 standard (Ethernet) or any predecessors, revisions, or variants thereof, and other architectures, such as Intel® Omni-Path®. The sleds, in the illustrative embodiment, are coupled to switches via optical fibers, which provide higher bandwidth and lower latency than typical twisted pair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high bandwidth, low latency interconnections and network architecture, the data center 100 may, in use, pool resources, such as memory, accelerators (e.g., graphics accelerators, FPGAs, ASICs, etc.), and data storage drives that are physically disaggregated, and provide them to compute resources (e.g., processors) on an as needed basis, enabling the compute resources to access the pooled resources as if they were local. The illustrative data center 100 additionally receives usage information for the various resources, predicts resource usage for different types of workloads based on past resource usage, and dynamically reallocates the resources based on this information.

The racks 102A, 102B, 102C, 102D of the data center 100 may include physical design features that facilitate the automation of a variety of types of maintenance tasks. For example, data center 100 may be implemented using racks that are designed to be robotically-accessed, and to accept and house robotically-manipulable resource sleds. Furthermore, in the illustrative embodiment, the racks 102A, 102B, 102C, 102D include integrated power sources that receive a greater voltage than is typical for power sources. The increased voltage enables the power sources to provide additional power to the components on each sled, enabling the components to operate at higher than typical frequencies. FIG. 2 illustrates an exemplary logical configuration of a rack 202 of the data center 100. As shown in FIG. 2, rack 202 may generally house a plurality of sleds, each of which may comprise a respective set of physical resources. In the particular non-limiting example depicted in FIG. 2, rack 202 houses sleds 204-1 to 204-4 comprising respective sets of physical resources 205-1 to 205-4, each of which constitutes a portion of the collective set of physical resources 206 comprised in rack 202. With respect to FIG. 1, if rack 202 is representative of—for example—rack 102A, then physical resources 206 may correspond to the physical resources 105A comprised in rack 102A. In the context of this example, physical resources 105A may thus be made up of the respective sets of physical resources, including physical storage resources 205-1, physical accelerator resources 205-2, physical memory resources 204-3, and physical compute resources 205-5 comprised in the sleds 204-1 to 204-4 of rack 202. The embodiments are not limited to this example. Each sled may contain a pool of each of the various types of physical resources (e.g., compute, memory, accelerator, storage). By having robotically accessible and robotically manipulable sleds comprising disaggregated resources, each type of resource can be upgraded independently of each other and at their own optimized refresh rate.

FIG. 3 illustrates an example of a data center 300 that may generally be representative of one in/for which one or more techniques described herein may be implemented according to various embodiments. In the particular non-limiting example depicted in FIG. 3, data center 300 comprises racks 302-1 to 302-32. In various embodiments, the racks of data center 300 may be arranged in such fashion as to define and/or accommodate various access pathways. For example, as shown in FIG. 3, the racks of data center 300 may be arranged in such fashion as to define and/or accommodate access pathways 311A, 311B, 311C, and 311D. In some embodiments, the presence of such access pathways may generally enable automated maintenance equipment, such as robotic maintenance equipment, to physically access the computing equipment housed in the various racks of data center 300 and perform automated maintenance tasks (e.g., replace a failed sled, upgrade a sled). In various embodiments, the dimensions of access pathways 311A, 311B, 311C, and 311D, the dimensions of racks 302-1 to 302-32, and/or one or more other aspects of the physical layout of data center 300 may be selected to facilitate such automated operations. The embodiments are not limited in this context.

FIG. 4 illustrates an example of a data center 400 that may generally be representative of one in/for which one or more techniques described herein may be implemented according to various embodiments. As shown in FIG. 4, data center 400 may feature an optical fabric 412. Optical fabric 412 may generally comprise a combination of optical signaling media (such as optical cabling) and optical switching infrastructure via which any particular sled in data center 400 can send signals to (and receive signals from) each of the other sleds in data center 400. The signaling connectivity that optical fabric 412 provides to any given sled may include connectivity both to other sleds in a same rack and sleds in other racks. In the particular non-limiting example depicted in FIG. 4, data center 400 includes four racks 402A to 402D. Racks 402A to 402D house respective pairs of sleds 404A-1 and 404A-2, 404B-1 and 404B-2, 404C-1 and 404C-2, and 404D-1 and 404D-2. Thus, in this example, data center 400 comprises a total of eight sleds. Via optical fabric 412, each such sled may possess signaling connectivity with each of the seven other sleds in data center 400. For example, via optical fabric 412, sled 404A-1 in rack 402A may possess signaling connectivity with sled 404A-2 in rack 402A, as well as the six other sleds 404B-1, 404B-2, 404C-1, 404C-2, 404D-1, and 404D-2 that are distributed among the other racks 402B, 402C, and 402D of data center 400. The embodiments are not limited to this example.

FIG. 5 illustrates an overview of a connectivity scheme 500 that may generally be representative of link-layer connectivity that may be established in some embodiments among the various sleds of a data center, such as any of example data centers 100, 300, and 400 of FIGS. 1, 3, and 4. Connectivity scheme 500 may be implemented using an optical fabric that features a dual-mode optical switching infrastructure 514. Dual-mode optical switching infrastructure 514 may generally comprise a switching infrastructure that is capable of receiving communications according to multiple link-layer protocols via a same unified set of optical signaling media, and properly switching such communications. In various embodiments, dual-mode optical switching infrastructure 514 may be implemented using one or more dual-mode optical switches 515. In various embodiments, dual-mode optical switches 515 may generally comprise high-radix switches. In some embodiments, dual-mode optical switches 515 may comprise multi-ply switches, such as four-ply switches. In various embodiments, dual-mode optical switches 515 may feature integrated silicon photonics that enable them to switch communications with significantly reduced latency in comparison to conventional switching devices. In some embodiments, dual-mode optical switches 515 may constitute leaf switches 530 in a leaf-spine architecture additionally including one or more dual-mode optical spine switches 520. Spine switches may include switches that can handle Layer 3 (L3) with high port density, which allows for scalability. In some instances, a spine switch is directly connected to a network control system with a virtual Layer 2 switch on top of the leaf-spine system.

In various embodiments, dual-mode optical switches may be capable of receiving both Ethernet protocol communications carrying Internet Protocol (IP packets) and communications according to a second, high-performance computing (HPC) link-layer protocol (e.g., Intel® Omni-Path Architecture®, Infiniband®) via optical signaling media of an optical fabric. As reflected in FIG. 5, with respect to any particular repair of sleds 504A and 504B possessing optical signaling connectivity to the optical fabric, connectivity scheme 500 may thus provide support for link-layer connectivity via both Ethernet links and HPC links. Thus, both Ethernet and HPC communications can be supported by a single high-bandwidth, low-latency switch fabric. The embodiments are not limited to this example.

FIG. 6 illustrates a general overview of a rack architecture 600 that may be representative of an architecture of any particular one of the racks depicted in FIGS. 1 to 4 according to some embodiments. As reflected in FIG. 6, rack architecture 600 may generally feature a plurality of sled spaces into which sleds may be inserted, each of which may be robotically-accessible via a rack access region 601. In the particular non-limiting example depicted in FIG. 6, rack architecture 600 features five sled spaces 603-1 to 603-5. Sled spaces 603-1 to 603-5 feature respective multi-purpose connector modules (MPCMs) 616-1 to 616-5. In some instances, when a sled is inserted into any given one of sled spaces 603-1 to 603-5, the corresponding MPCM may couple with a counterpart MPCM of the inserted sled. This coupling may provide the inserted sled with connectivity to both signaling infrastructure and power infrastructure of the rack in which it is housed.

Included among the types of sleds to be accommodated by rack architecture 600 may be one or more types of sleds that feature expansion capabilities. FIG. 7 illustrates an example of a sled 704 that may be representative of a sled of such a type. As shown in FIG. 7, sled 704 may comprise a set of physical resources 705, as well as an MPCM 716 designed to couple with a counterpart MPCM when sled 704 is inserted into a sled space such as any of sled spaces 603-1 to 603-5 of FIG. 6. Sled 704 may also feature an expansion connector 717. Expansion connector 717 may generally comprise a socket, slot, or other type of connection element that is capable of accepting one or more types of expansion modules, such as an expansion sled 718. By coupling with a counterpart connector on expansion sled 718, expansion connector 717 may provide physical resources 705 with access to supplemental computing resources 705B residing on expansion sled 718. The embodiments are not limited in this context.

FIG. 8 illustrates an example of a rack architecture 800 that may be representative of a rack architecture that may be implemented in order to provide support for sleds featuring expansion capabilities, such as sled 704 of FIG. 7. In the particular non-limiting example depicted in FIG. 8, rack architecture 800 includes seven sled spaces 803-1 to 803-7, which feature respective MPCMs 816-1 to 816-7. Sled spaces 803-1 to 803-7 include respective primary regions 803-1A to 803-7A and respective expansion regions 803-1B to 803-7B. With respect to each such sled space, when the corresponding MPCM is coupled with a counterpart MPCM of an inserted sled, the primary region may generally constitute a region of the sled space that physically accommodates the inserted sled. The expansion region may generally constitute a region of the sled space that can physically accommodate an expansion module, such as expansion sled 718 of FIG. 7, in the event that the inserted sled is configured with such a module.

FIG. 9 illustrates an example of a rack 902 that may be representative of a rack implemented according to rack architecture 800 of FIG. 8 according to some embodiments. In the particular non-limiting example depicted in FIG. 9, rack 902 features seven sled spaces 903-1 to 903-7, which include respective primary regions 903-1A to 903-7A and respective expansion regions 903-1B to 903-7B. In various embodiments, temperature control in rack 902 may be implemented using an air cooling system. For example, as reflected in FIG. 9, rack 902 may feature a plurality of fans 919 that are generally arranged to provide air cooling within the various sled spaces 903-1 to 903-7. In some embodiments, the height of the sled space is greater than the conventional “1U” server height. In such embodiments, fans 919 may generally comprise relatively slow, large diameter cooling fans as compared to fans used in conventional rack configurations. Running larger diameter cooling fans at lower speeds may increase fan lifetime relative to smaller diameter cooling fans running at higher speeds while still providing the same amount of cooling. The sleds are physically shallower than conventional rack dimensions. Further, components are arranged on each sled to reduce thermal shadowing (i.e., not arranged serially in the direction of air flow). As a result, the wider, shallower sleds allow for an increase in device performance because the devices can be operated at a higher thermal envelope (e.g., 250 W) due to improved cooling (i.e., no thermal shadowing, more space between devices, more room for larger heat sinks, etc.).

MPCMs 916-1 to 916-7 may be configured to provide inserted sleds with access to power sourced by respective power modules 920-1 to 920-7, each of which may draw power from an external power source 921. In various embodiments, external power source 921 may deliver alternating current (AC) power to rack 902, and power modules 920-1 to 920-7 may be configured to convert such AC power to direct current (DC) power to be sourced to inserted sleds. In some embodiments, for example, power modules 920-1 to 920-7 may be configured to convert 277-volt AC power into 12-volt DC power for provision to inserted sleds via respective MPCMs 916-1 to 916-7. The embodiments are not limited to this example.

MPCMs 916-1 to 916-7 may also be arranged to provide inserted sleds with optical signaling connectivity to a dual-mode optical switching infrastructure 914, which may be the same as—or similar to—dual-mode optical switching infrastructure 514 of FIG. 5. In various embodiments, optical connectors contained in MPCMs 916-1 to 916-7 may be designed to couple with counterpart optical connectors contained in MPCMs of inserted sleds to provide such sleds with optical signaling connectivity to dual-mode optical switching infrastructure 914 via respective lengths of optical cabling 922-1 to 922-7. In some embodiments, each such length of optical cabling may extend from its corresponding MPCM to an optical interconnect loom 923 that is external to the sled spaces of rack 902. In various embodiments, optical interconnect loom 923 may be arranged to pass through a support post or other type of load-bearing element of rack 902. The embodiments are not limited in this context. Because inserted sleds connect to an optical switching infrastructure via MPCMs, the resources typically spent in manually configuring the rack cabling to accommodate a newly inserted sled can be saved.

FIG. 10 illustrates an example of a sled 1004 that may be representative of a sled designed for use in conjunction with rack 902 of FIG. 9 according to some embodiments. Sled 1004 may feature an MPCM 1016 that comprises an optical connector 1016A and a power connector 1016B, and that is designed to couple with a counterpart MPCM of a sled space in conjunction with insertion of MPCM 1016 into that sled space. Coupling MPCM 1016 with such a counterpart MPCM may cause power connector 1016 to couple with a power connector comprised in the counterpart MPCM. This may generally enable physical resources 1005 of sled 1004 to source power from an external source, via power connector 1016 and power transmission media 1024 that conductively couples power connector 1016 to physical resources 1005.

Sled 1004 may also include dual-mode optical network interface circuitry 1026. Dual-mode optical network interface circuitry 1026 may generally comprise circuitry that is capable of communicating over optical signaling media according to each of multiple link-layer protocols supported by dual-mode optical switching infrastructure 914 of FIG. 9. In some embodiments, dual-mode optical network interface circuitry 1026 may be capable both of Ethernet protocol communications and of communications according to a second, high-performance protocol. In various embodiments, dual-mode optical network interface circuitry 1026 may include one or more optical transceiver modules 1027, each of which may be capable of transmitting and receiving optical signals over each of one or more optical channels. The embodiments are not limited in this context.

Coupling MPCM 1016 with a counterpart MPCM of a sled space in a given rack may cause optical connector 1016A to couple with an optical connector comprised in the counterpart MPCM. This may generally establish optical connectivity between optical cabling of the sled and dual-mode optical network interface circuitry 1026, via each of a set of optical channels 1025. Dual-mode optical network interface circuitry 1026 may communicate with the physical resources 1005 of sled 1004 via electrical signaling media 1028. In addition to the dimensions of the sleds and arrangement of components on the sleds to provide improved cooling and enable operation at a relatively higher thermal envelope (e.g., 250 W), as described above with reference to FIG. 9, in some embodiments, a sled may include one or more additional features to facilitate air cooling, such as a heatpipe and/or heat sinks arranged to dissipate heat generated by physical resources 1005. It is worthy of note that although the example sled 1004 depicted in FIG. 10 does not feature an expansion connector, any given sled that features the design elements of sled 1004 may also feature an expansion connector according to some embodiments. The embodiments are not limited in this context.

FIG. 11 illustrates an example of a data center 1100 that may generally be representative of one in/for which one or more techniques described herein may be implemented according to various embodiments. As reflected in FIG. 11, a physical infrastructure management framework 1150A may be implemented to facilitate management of a physical infrastructure 1100A of data center 1100. In various embodiments, one function of physical infrastructure management framework 1150A may be to manage automated maintenance functions within data center 1100, such as the use of robotic maintenance equipment to service computing equipment within physical infrastructure 1100A. In some embodiments, physical infrastructure 1100A may feature an advanced telemetry system that performs telemetry reporting that is sufficiently robust to support remote automated management of physical infrastructure 1100A. In various embodiments, telemetry information provided by such an advanced telemetry system may support features such as failure prediction/prevention capabilities and capacity planning capabilities. In some embodiments, physical infrastructure management framework 1150A may also be configured to manage authentication of physical infrastructure components using hardware attestation techniques. For example, robots may verify the authenticity of components before installation by analyzing information collected from a radio frequency identification (RFID) tag associated with each component to be installed. The embodiments are not limited in this context.

As shown in FIG. 11, the physical infrastructure 1100A of data center 1100 may comprise an optical fabric 1112, which may include a dual-mode optical switching infrastructure 1114. Optical fabric 1112 and dual-mode optical switching infrastructure 1114 may be the same as—or similar to—optical fabric 412 of FIG. 4 and dual-mode optical switching infrastructure 514 of FIG. 5, respectively, and may provide high-bandwidth, low-latency, multi-protocol connectivity among sleds of data center 1100. As discussed above, with reference to FIG. 1, in various embodiments, the availability of such connectivity may make it feasible to disaggregate and dynamically pool resources such as accelerators, memory, and storage. In some embodiments, for example, one or more pooled accelerator sleds 1130 may be included among the physical infrastructure 1100A of data center 1100, each of which may comprise a pool of accelerator resources—such as co-processors and/or field-programmable gate arrays (FPGAs), for example—that is available globally accessible to other sleds via optical fabric 1112 and dual-mode optical switching infrastructure 1114.

In another example, in various embodiments, one or more pooled storage sleds 1132 may be included among the physical infrastructure 1100A of data center 1100, each of which may comprise a pool of storage resources that is available globally accessible to other sleds via optical fabric 1112 and dual-mode optical switching infrastructure 1114. In some embodiments, such pooled storage sleds 1132 may comprise pools of storage devices such as solid-state drives (SSDs), hard disk drives (HDD), hard drive, disk drive, fixed disk drives, and so forth. In various embodiments, one or more high-performance processing sleds 1134 may be included among the physical infrastructure 1100A of data center 1100. In some embodiments, high-performance processing sleds 1134 may comprise pools of high-performance processors, as well as cooling features that enhance air cooling to yield a higher thermal envelope of up to 250 Watts (W) or more. In various embodiments, any given high-performance processing sled 1134 may feature an expansion connector 1117 that can accept a memory expansion sled, such that the next level (second level or third level) memory that is locally available to that high-performance processing sled 1134 is disaggregated from the processors and memory comprised on that sled. In some embodiments, such a high-performance processing sled 1134 may be configured with the next level memory using an expansion sled that comprises low-latency SSD. The optical infrastructure allows for compute resources on one sled to utilize remote accelerator/FPGA, memory, and/or storage resources that are disaggregated on a sled located on the same rack or any other rack in the data center. The remote resources can be located one switch jump away or two-switch jumps away, e.g. remote resources connected through a single or two switches, in the spine-leaf network architecture described above with reference to FIG. 5. The embodiments are not limited in this context.

In various embodiments, one or more layers of abstraction may be applied to the physical resources of physical infrastructure 1100A in order to define a virtual infrastructure, such as a software-defined infrastructure 1100B. In some embodiments, virtual computing resources 1136 of software-defined infrastructure 1100B may be allocated to support the provision of cloud services 1140. In various embodiments, particular sets of virtual computing resources 1136 may be grouped for provision to cloud services 1140 in the form of software defined infrastructure (SDI) services 1138. Examples of cloud services 1140 may include—without limitation—software as a service (SaaS) services 1142, platform as a service (PaaS) services 1144, and infrastructure as a service (IaaS) services 1146.

In some embodiments, management of software-defined infrastructure 1100B may be conducted using a virtual infrastructure management framework 1150B. In various embodiments, virtual infrastructure management framework 1150B may be designed to implement workload fingerprinting techniques and machine-learning techniques in conjunction with managing allocation of virtual computing resources 1136 and/or SDI services 1138 to cloud services 1140. In some embodiments, virtual infrastructure management framework 1150B may use/consult telemetry data in conjunction with performing such resource allocation. In various embodiments, an application/service management framework 1150C may be implemented to provide quality of service (QoS) management capabilities for cloud services 1140. The embodiments are not limited in this context.

FIG. 12 illustrates an example of a compute system 1200 that includes a sled 1204 coupled with physical memory resources 1205-3, which may be incorporated in a memory expander sled 1218. In embodiments, the sled 1204 includes a connector 1217 to couple with a connector 1219 of the memory expander sled 1218. The sled 1204 is capable of communicating data via a high speed serial link 1251 with the memory expander sled 1218 and the physical memory resources 1205-3. The memory expander sled 1218 and physical memory resources 1205-3 may be utilized to store and access data for the physical compute resources 1205-4 of the sled 1204, for example. Having a memory expander sled 1218 with physical memory resources 1205-3 coupled with the physical compute resources 1205-4 may also enable disaggregation of the physical compute resources 1205-4 from the physical memory resources 1205-3. Thus, the physical compute resources 1205-4 or the physical memory resources 1205-3 may be replaced without affecting the remaining physical resource (memory or compute) in the compute system 1200.

In embodiments, the sled 1204 may be the same as other sleds discussed herein, such as sled 1004 illustrated in FIG. 10, and include similar components. For example, the sled 1204 includes physical compute resources 1205-4, which may further include one or more cores 1207-1 through 1207-a, where a may be any positive integer. The physical compute resource 1205-4 also includes a memory controller 1236 and a memory interface 1234 that may couple with the connector 1217 via a high speed serial link 1251, which may be an electrical or optical interconnect or bus and capable of communicating data in serial.

In embodiments, the physical compute resource 1205-4 may be implemented as a microprocessor, a processor, a central processing unit, a multi-core processor, a mobile device processor, a single core processor, a system-on-chip (SoC) device, and so forth. The physical compute resource 1205-4 may be integrated on a single die or multiple dies in a single chip package. Moreover, each of the cores 1207 of the physical compute resources 1205-4 may be independent processing units capable of reading and executing program instructions. The instructions are ordinary instructions that can be executed at the same time or in parallel. In embodiments, the physical compute resource 1205-4 may be coupled with other components of the sled 1204 via one or more interconnects or links.

The physical compute resource 1205-4 also includes a memory controller 1236, which may be an integrated memory controller on the same die as the cores 1207. In other instances, the memory controller 1236 may be integrated into a different die on a different chipset and couple with the cores 1207 by a bus or link, for example. The memory controller 1236 may receive read requests and memory address(es) to read data from memory, e.g. the physical memory resources 1205-3. Data may be read from the physical memory resources 1205-3 of the memory expander sled 1218. The memory controller 1236 may provide the data to the cores 1207 once it is read from memory, for example. Further, the memory controller 1236 may also receive write requests, memory address(es) and associated data to write to the physical memory resources 1205-3 of the memory expander sled 1218.

In some embodiments, the physical memory resources 1205-3 including the memory modules 1211 may include one or more byte addressable write-in-place non-volatile memory devices. The memory devices may also include future generation non-volatile devices, such as a three dimensional crosspoint memory device, or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory devices may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thiristor based memory device, or a combination of any of the above, or other memory. The memory devices may refer to the die itself and/or to a packaged memory product. In some embodiments, the memory modules 1211 may include other types of memory devices, such as dynamic RAM (DRAM), static RAM (SRAM), double data rate DRAM (DDR DRAM), synchronous DRAM (SDRAM), DDR SDRAM, and so forth. Some embodiments may include a combination of different memory types, embodiments are not limited in this manner.

In some embodiments, the memory module 1211 may be a dual in-line memory module (DIMM) having one or more memory devices capable of plugging into a DIMM slot of a PCB of the memory expander sled 1218. The module 1211 may have a DIMM form factor in accordance with one or more standards, such as Joint Electronic Device Engineering Council (JEDEC) defined technical standard JESD248 (“DDR NVDIMM-N Design Standard”), JEDEC Module 4.20.27 (“288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification”), JESD79-4A (“DDR4 SDRAM Standard”), JEDEC Module 4.20.28 (“288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification”), and so forth. Embodiments are not limited in this manner. In some instances, the memory module 1211 may be integrated circuit memory devices incorporated directly on a PCB of the memory expander sled 1218.

In embodiments, the memory controller 1236 may be coupled with a memory interface 1234 via a parallel link 1253, wherein the memory interface 1234 is capable of interfacing with the physical memory resources 1205-3 of the memory expander sled 1218 via a high speed serial link 1251. The parallel link 1253 may be a high-speed parallel link or bus to communicate data in parallel and coupled with the memory interface 1234 and the high speed serial link 1251 may be a link to communicate data in serial. The memory interface 1234 may also include circuitry to communicate data between the memory controller 1234 and the memory module(s) 1211. For example, the memory interface 1234 may include an optical transceiver to communicate data via an optical high speed serial link. In another example, the memory interface 1234 may include an electrical transceiver to communicate via electrical high speed serial links.

The memory interface 1234 may also include circuitry, such as serializer/deserializer (SerDes) circuitry, to convert parallel data to serial data, and vice versa. More specifically, the memory interface 1234 can convert parallel data communicated from one or more cores 1207 to serial data for communication to the memory module(s) 1211 via the high speed serial links 1251. Similarly, the memory interface 1234 may convert serial data received from the memory module(s) 1211 to parallel data for communication to the one or more cores 1207 via the high speed parallel links 1253. Embodiments are not limited to this example, and in some instances, the SerDes circuitry may be incorporated into the connector 1217 instead of the memory interface 1234.

In some embodiments, the memory interface 1234 may include circuitry to compress and decompress data communicated via the high speed serial link 1251. For example, a compression mechanism may be used to generate a fabric packet including the compressed data to communicate serial via the high speed serial links 1251. The compression mechanism may utilize a compression algorithm, such as a Byte Pattern Repeat compression mechanism, a Word (2 bytes) Pattern Repeat compression mechanism, a Dword (4 bytes) Pattern Repeat compression mechanism, and a Qword (8 bytes) Pattern Repeat. In some instances, other compression mechanisms may be utilized, such as compression logic or an algorithm to perform lossless data compression on the data. In one example, a run-length encoding (RLE) algorithm may be used on the data such that a repeating pattern and the length of the repeating pattern are indicated in the compressed data. Other examples of compression algorithms that may be used include Lempel-Ziv 1978, Lempel-Ziv Fast (LZF), DEFLATE, bzip2, Lempel-Ziv-Markov chain algorithm, Lempel-Ziv-Oberhumer, and so forth.

In some embodiments, the memory interface 1234 may communicate information and data including packets using a transaction protocol. The transaction protocol may enable transaction-based data transfers using the high speed interconnect 1251. For example, the high speed interconnect may support a Quick-Path Interconnect transaction protocol that may employ packet-based transfers using a multi-layer protocol architecture. Among its features is support for coherent transactions (e.g., memory coherency). In embodiments, to increase memory transaction bandwidth, a Fully Buffered DIMM (or FB-DIMM) architecture is employed, which introduces an advanced memory buffer (AMB) between the memory controller 1236 and a memory module 1211. Unlike the parallel bus architecture of traditional DRAMs, the high speed serial link 1251 enables an increase in the width of the memory without increasing the pin count of the memory controller 1236 beyond a feasible level. In another example, the high speed serial link 1251 may be a scalable memory interconnect (SMI) link and include Scalable Memory Buffers (SMB).

The memory interface 1234 may be coupled to the connector 1217 via a high speed serial link 1251. In some embodiments, the connector 1217 may be a low pin count high-speed slot connector capable of receiving and coupling with the connector 1219 of the memory expander sled 1218. In one example, the connector 1217 may be a serial attachment (SATA) connector, a micro SATA (mSATA) connector, a SATA2 connector a SATA3 connector, a SATA4 connector, a universal serial bus (USB) connector, a USB3 connector, a SATAe connector, a Thunderbolt 3 connector, a connector in accordance with JEDEC defined technical standard, such as the MO-297 standard, and the MO-300 standard. Other examples, may include a Next Generation Form Factor (NGFF) connector or an M.2 connector. In some embodiments, the connector 1217 may provide an optical connection, e.g. an optical fiber connector. Embodiments are not limited to these examples and other high speed serial connectors may be utilized for the connectors 1217 and 1219.

In some instances, the form factor of the memory expander sled 1218 may determine which connector type is utilized for connectors 1217 and 1219. For example, the memory expander sled 1218 may be in a solid state drive (SSD) form factor and the memory module(s) 1211 may include one or more byte addressable write-in-place non-volatile memory devices, or any other memory device, as previously discussed. In some instances, the memory expander sled 1218 may not incorporate memory modules, but may have integrated circuit memory devices incorporated directly on a printed circuit board (PCB) of the memory expander sled 1218. Embodiments are not limited in this manner.

The SSD form factor may be in accordance with the JEDEC MO-297-A (May 2009) standard or any predecessors, revisions, or variants thereof. Other examples include SSD form factors in accordance with a Next Generation Form Factor (NGFF) or an M.2 form factor. The connectors 1217 and 1219 may be one of the SATA connectors, e.g. SATA2, SATA3, SATA4, etc., or other high speed serial connectors for connecting with a SSD form factor. In this example, the SSD form factor enables the sled 1204 having the physical compute resource 1205-4 to be changed without changing the memory expander sled 1218 and memory modules 1211 or allowing them to be reused with other physical compute resources 1205-4.

In another example, the memory expander sled 1218 may have a DIMM form factor and the memory module 1211 may be integrated circuit memory devices incorporated on the PCB of the memory expander sled 1218. The connector 1217 of the sled 1204 may be a pig tail type connector capable of coupling with connector 1219 of the memory expander sled 1218 via a high speed serial link 1251. The DIMM form factor of the memory expander sled 1218 may be in accordance with one or more standards, such as JEDEC defined technical standard JESD248 (“DDR NVDIMM-N Design Standard”), JEDEC Module 4.20.27 (“288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification”), JESD79-4A (“DDR4 SDRAM Standard”), JEDEC Module 4.20.28 (“288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification”), and so forth. Embodiments are not limited in this manner. In this example, the connector 1217, configured as a pig tail, may be added as DIMM connector to the PCB of the sled 1204. The connector 1217 may couple with a high speed serial link, which may be low pin count cable or wire that is part of the pig tail having an opposing end that may couple with a DIMM connector (connector 1219) of the memory expander sled 1218. In this example, the connectors 1217 and 1219 may include SerDes circuitry to convert data from parallel to serial, and vice versa, for communication via the low pin count wire between the memory expander sled 1218 and the sled 1204. Note that FIG. 12 only includes a single sled 1204 coupled with a single memory expander sled 1218. However, embodiments are not limited in manner. In some instances, the sled 1204 may include a number of connectors 1217, each configured as a pig tail and coupled with a corresponding memory expander sled 1218, for example.

On the memory expander sled 1218, the connector 1219 may be coupled with a physical memory resource 1205-3, including a memory interface 1209 via a high speed serial link 1251 or a high speed parallel link (not shown) for instances when the SerDes circuitry is incorporated in the connector 1219 itself. Data may be passed or communicated to the memory interface 1209, which may include at least one of an optical transceiver and electrical transceiver to communicate data between the memory module(s) 1211 and the memory controller 1236 of the sled 1204. In some instances, the memory interface 1209 may also include SerDes circuitry to convert parallel data to serial data. Thus, data communicated from the connector 1219 to the memory interface 1209 in a serial data format and the memory interface 1209 may convert the data back to parallel data for the memory module(s) 1211. Similarly, parallel data communicated from the memory module(s) 1211 may be serialized by the memory interface 1209 for communication to the sled 1204. The memory interface 1209 may also include circuitry to perform compression and decompression and communicate data via a transactional protocol, as previously discussed.

In embodiments, the memory interface 1209 may receive the read requests from memory interface 1234, which may include one or more address(es) to read data from the memory modules 1211. The data may be read from the memory modules 1211 and the memory interface 1209 may provide the data over the high speed serial link 1251, as discussed. Similarly, the memory interface 1209 may also receive write requests from memory interface 1234, which may include one or more address(es) and data that may be written into memory modules 1211. The data may be written into the memory modules 1211 based on the one or more address(es).

FIG. 13 illustrates an example of a compute system 1300 that may generally be representative of a sled 1304 coupled with an add-in component, such as a memory expander sled 1318 having physical memory resources 1305-3. In embodiments, the compute system 1300 may be similar to compute system 1200 of FIG. 12. Further and in some embodiments, sled 1304 may be the same as other sleds discussed herein, such as sled 1004 illustrated in FIG. 10 and sled 1204 of FIG. 12, and include similar components. For example, the sled 1304 includes physical compute resources 1305-4, which may further include one or more cores 1307-1 through 1307-a, where a may be any positive integer. The physical compute resource 1305-4 also includes a number of memory controllers 1336-1 through 1336-4 and a number of memory interfaces 1334-1 through 1334-4 that may couple with a connector 1317 via a high speed serial link 1351. The illustrated example of FIG. 13 only shows four memory controllers 1336-1 through 1336-4 and four memory interfaces 1334-1 through 1334-4. However, embodiments are not limited in this manner and embodiments may include more or fewer memory controllers 1336 and memory interfaces 1334.

In embodiments, the physical compute resource 1305-4 may be implemented via a processor, computer processing unit, multi-core processor, and so forth as similarly discussed with respect physical compute resources 1205-4 of FIG. 12. The physical compute resource 1305-4 may be integrated on a single die or multiple dies in a single chip package, for example. In FIG. 13 the physical compute resource 1305-4 includes four memory controllers 1336-1 through 1336-4, each of which may be an integrated memory controller on the same die as the cores 1307. In other instances, the memory controllers 1336-1 through 1336-4 may be integrated into a different die on a different chipset and couple with the cores 1307 by a bus, for example.

Each of the memory controllers 1336-1 through 1336-4 may process read and write requests. Further, each of the memory controllers 1336-1 through 1336-4 may provide a memory channel in a multi-channel memory architecture. Each of the memory channels may enable communication between the memory controllers 1336-1 through 1336-4 and one or more of the memory modules 1311-1 through 1311-8. In some instances, the throughput may be 50 GigaTransfers/second (GT/s)/Channel. The illustrated embodiment includes four channels; however, embodiments are not limited in this manner and embodiments may include more or fewer channels.

In embodiments, each of the memory controllers 1336-1 through 1336-4 may be coupled with a corresponding memory interface 1334-1 through 1334-4 via parallel links 1353. The parallel links 1353 may be high-speed parallel links or a bus coupled with the memory interfaces 1334-1 through 1334-4. In embodiments, each of the memory interface 1334-1 through 1334-4 may include circuitry, e.g. an optical and/or electrical transceiver, to communicate data between the corresponding memory controllers 1336-1 through 1336-4 and the memory modules 1311-1 through 1311-8. Each of the memory interfaces 1334-1 through 1334-4 may also include circuitry, such as SerDes circuitry, to convert parallel data to serial data, and vice versa. Thus, data communicated from one or more cores 1307 may be converted from parallel data to serial data for communication to the memory modules 1311-1 through 1311-8 by the memory interfaces 1334-1 through 1334-4. Similarly, the memory interfaces 1334-1 through 1334-4 may convert serial data received from the memory modules 1311-1 through 1311-8 to parallel data for communication to the one or more cores 1307. Embodiments are not limited in this manner and some instances, the SerDes circuitry may be implemented as part of the connector 1317. In this example, memory interfaces 1334 may be coupled with the connector 1317 via parallel links and the connector 1317 may convert the data. However, if each of the memory interfaces 1334-1 through 1334-4 includes SerDes circuitry, they may also circuitry to send and receive data via at least one of optical serial links and electrical serial links, perform compression and decompression of the data, and use a transactional protocol.

In embodiments, the memory interfaces 1334-1 through 1334-4 may be coupled with a connector 1317 via a high speed serial link 1351 or a parallel link depending on whether the parallel to serial (or vice versa) conversation occurs in the memory interface 1334 or the connector 1317. In embodiments, the connector 1317 may couple with connector 1319 of the memory expander sled 1318 via the high speed serial links 1351. Each high speed serial link 1351 may provide a memory channel for the multi-channel memory architecture. In embodiments, the connectors 1317 and 1319 may provide at least one of an optical high-speed serial connection and electrical high-speed serial connection via the high speed serial link 1351.

Moreover, the connector 1319 of the memory expander sled 1818 may communicate data with the sled 1304 via the high speed serial links 1351, as discussed. In some instances, the connector 1319 also includes SerDes circuitry to convert data from parallel data to serial data to communicate to the memory modules 1311, and vice versa to communicate data to the sled 1304. The connector 1319 may be coupled with the physical memory resource 1305-3, and in particular, memory interfaces 1309-1 through 1309-4. Although FIG. 13 illustrates four memory interfaces 1309-1 through 1309-4, embodiments are not limited in this manner and may include more or fewer interfaces.

Each of the memory interfaces 1309-1 through 1309-4 may be coupled with the connector 1319 via a parallel link if the connector 1319 includes the SerDes circuitry or a high speed serial link 1351 if the memory interfaces 1309 include the SerDes circuitry. In embodiments, each of the memory interfaces 1309-1 through 1309-4 may also include circuitry, e.g. an electrical or optical transceiver, to send and receive data via optical serial links and electrical serial links. Each of the memory interfaces 1309-1 through 1309-4 may be capable of receiving and sending data between the memory module(s) 1311-1 through 1311-8 of the memory expander sled 1318 and the sled 1304. In instances, the data may be communicated via high-speed parallel links 1353 with the memory modules 1311-1 through 1311-8.

In embodiments, the physical memory resources 1305-3 may include a number of memory modules 1311-1 through 1311-8, each of which include one or more byte addressable write-in-place non-volatile memory devices. The memory devices may also include future generation non-volatile devices, such as a three dimensional crosspoint memory device, or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory devices may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thiristor based memory device, or a combination of any of the above, or other memory. The memory devices may refer to the die itself and/or to a packaged memory product. In some embodiments, the memory modules 1211 may include other types of memory devices, such as dynamic RAM (DRAM), static RAM (SRAM), double data rate DRAM (DDR DRAM), synchronous DRAM (SDRAM), DDR SDRAM, and so forth. Some embodiments may include a combination of different memory types, embodiments are not limited in this manner. In some embodiments, the memory module 1311 may be a dual in-line memory module (DIMM) having one or more memory devices capable of plugging into a DIMM slot of a PCB of the memory expander sled 1318. The memory module 1311 may have a DIMM form factor in accordance with one or more standards, such as Joint Electronic Device Engineering Council (JEDEC) defined technical standard JESD248 (“DDR NVDIMM-N Design Standard”), JEDEC Module 4.20.27 (“288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification”), JESD79-4A (“DDR4 SDRAM Standard”), JEDEC Module 4.20.28 (“288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification”), and so forth. Embodiments are not limited in this manner.

In embodiments, the memory expander sled 1318 coupled with the sled 1304 via the connectors 1317 and 1319 and the high speed serial links 1351 may enable disaggregation of the physical compute resources 1305-4 from the physical memory resources 1305-3. Thus, the physical compute resources 1305-4 or the physical memory resources 1305-3 may be replaced without affecting the remaining physical resource (memory or compute) in the compute system 1300.

FIG. 14 illustrates an example of a compute system 1400 that may generally include a sled 1404 coupled with an add-in component, such as a memory expander sled 1418 having physical memory resources 1405-3. In some instances, the sled 1404 may be a processor cartridge as part of a rack-scale system. In embodiment compute system 1400 may be similar to compute systems 1200 and 1300 of FIGS. 12 and 13. The sled 1404 may include a number of physical compute resources 1405-4-1 through 1405-4-x, where x may be any positive integer. Further and in some embodiments, the sled 1404 may be the same as other sleds discussed herein, such as sleds 1004, 1204, and 1304 illustrated in FIGS. 10, 12 and 13, and include similar components. In some instances, each of the physicals compute resources 1405-4 may be incorporated into their own sled 1404. Embodiments are not limited in this manner.

In instances, each of the physical compute resources 1405-4 may include one or more cores (not shown), one or more memory controllers 1436, and one or more memory interfaces 1434. These components may be similar or the same as the liked named components as previously discussed in FIGS. 12 and 13. For example, each of the physical resources 1405-4 may include memory controllers 1436 to process read and write requests for memory, and communicate with memory interfaces 1434 via high-speed parallel links (not shown). Further, the memory interfaces 1434 may include circuitry to communicate the data and convert the parallel data to serial data for communication via the high-speed serial links 1451. In some instances, the memory interfaces 1434 may include SerDes circuitry to convert parallel data to serial data and vice versa, for example. The serial data may be communicated via the high-speed serial links 1451, which may be optical high-speed serial links or electrical high-speed serial links capable of communicating data at 50 GigaTransfers/second (GT/s). In some instances, the high speed serial links 1451 may be capable of communicating data at 50 GT/s for each memory channel in a multi-channel memory architecture.

In embodiments, the memory interfaces 1434 may be coupled to a connector 1417 via high speed serial links 1451. Although not shown, in some instances the memory interfaces 1434 may be coupled to connector 1417 via parallel links, and the connector 1417 may include SerDes circuitry to convert data between parallel and serial formats. Further, the connector 1417 may couple with connector 1419 of the memory expander sled 1418 via high speed serial links 1451 to electrically and/or optically link the two sleds 1404 and 1418 together. In some instances, each high speed serial link 1451 linking the two sleds 1404 and 1418 may provide a memory channel for a multi-channel memory architecture. Similar to connector 1417, the connector 1419 of the memory expander sled 1418 may also include SerDes circuitry to convert data from parallel data to serial data and vice versa. However, embodiments are not limited in this manner and some instances; memory interfaces 1409 may include the SerDes circuitry to convert serial data to parallel data and vice versa. The memory interfaces 1434 may also include circuitry to perform compression/decompression of the data and communicate via a transactional protocol.

The connector 1419 may be coupled with a circuit switch 1414, such as an electrical circuit switch (flit or FED) or an optical circuit switch. The circuit switch 1414 may enable the physical compute resources 1405 to share memory, such as the memory modules 1411 of physical memory resource 1405-3. In some instances, the circuit switch 1414 may be incorporated in or be part of the connector 1419. The circuit switch 1414 may couple one or more memory modules 1411 with a physical compute resource 1405-4 for utilization by the physical compute resources 1405-4 to process data and workloads.

In some instances, the circuit switch 1414 may include circuitry to determine workloads for the physical compute resource 1405-4 and a required amount of memory to process those workloads. The circuit switch 1414 may dynamically assign memory modules 1411 (and channels) for use by a physical compute resource 1405-4 during run-time to process a workload, for example. Once a workload is complete or processed, the circuit switch 1414 may configure or reallocate memory modules 1411 to process another workload. The reallocation and configuration of which memory modules 1411 are used by which physical compute resource 1405-4 may occur continuously, and in real-time, while the compute system 1400 is processing workloads.

The circuit switch 1414 may also be configurable based on information received by a controller. For example, a baseboard management controller (not shown) of a sled 1404 may communicate information and control the circuit switch 1414. The information may indicate a circuit switch configuration or information of workloads, which may be used by the circuit switch 1414 to make the determination of configuration. The circuit switch 1414 may receive information from other controllers of the compute system 1400, such as pod management controller and a rack management controller. In some instances, the circuit switch 1414 may be configured or reconfigured at a time of a boot or reboot. For example, if one or more of the physical compute resources 1405-4 are rebooted or booted, the circuit switch 1414 may configure itself to allocate memory modules 1411 accordingly, e.g. to process workloads based on a requirement of the physical compute resources 1405. Embodiments are not limited in this manner.

The physical memory resource 1405-3 may include any number of memory modules 1411-c, where c may be any positive integer. Moreover, the memory modules 1411 may be shared with the physical compute resources 1405-4 via the circuit switch 1414; and therefore, may be considered a pool of memory modules 1411. each of which include one or more byte addressable write-in-place non-volatile memory devices. The memory devices may also include future generation non-volatile devices, such as a three dimensional crosspoint memory device, or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory devices may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thiristor based memory device, or a combination of any of the above, or other memory. The memory devices may refer to the die itself and/or to a packaged memory product. In some embodiments, the memory modules 1211 may include other types of memory devices, such as dynamic RAM (DRAM), static RAM (SRAM), double data rate DRAM (DDR DRAM), synchronous DRAM (SDRAM), DDR SDRAM, and so forth. Some embodiments may include a combination of different memory types, embodiments are not limited in this manner.

In embodiments, the memory modules 1411 may be in memory expander sled 1418 in an SSD form factor and may use any SATA connector, as previously discussed. For example, The SSD form factor may be in accordance with the JEDEC MO-297-A (May 2009) standard or any predecessors, revisions, or variants thereof. Other examples include SSD form factors in accordance with a Next Generation Form Factor (NGFF) or an M.2 form factor. The connectors 1417 and 1419 may be one of the SATA connectors, e.g. SATA2, SATA3, SATA4, etc., or other high speed serial connectors for connecting with a SSD form factor. Embodiments are not limited to these examples, and other SSD form factors may be utilized and be consistent with embodiments discussed herein.

In embodiments, the memory expander sled 1418 coupled with the sled 1404 via the connectors 1417 and 1419 and the high speed serial links 1451 may enable disaggregation of the physical compute resources 1405-4 from the physical memory resources 1405-3. Thus, the physical compute resources 1405-4 or the physical memory resources 1405-3 may be replaced without affecting the remaining physical resource (memory or compute) in the compute system 1400.

FIG. 15 illustrates an embodiment of logic flow 1500 and logic flow 1550. The logic flows 1500 and 1550 may be representative of some or all of the operations executed by one or more embodiments described herein. For example, the logic flows 1500 and 1550 may illustrate operations performed by a memory interface of a sled having physical compute resources, However, embodiments are not limited in this, and one or more operations may be performed by other components or systems discussed herein, such as a connector.

With respect to logic flow 1500, embodiments include receiving data via a high speed parallel link from a core of physical compute resource at block 1502. In some instances, the data may be data a core requests to store or write to memory. The data may be communicated to a memory interface via a memory controller and may also be communicated with address information for use by the memory to store the data.

At block 1504, the logic flow 1500 may include converting the data received via the high speed parallel link for communication via a high speed serial link. For example, the memory interface may serialize the data, via SerDes circuitry, to communicate the data via a single/differential link. In embodiments, the SerDes circuitry may convert the data for communication via a high speed serial link using any number of techniques, including but not limited to, a parallel clock SerDes technique, an Embedded clock SerDes technique, a 8b/10b SerDes technique, and a bit interleaved SerDes technique. To convert the data for serial communication, the SerDes circuitry may receive a parallel clock input, a set of data input lines (parallel link), and input data latches. The SerDes circuitry may utilize a phase-locked looped to multiply the incoming parallel clock up to a serial frequency for the high speed serial link.

At block 1506, the logic flow 1500 may include sending the data via the high speed serial link to one or more memory modules. In some instances, the one or more memory modules may be incorporated on a memory expander sled to enable easy disaggregation of the memory modules and the cores.

With respect to logic flow 1550, embodiments include receiving data via a high speed serial link from a memory of a memory expander sled at block 1522. In some instances, the data may be data a core requests to be read from the memory and may be received based on a read request. The data may be communicated to the memory interface via a memory interface of a memory expander sled. In some instances, data may be received from a circuit switch coupled with the memory interface of the memory expander sled.

At block 1554, the logic flow 1550 may include converting the data received via high speed serial link for communication via a high speed parallel link. For example, the memory interface may deserialize the data, via SerDes circuitry, to communicate the data via a parallel link. In embodiments, the SerDes circuitry may convert the data for communication via a high speed parallel link using any number of techniques, including but not limited to, the parallel clock SerDes technique, the Embedded clock SerDes technique, the 8b/10b SerDes technique, and the bit interleaved SerDes technique. To convert the data for parallel, the SerDes circuitry may utilize a receive clock output to clock down to a parallel data rate for communication of the data via the parallel link. The data may be communicated via a set of output lines using output data latches to the cores. based on the parallel rate, for example. In some instances, a buffer (two registers) may be used to clock down the data from the high serial link to the parallel link rate. At block 1556, the logic flow 1500 may include sending the data via the high speed parallel link to a core.

FIG. 16 illustrates an embodiment of logic flow 1600 and logic flow 1650. The logic flows 1600 and 1650 may be representative of some or all of the operations executed by one or more embodiments described herein. For example, the logic flows 1600 and 1650 may illustrate operations performed by a memory interface of a memory expander sled having physical memory resources, However, embodiments are not limited in this, and one or more operations may be performed by other components or systems discussed herein, such as a connector.

With respect to logic flow 1600, embodiments include receiving data via a high speed parallel link from a memory module of physical memory resource at block 1602. In some instances, the data may be data a core requested to read from the memory module.

At block 1604, the logic flow 1600 may include converting the data received via the high speed parallel link for communication via a high speed serial link. For example, the memory interface may serialize the data, via SerDes circuitry, to communicate the data via a single/differential link. In embodiments, the SerDes circuitry may convert the data for communication via a high speed serial link using any number of techniques, including but not limited to, a parallel clock SerDes technique, an Embedded clock SerDes technique, a 8b/10b SerDes technique, and a bit interleaved SerDes technique. To convert the data for serial communication, the SerDes circuitry may receive a parallel clock input, a set of data input lines (parallel link), and input data latches. The SerDes circuitry may utilize a phase-locked looped to multiply the incoming parallel clock up to a serial frequency for the high speed serial link. At block 1606, the logic flow 1600 may include sending the data via the high speed serial link to physical compute resources include the core requesting the data.

With respect to logic flow 1650, embodiments include receiving data via a high speed serial link from a physical compute resources at block 1652. In some instances, the data may be data a core requests to be read from the memory to be stored in the memory. The data may be communicated to the memory interface via a memory interface of a sled having the physical compute resources. In some instances, data may be received from a circuit switch coupled with the memory interface of the memory expander sled.

At block 1654, the logic flow 1650 may include converting the data received via high speed serial link for communication via a high speed parallel link. For example, the memory interface may deserialize the data, via SerDes circuitry, to communicate the data via a parallel link. In embodiments, the SerDes circuitry may convert the data for communication via a high speed parallel link using any number of techniques, including but not limited to, the parallel clock SerDes technique, the Embedded clock SerDes technique, the 8b/10b SerDes technique, and the bit interleaved SerDes technique. To convert the data for parallel, the SerDes circuitry may utilize a receive clock output to clock down to a parallel data rate for communication of the data via the parallel link. The data may be communicated via a set of output lines using output data latches to the memory based on the parallel rate, for example. In some instances, a buffer (two registers) may be used to clock down the data from the high serial link to the parallel link rate. At block 1656, the logic flow 1600 may include sending the data via the high speed parallel link to memory or memory module.

FIG. 17 illustrates an embodiment of a logic flow 1700 that may be representative of some or all of the operations executed by one or more embodiments described herein. For example, the logic flows 1700 and 1750 may illustrate operations performed by a circuit switch. However, embodiments are not limited in this, and one or more operations may be performed by other components or systems discussed herein.

The logic flow 1700, at block 1702, includes receiving configuration information to configure usage of memory, such as one or more memory modules. In some instances, the configuration information may be received from a controller, such as baseboard management controller of a sled, a rack management controller of a rack, and a pod management controller of a pod. The configuration information may include information associating workloads and cores processing the workloads with particular memory modules. In some embodiments, the configuration information may include an indication of workload requirements and the circuit switch may determine which memory modules may support the workload. For example, the determination may be based on a storage size, a bandwidth, a transfer rate, error correction, and so forth for the memory module.

At block 1704, the logic flow 1700 may include determining a configuration of memory. Further and a block 1706, the logic flow may include setting the configuration for the memory. The configuration may include setting the circuit switch to direct read/write requests based on data, associated workloads, and received addresses. For example, the circuit switch may direct a read request to a particular memory and memory module based on an address associated with the read request.

At decision block 1708, the logic flow 1700 may include determine whether update configuration information is received. If so, the logic flow 1700 may include perform operations as previous discussed in blocks 1704 and 1706. If not, the logic flow 1700 may include waiting a period of time at block 1710 and then making the determination again at decision block 1708.

The detailed disclosure now turns to providing examples that pertain to further embodiments. Examples one through twenty-five (1-25) provided below are intended to be exemplary and non-limiting.

In a first example, a system, a device, an apparatus, and so forth may include a memory controller, and a memory interface coupled with the memory controller, the memory interface to receive data in parallel via a bus, and convert the received parallel data to send to a memory module of a memory expander sled in serial via a high speed serial link, and receive data in serial via the high speed serial link from the memory module of the memory expander sled, and convert the received serial data to send in parallel to the memory controller via the bus.

In a second example and in furtherance of the first example, a system, a device, an apparatus, and so forth may include the memory interface wherein the memory module is a dual in-line memory module or a integrated circuit.

In a third example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include the memory interface comprising an optical transceiver and the high speed serial link comprising an optical high speed serial link coupled with the memory module.

In a fourth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include the memory interface comprising an electrical transceiver and the high speed serial link comprising an electrical high speed serial link coupled with the memory module.

In a fifth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include the high speed serial link providing a memory channel for communication of data between the memory controller and the memory module.

In a sixth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include a plurality of memory controllers including the memory controller, and a plurality of memory interfaces including the memory interface, each of the plurality of memory interfaces to couple to one of the plurality of memory controllers via buses, each of the plurality of memory interfaces to couple with at least one of a plurality of memory modules including the memory module via at least one of a plurality of high speed serial links including the high speed serial link.

In a seventh example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include each of the high speed serial links to provide one of a plurality of memory channels between one of the memory controllers and one of the memory modules.

In an eighth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include a processing unit comprising the plurality of memory controllers and the plurality of memory interfaces.

In a ninth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include the memory interface to couple with one of a plurality memory modules including the memory module via a circuit switch coupled with the high speed serial link.

In a tenth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include the memory interface comprising serializer/deserializer (SERDES) circuitry to convert data from parallel to serial and serial to parallel.

In an eleventh example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include the memory interface comprising a pig tail connector comprising circuitry to convert data from the parallel to serial and serial to parallel.

In a twelfth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include a memory module, and a memory interface coupled with the memory module. The memory interface to receive data in parallel via a bus, and convert the received parallel data to send to to a memory module of a memory expander sled in serial via a high speed serial link, and receive data in serial via the high speed serial link from the memory module of the memory expander sled, and convert the received serial data to send in parallel to the memory controller via the bus.

In a thirteenth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include the memory interface comprising an optical transceiver and the high speed serial link comprising an optical high speed serial link coupled with the memory controller.

In a fourteenth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include the memory interface comprising an electrical transceiver and the high speed serial link comprising an electrical high speed serial link coupled with the memory controller.

In a fifteenth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include the high speed serial link providing a memory channel for communication of data between the memory controller and the memory module.

In a sixteenth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include a plurality of memory modules including the memory module, and a plurality of memory interfaces including the memory interface, each of the plurality of memory interfaces to couple at least one of the plurality of memory modules with one of a plurality of memory controllers including the memory controller via one of a plurality of high speed serial links including the high speed serial link.

In a seventeenth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include each of the high speed serial links to provide one of a plurality of memory channels between one of the memory controllers and one of the memory modules.

In an eighteenth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include a memory expander sled comprising the plurality of memory modules and the plurality of memory interfaces.

In a nineteenth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth the memory interface to couple the memory module with the memory controller via a circuit switch coupled with the high speed serial link.

In a twentieth example and in furtherance of any of the previous examples, a method may include the memory interface comprising serializer/deserializer (SERDES) circuitry to convert data received in parallel to send in serial to a memory controller, and convert data received in serial from the memory controller to parallel to send to the memory module.

In a twenty-first example and in furtherance of any of the previous examples, a memory expander sled comprising the memory module in a low pin count high speed memory slot, wherein the memory module is byte accessible.

In a twenty-second example and in furtherance of any of the previous examples, a method may include receiving data in parallel via a bus, and convert the received parallel data to send to a memory module of a memory expander sled in serial via a high speed serial link, and receiving data in serial via the high speed serial link from the memory module of the memory expander sled, and convert the received serial data to send in parallel to the memory controller via the bus.

In a twenty-third example and in furtherance of any of the previous examples, a method may include receiving the data from a core in parallel via a high speed parallel link.

In a twenty-fourth example and in furtherance of any of the previous examples, a method may sending the data in serial to the memory module of the memory expander sled via the high speed serial link.

In a twenty-fifth example and in furtherance of any of the previous examples, a method may include wherein the high speed serial link comprising an optical high speed serial link coupling a memory interface with the memory module, the memory interface comprising an optical transceiver to send the data to the memory module; or the high speed serial link comprising an electrical high speed serial link coupling a memory interface with the memory module, the memory interface comprising an electrical transceiver to send the data to the memory module.

Some embodiments may be described using the expression “one embodiment” or “an embodiment” along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment. Further, some embodiments may be described using the expression “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, some embodiments may be described using the terms “connected” and “coupled” to indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

It is emphasized that the Abstract of the Disclosure is provided to allow a reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the preceding Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are at this moment incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein,” respectively. Moreover, the terms “first,” “second,” “third,” and so forth, are used merely as labels and are not intended to impose numerical requirements on their objects.

What has been described above includes examples of the disclosed architecture. It is, of course, not possible to describe every conceivable combination of components and methodologies, but one of ordinary skill in the art may recognize that many further combinations and permutations are possible. Accordingly, the novel architecture is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.

Claims

1. An apparatus, comprising:

a memory controller; and

a memory interface coupled with the memory controller and a memory module, the memory interface to:

receive data in parallel via a bus, and convert the received parallel data to send to a memory module of a memory expander sled in serial via a high speed serial link; and

receive data in serial via the high speed serial link from the memory module of the memory expander sled, and convert the received serial data to send in parallel to the memory controller via the bus.

2. The apparatus of claim 1, wherein the memory module is a dual in-line memory module or a integrated circuit.

3. The apparatus of claim 1, the memory interface comprising an optical transceiver and the high speed serial link comprising an optical high speed serial link coupled with the memory module.

4. The apparatus of claim 1, the memory interface comprising an electrical transceiver and the high speed serial link comprising an electrical high speed serial link coupled with the memory module.

5. The apparatus of claim 1, the high speed serial link providing a memory channel for communication of data between the memory controller and the memory module.

6. The apparatus of claim 1, comprising:

a plurality of memory controllers including the memory controller; and

a plurality of memory interfaces including the memory interface, each of the plurality of memory interfaces to couple to one of the plurality of memory controllers via buses, each of the plurality of memory interfaces to couple with at least one of a plurality of memory modules including the memory module via at least one of a plurality of high speed serial links including the high speed serial link.

7. The apparatus of claim 6, each of the high speed serial links to provide one of a plurality of memory channels between one of the memory controllers and one of the memory modules.

8. The apparatus of claim 6, comprising:

a processing unit comprising the plurality of memory controllers and the plurality of memory interfaces.

9. The apparatus of claim 1, the memory interface to couple with one of a plurality memory modules including the memory module via a circuit switch coupled with the high speed serial link.

10. The apparatus of claim 1, the memory interface comprising serializer/deserializer (SERDES) circuitry to convert data from parallel to serial and serial to parallel.

11. The apparatus of claim 1, the memory interface comprising a pig tail connector comprising circuitry to convert data from the parallel to serial and serial to parallel.

12. An apparatus, comprising:

a memory module; and

a memory interface coupled with the memory module, the memory interface to:

receive data in parallel via a bus, and convert the received parallel data to send to to a memory module of a memory expander sled in serial via a high speed serial link; and

receive data in serial via the high speed serial link from the memory module of the memory expander sled, and convert the received serial data to send in parallel to a memory controller via the bus.

13. The apparatus of claim 12, the memory interface comprising an optical transceiver and the high speed serial link comprising an optical high speed serial link coupled with the memory controller.

14. The apparatus of claim 12, the memory interface comprising an electrical transceiver and the high speed serial link comprising an electrical high speed serial link coupled with the memory controller.

15. The apparatus of claim 12, the high speed serial link providing a memory channel for communication of data between the memory controller and the memory module.

16. The apparatus of claim 12, comprising:

a plurality of memory modules including the memory module; and

a plurality of memory interfaces including the memory interface, each of the plurality of memory interfaces to couple at least one of the plurality of memory modules with one of a plurality of memory controllers including the memory controller via one of a plurality of high speed serial links including the high speed serial link.

17. The apparatus of claim 16, each of the high speed serial links to provide one of a plurality of memory channels between one of the memory controllers and one of the memory modules.

18. The apparatus of claim 16, comprising:

a memory expander sled comprising the plurality of memory modules and the plurality of memory interfaces.

19. The apparatus of claim 12, the memory interface to couple the memory module with the memory controller via a circuit switch coupled with the high speed serial link.

20. The apparatus of claim 12, the memory interface comprising serializer/deserializer (SERDES) circuitry to convert data received in parallel to send in serial to a memory controller, and convert data received in serial from the memory controller to parallel to send to the memory module.

21. The apparatus of claim 12, comprising:

a memory expander sled comprising the memory module in a low pin count high speed memory slot, wherein the memory module is byte accessible.

22. A computer-implemented method, comprising:

receiving data in parallel via a bus, and convert the received parallel data to send to a memory module of a memory expander sled in serial via a high speed serial link; and

receiving data in serial via the high speed serial link from the memory module of the memory expander sled, and convert the received serial data to send in parallel to a memory controller via the bus.

23. The computer-implemented method of claim 22, comprising receiving the data from a core in parallel via a high speed parallel link.

24. The computer-implemented method of claim 22, comprising sending the data in serial to the memory module of the memory expander sled via the high speed serial link.

25. The computer-implemented method of claim 22, the high speed serial link comprising an optical high speed serial link coupling a memory interface with the memory module, the memory interface comprising an optical transceiver to send the data to the memory module; or the high speed serial link comprising an electrical high speed serial link coupling a memory interface with the memory module, the memory interface comprising an electrical transceiver to send the data to the memory module.