Patents by Inventor Cheng-Hang Hsu

Cheng-Hang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11165033
    Abstract: An active device is disposed on a substrate and includes a gate, an organic active layer, a gate insulation layer, a plurality of crystal induced structures, a source and a drain. The gate insulation layer is disposed between the gate and the organic active layer. The crystal induced structures distribute in the organic active layer and directly contact with the substrate or the gate insulation layer. The source and the drain are disposed on two opposite sides of the organic active layer, wherein a portion of the organic active layer is exposed between the source and the drain.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: November 2, 2021
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chao-Hsuan Chen, Cheng-Hang Hsu
  • Publication number: 20200287147
    Abstract: An active device is disposed on a substrate and includes a gate, an organic active layer, a gate insulation layer, a plurality of crystal induced structures, a source and a drain. The gate insulation layer is disposed between the gate and the organic active layer. The crystal induced structures distribute in the organic active layer and directly contact with the substrate or the gate insulation layer. The source and the drain are disposed on two opposite sides of the organic active layer, wherein a portion of the organic active layer is exposed between the source and the drain.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 10, 2020
    Applicant: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chao-Hsuan Chen, Cheng-Hang Hsu
  • Patent number: 10656445
    Abstract: A display device includes a transparent cover, a photovoltaic conversion layer, a display module, and a planarization layer. The transparent cover has a visible region and an edge region that surrounds the visible region. The photovoltaic conversion layer is located on the edge region of the transparent cover. A stage difference is formed by the photovoltaic conversion layer and the visible region of the transparent cover. The display module is electrically connected to the photovoltaic conversion layer. The planarization layer is located between the display module and the photovoltaic conversion layer, and is located between the display module and the visible region of the transparent cover. The thickness of the planarization layer is greater than the stage difference.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 19, 2020
    Assignee: E Ink Holdings Inc.
    Inventors: Chia-I Liu, Cheng-Hang Hsu, Hsin-Tao Huang
  • Publication number: 20200098549
    Abstract: A plasma processing chamber includes a chamber body and a lid assembly coupled to the chamber body to define a processing volume. The lid assembly includes a backing plate coupled to the chamber body, a diffuser with a plurality of openings formed therethrough, and a heat conductive spacer disposed between and coupled to the backing plate and the diffuser to transfer heat from the diffuser to the backing plate. The plasma processing chamber further includes a substrate support disposed within the processing volume.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Beom Soo PARK, Robin L. TINER, Jianheng LI, Sang Jeong OH, Lai ZHAO, Gaku FURUTA, Soo Young CHOI, Jeevan Prakash SEQUEIRA, Wei-Ting CHEN, Hsiao-Ling YANG, Cheng-Hang HSU, Won Ho SUNG, Hyun Young HONG
  • Patent number: 10263089
    Abstract: A transistor including a substrate, a gate layer, a first insulating layer, an active layer, a source and a drain is provided. The gate layer is disposed on the first insulating layer, and has a plurality of first through holes. The first insulating layer covers the gate layer and a part of the substrate exposed by the first through holes, and forms a plurality of recesses respectively corresponding to the first through holes. The active layer is disposed on the first insulating layer, and has a plurality of second through holes. The second through holes communicate with the recesses, respectively. The source is disposed on a part of the active layer. The drain is disposed on another part of the active layer. A manufacturing method of the transistor is also provided.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: April 16, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chia-Wei Chou, Cheng-Hang Hsu
  • Patent number: 10026919
    Abstract: An organic light-emitting device includes a first electrode, a first light-emitting layer, a first low work function layer, a second low work function layer, a conductive etching-resistant layer, a first hole-injection layer, a second light-emitting layer, and a second electrode. The first light-emitting layer is disposed over the first electrode. The first low work function layer is disposed over the first light-emitting layer. The second low work function layer is disposed over the first low work function layer, and a work function of the second low work function layer is greater than a work function of the first low work function layer. The conductive etching-resistant layer is disposed over the second low work function layer. The first hole-injection layer is disposed over the conductive etching-resistant layer. The second light-emitting layer is disposed over the first hole-injection layer. The second electrode is disposed over the second light-emitting layer.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 17, 2018
    Assignee: E Ink Holdings Inc.
    Inventors: Hsin-Fei Meng, Sheng-Fu Horng, Hsiao-Wen Zan, Hao-Wen Chang, Cheng-Hang Hsu
  • Publication number: 20180076402
    Abstract: A method of forming a transistor includes: forming a stack structure including a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer on a substrate; patterning the first insulating layer, the second conductive layer, and the second insulating layer to form at least one opening passing through the first insulating layer, the second conductive layer, and the second insulating layer; forming a semiconductor layer over the second insulating layer and filling the opening; removing the portion of the semiconductor layer over the second insulating layer, in which the portion of the semiconductor layer filled in the opening constitutes at least one semiconductor channel; and forming a third conductive layer over the semiconductor channel.
    Type: Application
    Filed: April 5, 2017
    Publication date: March 15, 2018
    Inventors: Hsiao-Wen ZAN, Shao-Fu PENG, Cheng-Hang HSU
  • Patent number: 9917268
    Abstract: A method of forming a transistor includes: forming a stack structure including a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer on a substrate; patterning the first insulating layer, the second conductive layer, and the second insulating layer to form at least one opening passing through the first insulating layer, the second conductive layer, and the second insulating layer; forming a semiconductor layer over the second insulating layer and filling the opening; removing the portion of the semiconductor layer over the second insulating layer, in which the portion of the semiconductor layer filled in the opening constitutes at least one semiconductor channel; and forming a third conductive layer over the semiconductor channel.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: March 13, 2018
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Shao-Fu Peng, Cheng-Hang Hsu
  • Publication number: 20180069188
    Abstract: An organic light-emitting device includes a first electrode, a first light-emitting layer, a first low work function layer, a second low work function layer, a conductive etching-resistant layer, a first hole-injection layer, a second light-emitting layer, and a second electrode. The first light-emitting layer is disposed over the first electrode. The first low work function layer is disposed over the first light-emitting layer. The second low work function layer is disposed over the first low work function layer, and a work function of the second low work function layer is greater than a work function of the first low work function layer. The conductive etching-resistant layer is disposed over the second low work function layer. The first hole-injection layer is disposed over the conductive etching-resistant layer. The second light-emitting layer is disposed over the first hole-injection layer. The second electrode is disposed over the second light-emitting layer.
    Type: Application
    Filed: August 31, 2017
    Publication date: March 8, 2018
    Inventors: Hsin-Fei MENG, Sheng-Fu HORNG, Hsiao-Wen ZAN, Hao-Wen CHANG, Cheng-Hang HSU
  • Publication number: 20180031884
    Abstract: A display device includes a transparent cover, a photovoltaic conversion layer, a display module, and a planarization layer. The transparent cover has a visible region and an edge region that surrounds the visible region. The photovoltaic conversion layer is located on the edge region of the transparent cover. A stage difference is formed by the photovoltaic conversion layer and the visible region of the transparent cover. The display module is electrically connected to the photovoltaic conversion layer. The planarization layer is located between the display module and the photovoltaic conversion layer, and is located between the display module and the visible region of the transparent cover. The thickness of the planarization layer is greater than the stage difference.
    Type: Application
    Filed: May 17, 2017
    Publication date: February 1, 2018
    Inventors: Chia-I LIU, Cheng-Hang HSU, Hsin-Tao HUANG
  • Publication number: 20170133607
    Abstract: A transistor structure disposed on a substrate includes a gate electrode, an organic semiconductor layer, a gate insulation layer and a patterned metal layer. The gate insulation layer is disposed between the gate and the organic semiconductor layer. The patterned metal layer has a conductive oxidation surface and is divided into a source electrode and a drain electrode. A portion of the organic semiconductor layer is exposed between the source electrode and the drain electrode. The conductive oxidation surface directly contacts with the organic semiconductor layer.
    Type: Application
    Filed: January 19, 2017
    Publication date: May 11, 2017
    Applicant: E Ink Holdings Inc.
    Inventors: Cheng-Hang Hsu, Henry Wang, Chih-Hsuan Wang, Ted-Hong Shinn
  • Patent number: 9577091
    Abstract: A vertical transistor and a manufacturing method thereof are provided herein. The manufacturing method includes forming a first patterned conductive layer on a substrate; forming a patterned metal oxide layer on the first patterned conductive layer, in which the patterned metal oxide layer includes a first patterned insulator layer, a second patterned insulator layer, and a second patterned conductive layer; forming a semiconductor layer; and forming a third patterned conductive layer. The first patterned insulator layer, the second patterned insulator layer, and the second patterned conductive layer are made by using a single metal oxide material. The oxygen concentration of the second patterned conductive layer is different from the oxygen concentrations of the first patterned insulator layer and the second patterned insulator layer.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: February 21, 2017
    Assignee: E Ink Holdings Inc.
    Inventors: Chia-Chun Yeh, Wei-Tsung Chen, Cheng-Hang Hsu, Ted-Hong Shinn
  • Publication number: 20170012227
    Abstract: An active device is disposed on a substrate and includes a gate, an organic active layer, a gate insulation layer, a plurality of crystal induced structures, a source and a drain. The gate insulation layer is disposed between the gate and the organic active layer. The crystal induced structures distribute in the organic active layer and directly contact with the substrate or the gate insulation layer. The source and the drain are disposed on two opposite sides of the organic active layer, wherein a portion of the organic active layer is exposed between the source and the drain.
    Type: Application
    Filed: April 12, 2016
    Publication date: January 12, 2017
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chao-Hsuan Chen, Cheng-Hang Hsu
  • Publication number: 20160126356
    Abstract: An active device circuit substrate includes a substrate, a plurality of active devices, and a first planarization layer. Each active device includes a gate electrode, a channel layer stacked with the gate electrode, a source electrode, and a drain electrode. The source electrode and the drain electrode are disposed on the channel layer and located on opposite sides of the channel layer to define a channel area of the channel layer. The active devices include a first active device and a second active device. The first active device is disposed between the first planarization layer and the substrate, and the first planarization layer is disposed between the first active device and the second active device. A minimum linear distance between the channel area of the first active device and the channel area of the second active device along a direction parallel to the substrate is not smaller than 5 ?m.
    Type: Application
    Filed: August 6, 2015
    Publication date: May 5, 2016
    Inventors: Cheng-Hang Hsu, Tzung-Wei Yu, Yu-Lin Hsu, Ted-Hong Shinn
  • Publication number: 20160064499
    Abstract: A transistor including a substrate, a gate layer, a first insulating layer, an active layer, a source and a drain is provided. The gate layer is disposed on the first insulating layer, and has a plurality of first through holes. The first insulating layer covers the gate layer and a part of the substrate exposed by the first through holes, and forms a plurality of recesses respectively corresponding to the first through holes. The active layer is disposed on the first insulating layer, and has a plurality of second through holes. The second through holes communicate with the recesses, respectively. The source is disposed on a part of the active layer. The drain is disposed on another part of the active layer. A manufacturing method of the transistor is also provided.
    Type: Application
    Filed: May 8, 2015
    Publication date: March 3, 2016
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chia-Wei Chou, Cheng-Hang Hsu
  • Patent number: 9274397
    Abstract: A reflective display device includes a drive array substrate, an electrophoretic display film, a reflective optical film and a light source module. The electrophoretic display film is disposed on the drive array substrate and includes a plurality of display mediums. The reflective optical film is disposed on the electrophoretic display film. The light source module is disposed beside the reflective optical film. A light emitting from the light source module is reflected to the electrophoretic display film by the reflective optical film. The light source module includes a plurality of first-color light sources, a plurality of second-color light sources and a plurality of third-color light sources which are switched on in sequence. The reflective display device is in a color display mode when the light source module is turned on. The reflective display device is in a monochrome display mode when the light source module is turned off.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: March 1, 2016
    Assignee: E Ink Holdings Inc.
    Inventors: Cheng-Hang Hsu, Tzung-Wei Yu, Kuan-Yi Lin, Ted-Hong Shinn
  • Publication number: 20150364499
    Abstract: A substrate structure including a flexible substrate, a gate line, a gate, an inorganic insulation layer, a semiconductor layer, a source, a drain, an inorganic passivation layer and an organic insulation layer is provided. The gate is electrically connected to the gate line. The inorganic insulation layer covers the gate and exposes a portion of the flexible substrate. The semiconductor layer is disposed on the inorganic insulation layer and disposed corresponding to the gate. The source and the drain extend from the inorganic insulation layer to the semiconductor layer and expose a portion of the semiconductor layer. The inorganic passivation layer covers portions of the source and the drain and directly contacts to the semiconductor layer exposed by the source and the drain. The organic insulation layer covers the source, the drain, the inorganic passivation layer and the flexible substrate exposed by the inorganic insulation layer.
    Type: Application
    Filed: March 24, 2015
    Publication date: December 17, 2015
    Inventors: Kuan-Yi Lin, Po-Hsin Lin, Fang-An Shu, Cheng-Hang Hsu, Tzung-Wei Yu
  • Patent number: 9147769
    Abstract: A thin film transistor structure including a substrate, a gate, an oxide semiconductor layer, a gate insulation layer, a source, a drain, a silicon-containing light absorption layer and an insulation layer is provided. The gate insulation layer is disposed between the oxide semiconductor layer and the gate. The oxide semiconductor layer and the gate are stacked in a thickness direction. The source and the drain contact the oxide semiconductor layer. A portion of the oxide semiconductor layer without contacting the source and the drain defines a channel region located between the source and the drain. The oxide semiconductor layer is located between the substrate and the silicon-containing light absorption layer. The silicon-containing light absorption layer has a band gap smaller than 2.5 eV. The insulation layer is disposed between the oxide semiconductor layer and the silicon-containing light absorption layer, and in contact with the silicon-containing light absorption layer.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: September 29, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Cheng-Hang Hsu, Tzung-Wei Yu, Wei-Tsung Chen, Ted-Hong Shinn
  • Publication number: 20150137092
    Abstract: A transistor structure disposed on a substrate includes a gate electrode, an organic semiconductor layer, a gate insulation layer and a patterned metal layer. The gate insulation layer is disposed between the gate and the organic semiconductor layer. The patterned metal layer has a conductive oxidation surface and is divided into a source electrode and a drain electrode. A portion of the organic semiconductor layer is exposed between the source electrode and the drain electrode. The conductive oxidation surface directly contacts with the organic semiconductor layer.
    Type: Application
    Filed: September 4, 2014
    Publication date: May 21, 2015
    Inventors: Cheng-Hang Hsu, Henry Wang, Chih-Hsuan Wang, Ted-Hong Shinn
  • Patent number: RE47505
    Abstract: A thin film transistor (TFT) structure includes a metal oxide semiconductor layer, a gate, a source, a drain, a gate insulation layer, and a passivation layer. The metal oxide semiconductor layer has a crystalline surface which is constituted by a plurality of grains separated from one another. An indium content of the grains accounts for at least 50% of all metal elements of the crystalline surface of the metal oxide semiconductor layer. The gate is disposed on one side of the metal oxide semiconductor layer. The source and the drain are disposed on the other side of the metal oxide semiconductor layer. The gate insulation layer is disposed between the gate and the metal oxide semiconductor layer. The passivation layer is disposed on the gate insulation layer, and the crystalline surface of the metal oxide semiconductor layer is in direct contact with the gate insulation layer or the passivation layer.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 9, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Cheng-Hang Hsu, Tzung-Wei Yu, Ted-Hong Shinn