METHOD FOR MANUFACTURING REDISTRIBUTION LAYER
In a method for manufacturing a semiconductor device, a semiconductor substrate having a top surface is provided. A top metal layer is formed in the top surface. A first passivation layer is formed to cover the top metal layer and the top surface. The first passivation layer has a via hole exposing a portion of the top metal layer. A redistribution layer is formed to cover the first passivation layer, the portion of the top metal layer, and a side surface of the via hole. The redistribution layer includes an overhang structure over the via hole. An etching process is performed on the redistribution layer to remove the overhang structure and a portion of the redistribution layer to expose a portion of the first passivation layer. A second passivation layer is formed to cover the redistribution layer and the portion of the first passivation layer.
This application claims priority to U.S. Provisional Application Ser. No. 62/427,938, filed Nov. 30, 2016, which is herein incorporated by reference.
BACKGROUNDThe semiconductor integrated circuit (IC) industry has experienced exponential growth over the last few decades. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
With the continuous decrease in feature size of integrated circuits, a flip chip package technology become more widespread because the flip chip package technology is applicable to very high density I/O connections and has high reliability in interconnects. However, the conventional flip chip package technology has not been entirely satisfactory in every aspect.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.
Terms used herein are only used to describe the specific embodiments, which are not used to limit the claims appended herewith. For example, unless limited otherwise, the term “one” or “the” of the single form may also represent the plural form. The terms such as “first” and “second” are used for describing various devices, areas and layers, etc., though such terms are only used for distinguishing one device, one area or one layer from another device, another area or another layer. Therefore, the first area can also be referred to as the second area without departing from the spirit of the claimed subject matter, and the others are deduced by analogy. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
In a typical process for manufacturing a redistribution layer of a top metal layer or a bonding layer, a redistribution layer depositing on a first passivation layer and covering a redistribution via (RV) hole formed in the first passivation layer has an overhang structure above the redistribution via hole due to poor coverage of the redistribution layer. Therefore, when a second passivation layer is deposited to cover the redistribution layer, voids are formed in the second passivation layer under the overhang structure, and thus resulting in a pinhole fail of a semiconductor device.
Embodiments of the present disclosure are directed to providing a method for manufacturing the semiconductor device, in which a redistribution layer is formed to cover a first passivation layer and a via hole formed in the first passivation layer, and an etching process is performed on the redistribution layer to pattern the redistribution layer into various pads and to remove an overhang structure of the redistribution layer above the via hole. The overhang structure of the redistribution layer is removed to form the redistribution layer having a V-shaped or a U-shaped cavity above the via hole. Therefore, when a second passivation layer is deposited to cover the redistribution layer, the second passivation layer has better coverage, such that no void is formed in the second passivation layer, thereby enhancing reliability of the semiconductor device and increasing yield of the method for manufacturing the semiconductor device.
As shown in
Referring to
As shown in
In some examples, the bottom surface 144 of the cavity 142 is located higher than or leveled with a top surface 136 of the first passivation layer 130. In certain examples, the bottom surface 144 of the cavity 142 is located lower than the top surface 136 of the first passivation layer 130. For example, the redistribution layer 140 may be formed from Al or AlCu.
As shown in
The cavity 142 of the redistribution layer 140 is V-shaped or U-shaped, and the included angle θ between the side surface 146 and the bottom surface 144 of the cavity 142 is equal to about 90 degrees or greater than about 90 degrees, such that the coverage of the second passivation layer 150 is superior, and no void is formed in the second passivation layer 150 within the cavity 142 of the redistribution layer 140, thereby enhancing reliability of the semiconductor device 100.
Referring to
As shown in
As shown in
In some examples, referring to
In some examples, in forming the redistribution bonding pads 238, and removing the overhang structure 234 and the protrusion 236, an etching hard mask layer 240 is formed on the redistribution layer 230. As shown in
Referring to
After the etching mask layer 240 is completed, the etching process is performed on the redistribution layer 230 with the etching mask layer 240 to remove the portions 239, the overhang structure 234, and the protrusion 236 of the redistribution layer 230. The portions 239 of the redistribution layer 230 are removed to form through holes 239a to expose portions 228 of the first passivation layer 220. The overhang structure 234 and the protrusion 236 in the cavity 232 are removed to form the cavity 232 of the redistribution layer 230 being V-shaped or U-shaped. In the embodiments, by forming the first hole 242 of the etching hard mask layer 240 having the diameter d1 being smaller than the diameter d2 of the opening 222a of the via hole 222, removing the overhang structure 234 and the protrusion 236 does not expose the portion 212 of the top metal layer 210. In certain examples, removing the overhang structure 234 and the protrusion 236 does not expose the portion 212 of the top metal layer 210 by controlling the process parameters of the etching process.
After forming the redistribution bonding pads 238, and removing the overhang structure 234 and the protrusion 236 are completed, the etching mask layer 240 is removed by, for example, a stripping technique.
Then, as shown in
The cavity 232 of the redistribution layer 230 is V-shaped or U-shaped, and the included angle φ between the side surface 232a and the bottom surface 232b of the cavity 232 is equal to about 90 degrees or greater than about 90 degrees, such that the second passivation layer 250 has superior coverage for the cavity 232 of the redistribution layer 230, and no void is formed in the second passivation layer 250 within the cavity 232 of the redistribution layer 230, thereby enhancing reliability of the semiconductor device 260.
Referring to
At operation 302, as shown in
At operation 304, referring to
At operation 308, as shown in
In some examples, referring to
In some examples, in forming the redistribution bonding pads 238, and removing the overhang structure 234 and the protrusion 236, an etching hard mask layer 240 is formed on the redistribution layer 230. As shown in
As shown in
Then, the etching process is performed on the redistribution layer 230 with the etching mask layer 240 to remove the portions 239, the overhang structure 234, and the protrusion 236 of the redistribution layer 230. The portions 239 of the redistribution layer 230 are removed to form through holes 239a to expose portions 228 of the first passivation layer 220. The overhang structure 234 and the protrusion 236 in the cavity 232 are removed to form the cavity 232 of the redistribution layer 230 being V-shaped or U-shaped. By forming the first hole 242 of the etching hard mask layer 240 having the diameter d1 being smaller than the diameter d2 of the opening 222a of the via hole 222, removing the overhang structure 234 and the protrusion 236 does not expose the portion 212 of the top metal layer 210. In certain examples, removing the overhang structure 234 and the protrusion 236 does not expose the portion 212 of the top metal layer 210 by controlling the process parameters of the etching process.
After forming the redistribution bonding pads 238, and removing the overhang structure 234 and the protrusion 236 are completed, the etching mask layer 240 is removed by, for example, a stripping technique.
At operation 310, as shown in
In accordance with an embodiment, the present disclosure discloses a method for manufacturing a semiconductor device. In this method, a semiconductor substrate having a top surface is provided. A top metal layer is formed in the top surface of the semiconductor substrate. A first passivation layer is formed to cover the top metal layer and the top surface of the semiconductor substrate, in which the first passivation layer is formed to have at least one via hole exposing at least one portion of the top metal layer. A redistribution layer is formed to cover the first passivation layer, the at least one portion of the top metal layer, and a side surface of the at least one via hole, in which the redistribution layer is formed to include at least one overhang structure over the at least one via hole. An etching process is performed on the redistribution layer to remove the at least one overhang structure and at least one portion of the redistribution layer, in which the at least one portion of the redistribution layer is removed to expose at least one portion of the first passivation layer. A second passivation layer is formed to cover the redistribution layer and the at least one portion of the first passivation layer.
In accordance with another embodiment, the present disclosure discloses a method for manufacturing a semiconductor device. In this method, a semiconductor substrate having a top surface is provided. A top metal layer is formed in the top surface of the semiconductor substrate. A first passivation layer is formed to cover the top metal layer and the top surface of the semiconductor substrate, in which the first passivation layer is formed to have at least one via hole exposing at least one portion of the top metal layer. A redistribution layer is formed to cover the first passivation layer, the at least one portion of the top metal layer, and a side surface of the at least one via hole, in which forming the redistribution layer forms the redistribution layer having at least one cavity over the at least one via hole, and the redistribution layer is formed to include at least one overhang structure on a side surface of the at least one cavity. An etching mask layer is formed on the redistribution layer, in which the etching mask layer is formed to have at least one first hole exposing the at least one cavity and at least one second hole exposing at least one portion of the redistribution layer. An etching process is performed on the redistribution layer with the etching mask layer to remove the at least one overhang structure and the at least one portion of the redistribution layer, in which the at least one portion of the redistribution layer is removed to expose at least one portion of the first passivation layer. The etching mask layer is removed. A second passivation layer is formed to cover the redistribution layer, the at least one cavity, and the at least one portion of the first passivation layer.
In accordance with yet another embodiment, the present disclosure discloses a semiconductor device. The semiconductor device includes a semiconductor substrate, a top metal layer, a first passivation layer, a redistribution layer, and a second passivation layer. The semiconductor substrate has a top surface. The top metal layer is disposed in the top surface of the semiconductor substrate. The first passivation layer covers the top metal layer and the top surface of the semiconductor substrate, in which the first passivation layer has at least one via hole exposing at least one portion of the top metal layer. The redistribution layer covers the first passivation layer, the at least one portion of the top metal layer, and a side surface of the at least one via hole, in which the redistribution layer has at least one cavity over the at least one via hole, the at least one cavity is V-shaped or U-shaped, and a bottom surface of the at least one cavity is located higher than or leveled with a top surface of the first passivation layer. The second passivation layer covers the redistribution layer and the at least one cavity.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A method for manufacturing a semiconductor device, the method comprising:
- providing a semiconductor substrate having a top surface;
- forming a top metal layer in the top surface of the semiconductor substrate;
- forming a first passivation layer to cover the top metal layer and the top surface of the semiconductor substrate, wherein the first passivation layer is formed to have at least one via hole exposing at least one portion of the top metal layer;
- forming a redistribution layer to cover the first passivation layer, said at least one portion of the top metal layer, and a side surface of the at least one via hole, wherein the redistribution layer is formed to comprise at least one overhang structure over the at least one via hole;
- performing an etching process on the redistribution layer to remove the at least one overhang structure and at least one portion of the redistribution layer, wherein said at least one portion of the redistribution layer is removed to expose at least one portion of the first passivation layer; and
- forming a second passivation layer to cover the redistribution layer and said at least one portion of the first passivation layer.
2. The method of claim 1, wherein each of the first passivation layer and the second passivation layer is formed from silicon oxide, silicon nitride, or silicon oxynitride.
3. The method of claim 1, wherein forming the redistribution layer is performed by a sputtering process.
4. The method of claim 1, wherein forming the redistribution layer forms the redistribution layer having at least one cavity over the at least one via hole, and the at least one overhang structure is located on a side surface of the at least one cavity.
5. The method of claim 4, wherein forming the redistribution layer forms the redistribution layer having at least one protrusion on a bottom surface of the at least one cavity.
6. The method of claim 5, wherein performing the etching process removes the at least one protrusion.
7. The method of claim 4, wherein performing the etching process forms an included angle between the side surface and a bottom surface of the at least one cavity, and the included angle is substantially equal to 90 degrees or greater than 90 degrees.
8. The method of claim 4, wherein performing the etching process further forms the at least one cavity being V-shaped or U-shaped.
9. The method of claim 4, wherein forming the redistribution layer forms a bottom surface of the at least one cavity which is located higher than or leveled with a top surface of the first passivation layer, and the bottom surface of the at least one cavity is formed to be a concave surface.
10. A method for manufacturing a semiconductor device, the method comprising:
- providing a semiconductor substrate having a top surface;
- forming a top metal layer in the top surface of the semiconductor substrate;
- forming a first passivation layer to cover the top metal layer and the top surface of the semiconductor substrate, wherein the first passivation layer is formed to have at least one via hole exposing at least one portion of the top metal layer;
- forming a redistribution layer to cover the first passivation layer, said at least one portion of the top metal layer, and a side surface of the at least one via hole, wherein forming the redistribution layer forms the redistribution layer having at least one cavity over the at least one via hole, and the redistribution layer is formed to comprise at least one overhang structure on a side surface of the at least one cavity;
- forming an etching mask layer on the redistribution layer, wherein the etching mask layer is formed to have at least one first hole exposing the at least one cavity and at least one second hole exposing at least one portion of the redistribution layer;
- performing an etching process on the redistribution layer with the etching mask layer to remove the at least one overhang structure and said at least one portion of the redistribution layer, wherein said at least one portion of the redistribution layer is removed to expose at least one portion of the first passivation layer;
- removing the etching mask layer; and
- forming a second passivation layer to cover the redistribution layer, the at least one cavity, and the at least one portion of the first passivation layer.
11. The method of claim 10, wherein forming the redistribution layer is performed by a sputtering process.
12. The method of claim 10, wherein forming the redistribution layer forms the redistribution layer having at least one protrusion on a bottom surface of the at least one cavity.
13. The method of claim 12, wherein performing the etching process removes the at least one protrusion.
14. The method of claim 12, wherein performing the etching process forms an included angle between the side surface and a bottom surface of the at least one cavity, and the included angle is substantially equal to 90 degrees or greater than 90 degrees.
15. The method of claim 10, wherein performing the etching process further forms the at least one cavity being V-shaped or U-shaped.
16. The method of claim 10, wherein the at least one first hole is formed to have a diameter which is smaller than a diameter of an opening of the at least one via hole.
17. The method of claim 10, wherein forming the redistribution layer forms a bottom surface of the at least one cavity which is located higher than or leveled with a top surface of the first passivation layer.
18-20. (canceled)
21. A method for manufacturing a semiconductor device, the method comprising:
- forming a top metal layer in a top surface of a semiconductor substrate;
- forming a first passivation layer to cover a first portion of the top metal layer and the top surface of the semiconductor substrate, wherein the first passivation layer is formed to expose a second portion of the top metal layer;
- forming a redistribution layer to cover the first passivation layer and said second portion of the top metal layer, wherein the redistribution layer is formed to comprise at least one overhang structure over said second portion of the top metal layer;
- performing an etching process to remove the at least one overhang structure and at least one portion of the redistribution layer, wherein said at least one portion of the redistribution layer is removed to expose at least one portion of the first passivation layer; and
- forming a second passivation layer to cover the redistribution layer and said at least one portion of the first passivation layer.
22. The method of claim 21, wherein forming the redistribution layer forms the redistribution layer having at least one cavity over said second portion of the top metal layer.
23. The method of claim 22, wherein forming the redistribution layer forms a bottom surface of the at least one cavity which is located higher than or leveled with a top surface of the first passivation layer.
Type: Application
Filed: Jan 13, 2017
Publication Date: May 31, 2018
Inventors: Szu-Hsien LU (Tainan City), Chiang-Ming Chuang (Changhua County)
Application Number: 15/405,384