Patents by Inventor Chiang-Ming Chuang
Chiang-Ming Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11925017Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.Type: GrantFiled: January 13, 2020Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
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Patent number: 11764285Abstract: Provided is a method of manufacturing a semiconductor device including: providing a substrate having a memory cell region and a logic region; forming a plurality of stack structures on the substrate in the memory cell region; forming a polysilicon layer to cover the plurality of stack structures and the substrate in the logic region; performing a chemical-mechanical polishing (CMP) process on the polysilicon layer to expose top surfaces of the plurality of stack structures; and after performing the CMP process, patterning the polysilicon layer to form an erase gate between adjacent two stack structures and form a logic gate on the substrate in the logic region, wherein the logic gate has a topmost top surface lower than a topmost top surface of the erase gate.Type: GrantFiled: June 23, 2022Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chuan Lin, Chiang-Ming Chuang, Shang-Yen Wu
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Publication number: 20220320315Abstract: Provided is a method of manufacturing a semiconductor device including: providing a substrate having a memory cell region and a logic region; forming a plurality of stack structures on the substrate in the memory cell region; forming a polysilicon layer to cover the plurality of stack structures and the substrate in the logic region; performing a chemical-mechanical polishing (CMP) process on the polysilicon layer to expose top surfaces of the plurality of stack structures; and after performing the CMP process, patterning the polysilicon layer to form an erase gate between adjacent two stack structures and form a logic gate on the substrate in the logic region, wherein the logic gate has a topmost top surface lower than a topmost top surface of the erase gate.Type: ApplicationFiled: June 23, 2022Publication date: October 6, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chuan Lin, Chiang-Ming Chuang, Shang-Yen Wu
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Patent number: 11411097Abstract: Provided is a semiconductor device including a substrate, a plurality of memory cells, and at least one dummy gate structure. The substrate has a memory cell region and a dummy region. The memory cells are disposed on the substrate in the memory cell region. Each memory cell includes: adjacent two stack structures disposed on the substrate; two select gates respectively disposed outside the adjacent two stack structures; and an erase gate disposed between the adjacent two stack structures. The erase gate has a step between a topmost top surface and a lowermost top surface of the erase gate. The at least one dummy gate structure is disposed on the substrate in the dummy region.Type: GrantFiled: October 12, 2020Date of Patent: August 9, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chuan Lin, Chiang-Ming Chuang, Shang-Yen Wu
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Patent number: 11121141Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.Type: GrantFiled: May 6, 2019Date of Patent: September 14, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
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Patent number: 11018233Abstract: The present disclosure relates to a flash memory cell that includes a substrate and a floating gate structure over the substrate. The floating gate structure includes a first portion having a first top surface and a first thickness. The floating gate structure also includes a second portion having a second top surface and a second thickness that is different from the first thickness. The floating gate structure further includes a sidewall surface connecting the first and second top surfaces, and an angle between the first top surface and the sidewall surface of the floating gate structure is an obtuse angle. The flash memory cell also includes a control gate structure over the first and second portions of the floating gate structure.Type: GrantFiled: May 15, 2020Date of Patent: May 25, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hsien Chu, Chiang-Ming Chuang, Cheng-Huan Chung
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Publication number: 20210043752Abstract: Provided is a semiconductor device including a substrate, a plurality of memory cells, and at least one dummy gate structure. The substrate has a memory cell region and a dummy region. The memory cells are disposed on the substrate in the memory cell region. Each memory cell includes: adjacent two stack structures disposed on the substrate; two select gates respectively disposed outside the adjacent two stack structures; and an erase gate disposed between the adjacent two stack structures. The erase gate has a step between a topmost top surface and a lowermost top surface of the erase gate. The at least one dummy gate structure is disposed on the substrate in the dummy region.Type: ApplicationFiled: October 12, 2020Publication date: February 11, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chuan Lin, Chiang-Ming Chuang, Shang-Yen Wu
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Patent number: 10825914Abstract: A method of manufacturing a semiconductor device includes following steps. The substrate has a dummy region and a memory cell region. A plurality of first stack structures are formed over the substrate in the memory cell region. At least one second stack structure is formed over the substrate in the dummy region. A conductive layer is formed over the substrate to cover the first stack structures and the at least one second stack structure. A planarization process is performed on the conductive layer to expose top surfaces of the first stack structures and the at least one second stack structure. The conductive layer is patterned to form an erase gate between adjacent two first stack structures, and to form first and second select gates outside the adjacent two first stack structures.Type: GrantFiled: November 5, 2018Date of Patent: November 3, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chuan Lin, Chiang-Ming Chuang, Shang-Yen Wu
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Publication number: 20200279930Abstract: The present disclosure relates to a flash memory cell that includes a substrate and a floating gate structure over the substrate. The floating gate structure includes a first portion having a first top surface and a first thickness. The floating gate structure also includes a second portion having a second top surface and a second thickness that is different from the first thickness. The floating gate structure further includes a sidewall surface connecting the first and second top surfaces, and an angle between the first top surface and the sidewall surface of the floating gate structure is an obtuse angle. The flash memory cell also includes a control gate structure over the first and second portions of the floating gate structure.Type: ApplicationFiled: May 15, 2020Publication date: September 3, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hsien CHU, Chiang-Ming CHUANG, Cheng-Huan CHUNG
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Patent number: 10672777Abstract: A method for manufacturing a semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively formed on the silicon substrate and connected to each other. A limiting block is formed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer is formed to blanketly cover the first structure, the second structure and the limiting block, in which the BARC layer includes a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are formed on the external surface of the BARC layer.Type: GrantFiled: February 18, 2019Date of Patent: June 2, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Wei Su, Yung-Lung Hsu, Chih-Hsun Lin, Kun-Tsang Chuang, Chiang-Ming Chuang, Chia-Yi Tseng
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Patent number: 10658479Abstract: The present disclosure relates to a flash memory cell that includes a substrate and a floating gate structure over the substrate. The floating gate structure includes a first portion having a first top surface and a first thickness. The floating gate structure also includes a second portion having a second top surface and a second thickness that is different from the first thickness. The floating gate structure further includes a sidewall surface connecting the first and second top surfaces, and an angle between the first top surface and the sidewall surface of the floating gate structure is an obtuse angle. The flash memory cell also includes a control gate structure over the first and second portions of the floating gate structure.Type: GrantFiled: November 14, 2018Date of Patent: May 19, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hsien Chu, Chiang-Ming Chuang, Cheng-Huan Chung
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Publication number: 20200152648Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.Type: ApplicationFiled: January 13, 2020Publication date: May 14, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
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Patent number: 10535670Abstract: A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.Type: GrantFiled: February 25, 2016Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
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Publication number: 20190259771Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.Type: ApplicationFiled: May 6, 2019Publication date: August 22, 2019Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
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Publication number: 20190181149Abstract: A method for manufacturing a semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively formed on the silicon substrate and connected to each other. A limiting block is formed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer is formed to blanketly cover the first structure, the second structure and the limiting block, in which the BARC layer includes a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are formed on the external surface of the BARC layer.Type: ApplicationFiled: February 18, 2019Publication date: June 13, 2019Inventors: Kuan-Wei SU, Yung-Lung HSU, Chih-Hsun LIN, Kun-Tsang CHUANG, Chiang-Ming CHUANG, Chia-Yi TSENG
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Publication number: 20190148513Abstract: A method of manufacturing a semiconductor device includes following steps. The substrate has a dummy region and a memory cell region. A plurality of first stack structures are formed over the substrate in the memory cell region. At least one second stack structure is formed over the substrate in the dummy region. A conductive layer is formed over the substrate to cover the first stack structures and the at least one second stack structure. A planarization process is performed on the conductive layer to expose top surfaces of the first stack structures and the at least one second stack structure. The conductive layer is patterned to form an erase gate between adjacent two first stack structures, and to form first and second select gates outside the adjacent two first stack structures.Type: ApplicationFiled: November 5, 2018Publication date: May 16, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Chuan Lin, Chiang-Ming Chuang, Shang-Yen Wu
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Publication number: 20190148504Abstract: The present disclosure relates to a flash memory cell that includes a substrate and a floating gate structure over the substrate. The floating gate structure includes a first portion having a first top surface and a first thickness. The floating gate structure also includes a second portion having a second top surface and a second thickness that is different from the first thickness. The floating gate structure further includes a sidewall surface connecting the first and second top surfaces, and an angle between the first top surface and the sidewall surface of the floating gate structure is an obtuse angle. The flash memory cell also includes a control gate structure over the first and second portions of the floating gate structure.Type: ApplicationFiled: November 14, 2018Publication date: May 16, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hsien CHU, Chiang-Ming CHUANG, Cheng-Huan CHUNG
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Patent number: 10283510Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.Type: GrantFiled: September 18, 2017Date of Patent: May 7, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
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Patent number: 10211214Abstract: A semiconductor device having semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively disposed on the silicon substrate and connected to each other. A limiting block is disposed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer blanketly covering the first structure, the second structure and the limiting block, in which the BARC layer comprises a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are disposed on the external surface of the BARC layer.Type: GrantFiled: March 13, 2017Date of Patent: February 19, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Wei Su, Yung-Lung Hsu, Chih-Hsun Lin, Kun-Tsang Chuang, Chiang-Ming Chuang, Chia-Yi Tseng
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Patent number: 10163641Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, and at least one memory cell. The raised dummy feature is present on the semiconductor substrate and defines a cell region and a non-cell region outside of the cell region on the semiconductor substrate, and the raised dummy feature has at least one opening communicating the cell region with the non-cell region. The memory cell is present on the cell region.Type: GrantFiled: August 15, 2016Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Ming Lee, Chiang-Ming Chuang, Kun-Tsang Chuang, Yung-Lung Hsu, Hsin-Chi Chen