Abstract: Provided is a pharmaceutical composition including gastrodin and a use thereof for the prevention or the treatment of amyotrophic lateral sclerosis. The pharmaceutical composition is effective in reducing neuronal axon degeneration and neurofibromin accumulation, improving symptoms of amyotrophic lateral sclerosis and extending life of patients of amyotrophic lateral sclerosis.

Abstract: The present disclosure discloses a method for recycling all types of lithium batteries. First, the lithium battery waste is acid-leached to obtain a solution containing most of metal ions. After filtering, the solution is separated from the remaining solids, and then the obtained solution is subjected to separate precipitation many times. After separately adjusting the pH value of the solution many times, adding precipitants with a high selectivity ratio, and matching with filtration and separation reaction, all ions in the lithium battery waste are sequentially precipitated in forms of iron phosphate (FePO4), aluminum hydroxide (Al(OH)3), manganese oxide (MnO2), dicobalt trioxide (cobalt oxide, Co2O3), nickel hydroxide (Ni(OH)2), and lithium carbonate (Li2CO3).

Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

Abstract: A semiconductor structure includes a substrate with a first surface and a second surface opposite to the first surface, a first and a second shallow trench isolations disposed in the substrate and on the second surface, a deep trench isolation structure in the substrate and coupled to the first shallow trench isolation, a first dielectric layer disposed on the first surface and coupled to the deep trench isolation structure, a second dielectric layer disposed over the first dielectric layer and coupled to the deep trench isolation structure, a third dielectric layer comprising a horizontal portion disposed over the second dielectric layer and a vertical portion coupled to the horizontal portion, and a through substrate via structure penetrating the substrate from the first surface to the second surface and penetrating the second shallow trench isolation.

Abstract: Devices and methods of manufacture for a deep trench layout area-saving semiconductor structure for use with bipolar-CMOS-DMOS (BCD) devices. A semiconductor device may comprise a first BCD device formed within a first perimeter of a first BCD layout area, and a deep trench isolation structure defining the first perimeter of the first BCD layout area, in which the deep trench isolation structure may comprise a first rounded corner that may define a first corner of the first BCD layout area. A semiconductor device may comprise, a substrate, BCD device formed on the substrate, and a deep trench isolation structure laterally surrounding the BCD device. The deep trench isolation structure, with respect to a top-down view, may comprise vertical portions, horizontal portions, a “T”-shaped intersection connecting at least one vertical portion and at least one horizontal portion, and a cross-shaped intersection connecting two vertical portions and two horizontal portions.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: A method for forming alignment keys of a semiconductor structure includes: forming an oxide pad layer and a passivation layer on a substrate; forming a patterned photoresist layer on the passivation layer, and using the patterned photoresist layer as a mask to remove part of the oxide pad layer and passivation layer and expose the substrate surface in the medium voltage and alignment mark regions; forming oxide portions on the exposed substrate surface, and the oxide portions extending into the first depth of the substrate; forming deep doped wells in the low voltage and medium voltage regions; thinning the oxide portions; forming high-voltage doped wells in the high voltage and alignment mark regions; performing an etching process on the high voltage and alignment mark regions to form a second trench, as an alignment key, having a second depth greater than the first depth in the alignment mark region.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: Devices and methods of manufacture for a deep trench layout area-saving semiconductor structure for use with bipolar-CMOS-DMOS (BCD) devices. A semiconductor device may comprise a first BCD device formed within a first perimeter of a first BCD layout area, and a deep trench isolation structure defining the first perimeter of the first BCD layout area, in which the deep trench isolation structure may comprise a first rounded corner that may define a first corner of the first BCD layout area. A semiconductor device may comprise, a substrate, BCD device formed on the substrate, and a deep trench isolation structure laterally surrounding the BCD device. The deep trench isolation structure, with respect to a top-down view, may comprise vertical portions, horizontal portions, a “T”-shaped intersection connecting at least one vertical portion and at least one horizontal portion, and a cross-shaped intersection connecting two vertical portions and two horizontal portions.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: Devices and methods of manufacture for a deep trench layout area-saving semiconductor structure for use with bipolar-CMOS-DMOS (BCD) devices. A semiconductor device may comprise a first BCD device formed within a first perimeter of a first BCD layout area, and a deep trench isolation structure defining the first perimeter of the first BCD layout area, in which the deep trench isolation structure may comprise a first rounded corner that may define a first corner of the first BCD layout area. A semiconductor device may comprise, a substrate, BCD device formed on the substrate, and a deep trench isolation structure laterally surrounding the BCD device. The deep trench isolation structure, with respect to a top-down view, may comprise vertical portions, horizontal portions, a “T”-shaped intersection connecting at least one vertical portion and at least one horizontal portion, and a cross-shaped intersection connecting two vertical portions and two horizontal portions.

Abstract: This application provides a method for detecting images of testing object using hyperspectral imaging. Firstly, obtaining a hyperspectral imaging information according to a reference image, hereby, obtaining corresponded hyperspectral image from an input image and obtaining corresponded feature values for operating Principal components analysis to simplify feature values. Then, obtaining feature images by Convolution kernel, and then positioning an image of an object under detected by a default box and a boundary box from the feature image. By Comparing with the esophageal cancer sample image, the image of the object under detected is classifying to an esophageal cancer image or a non-esophageal cancer image. Thus, detecting an input image from the image capturing device by the convolutional neural network to judge if the input image is the esophageal cancer image for helping the doctor to interpret the image of the object under detected.

Abstract: A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

Abstract: A chip crack detection structure, including a substrate, a first chip crack detection ring, a second chip crack detection ring, and a seal ring, is provided. The first chip crack detection ring includes multiple first conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the first conductive layers is not in contact with any plug. The second chip crack detection ring surrounds the first chip crack detection ring. The second chip crack detection ring includes multiple second conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the second conductive layers is not in contact with any plug. The seal ring surrounds the second chip crack detection ring. The seal ring includes multiple third conductive layers stacked over the substrate and electrically connected to each other.

Abstract: An electronic device including a panel is provided. The panel includes a first substrate, a second substrate opposite to the first substrate, a medium layer disposed between the first substrate and the second substrate, a sealant disposed between the first substrate and the second substrate and surrounding the medium layer, a plurality of first electrodes disposed between the first substrate and the medium layer, and a plurality of connecting lines disposed between the second substrate and the first electrodes. The sealant includes a plurality of conductive particles. The first electrodes are electrically connected to the connection lines through the conductive particles. There is a first space S1 between two adjacent connecting lines of the connecting lines. One of the conductive particles has a width of W. The first space S1 and the width W conform to the following formula: 3<S1/W<20.

Abstract: A chip crack detection structure, including a substrate, a first chip crack detection ring, a second chip crack detection ring, and a seal ring, is provided. The first chip crack detection ring includes multiple first conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the first conductive layers is not in contact with any plug. The second chip crack detection ring surrounds the first chip crack detection ring. The second chip crack detection ring includes multiple second conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the second conductive layers is not in contact with any plug. The seal ring surrounds the second chip crack detection ring. The seal ring includes multiple third conductive layers stacked over the substrate and electrically connected to each other.

Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source/drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate. The first source/drain region is disposed in the first drift region. At least a part of a first portion of the gate oxide layer is disposed between the gate structure and the semiconductor substrate in a vertical direction. A second portion of the gate oxide layer is disposed between the first portion and the first source/drain region in a horizontal direction. The second portion includes a bottom extending downwards and a first concave top surface located above the bottom. A part of the first drift region is located under the first portion and the second portion of the gate oxide layer.