SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
A method of forming a semiconductor structure is disclosed. A substrate is provided with a pad metal and a fuse metal formed thereon. A liner and an etching stop layer are formed at least covering a top surface of the fuse metal. A dielectric layer is formed on the substrate and a passivation layer is formed over the dielectric layer. A pad opening and a fuse opening are defined in the passivation layer. A first etching step is performed to remove the dielectric layer from the pad opening and the fuse opening to expose a top surface of the pad metal from the pad opening and an upper surface of the etching stop layer from the fuse opening respectively. A second etching step is performed to remove the etching stop layer from the fuse opening until an upper surface of the liner is exposed.
The present invention generally relates to a semiconductor device and method of forming the same, and more particularly, to a semiconductor structure including a pad opening and a fuse opening and the method of forming the same.
2. Description of the Prior ArtWith the miniaturization and higher degree of integration of semiconductor devices, semiconductor devices are more vulnerable to defects or impurities arising during manufacturing process. For example, a single deficient spot in the circuitry of a semiconductor chip such as metal discontinuity, via opening or electrical characteristic shifting, may cause the whole chip fail to function.
To eliminate the problem aforesaid, it has been employed extensively in the field to incorporate fuses connecting to redundancy circuitries into the circuitry of a semiconductor chip. When a failure of the chip is defected and recognized, particular fuses may be deleted or opened to re-route circuitry along an alternate pathway, thereby repairing the chip.
Fuse structures are usually made of semiconductor materials such as poly silicon, or metals. Among them, metal fuses are more widely used for their better yield. A metal fuse may be formed integrated with a particular metal layer of the metal interconnection system, for example, one of intermediate metal layers or the last metal layer. After uppermost passivation layers are formed, pad openings are then formed to expose the pad metals for further electrical connection. Meanwhile, fuse openings are also formed to provide accesses to fuse metals.
The bottom of the fuse opening usually includes a dielectric layer covering the top surface of a fuse metals, preventing the fuse metal from being directly exposed, thereby eliminating the risk of corrosion and oxidation. However, the thickness and uniformity of the dielectric layer may interfere with the fusing process. Furthermore, during the process of forming pad openings and fuse openings, photoresist and developing solutions used in photolithography processes may be in direct contact with pad metals or fuse metals, causing residues or metal corrosion.
Accordingly, there is still a need in the field to provide optimized structures and a method of forming pad openings and fuse openings which is able to avoid the aforesaid problems.
SUMMARY OF THE INVENTIONThe objective of the present invention is to provide a semiconductor structure and method of forming the same, wherein pad openings and fuse openings are formed concurrently through a simplified process and the yield may be improved.
According to one aspect of the present invention, a method of forming a semiconductor structure is provided. First, a substrate is provided. At least a pad metal and at least a fuse metal are formed on the substrate. A liner and an etching stop layer are successively formed on the substrate at least covering a top surface of the fuse metal. After that, a dielectric layer is formed completely covering the pad metal and the fuse metal. A passivation layer is formed on the dielectric layer and then patterned to define a pad opening vertically aligned above the pad metal and a fuse opening vertically aligned above the fuse metal. The dielectric layer is exposed from the pad opening and the fuse opening respectively. An etching step having etching selectivity between the dielectric layer and the etching stop layer is then performed to remove the exposed dielectric layer from the pad opening and the fuse opening downwardly until a top surface of the pad metal and an upper surface of the etching stop layer are exposed from the pad opening and the fuse opening respectively. After that, another etching step is performed to remove the exposed etching stop layer from the fuse opening until an upper surface of the liner is exposed.
According to another aspect of the present invention, a semiconductor structure is provided. The semiconductor structure includes a substrate, at least a pad metal and at least a fuse metal formed on the substrate and completely covered by a dielectric layer. A liner and an etching stop layer are formed between the substrate and the dielectric layer and at least cover a top surface of the fuse metal. A passivation layer is formed on the dielectric layer. A fuse opening is disposed vertically aligned above the fuse metal, penetrating through the passivation layer, the dielectric layer and the etching stop layer without penetrating the liner, therefore exposing an upper surface of the liner directly above the fuse metal. A pad opening is disposed vertically aligned above the pad metal, penetrating through the passivation layer and the dielectric layer, exposing a top surface of the pad metal.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:
In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration of specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.
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Subsequently, a liner 22 and an etching stop material layer 24 are formed successively and conformally on the substrate, top surfaces and sidewalls of the pad metal 16 and the fuse metal 18. The etching stop material layer 24 is preferably made of materials different from that of the dielectric layer 32 formed in the following process (shown in
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It is one feature of the present invention that by forming a liner and an etching stop layer selectively covering the top surface of the fuse metal, a pad opening and a fuse opening may be formed concurrently through the same process steps. A thin dielectric layer (the remaining liner 22) may be formed with uniform and well-controlled thickness covering the top surface of the fuse metal, preventing the fuse metal from being exposed to the environment. The risk of corrosion or oxidation of the fuse metal may be therefore avoided and a stable fusing process and better yield may be achieved.
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After that, similarly, a first etching step 42, a second etching step 44 and a third etching step 46 are performed successively, using the patterned passivation layer 36 as an etching mask to remove dielectric materials from the pad opening 36a and the fuse opening 36b downwardly until the pad metal 16 and the liner 22 on the fuse metal 18 are exposed, as shown in
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Similarly, a first etching step 42, a second etching step 44 and a third etching step 46 are then performed, using the patterned passivation layer 36 as an etching mask to etch the dielectric materials from the pad opening 36a and the fuse opening 36b downwardly until the pad metal 16 and the liner 22 on the top surface of the fuse metal 18 are exposed. As shown in
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Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A method of forming a semiconductor structure, comprising:
- providing a substrate;
- forming a pad metal and a fuse metal on the substrate;
- forming a liner and an etching stop layer on the liner and at least covering a top surface of the fuse metal;
- forming a dielectric layer;
- forming a passivation layer on the dielectric layer;
- defining a pad opening and a fuse opening in the passivation layer, wherein the pad opening is vertically aligned above the pad metal, and the fuse opening is vertically aligned above the fuse metal;
- performing a first etching step to remove the dielectric layer from the pad opening and the fuse opening until the pad metal and the etching stop layer are exposed from the pad opening and the fuse opening respectively; and
- performing a second etching stop to remove the exposed etching stop layer from the fuse opening until the liner is exposed.
2. The method of forming a semiconductor structure according to claim 1, wherein the first etching step has an etching selectivity between the dielectric layer and the etching stop layer.
3. The method of forming a semiconductor structure according to claim 1, wherein the liner and the dielectric layer comprise silicon oxide, and the etching stop layer comprises silicon nitride.
4. The method of forming a semiconductor structure according to claim 1, wherein the passivation layer comprises polyimide.
5. The method of forming a semiconductor structure according to claim 1, wherein the pad metal and the fuse metal are formed in the same material layer.
6. The method of forming a semiconductor structure according to claim 5, wherein the step of forming the liner and the etching stop layer comprises:
- forming the liner conformally covering the substrate, the sidewall and the top surface of the pad metal and the sidewall and the top surface fuse metal;
- forming an etching stop material layer on the liner;
- removing a portion of the etching stop material layer vertically above the pad metal, and the remaining etching stop material layer is the etching stop layer.
7. The method of forming a semiconductor structure according to claim 6, wherein another portion of the etching stop material layer on the sidewall of the pad metal is also removed.
8. The method of forming a semiconductor structure according to claim 6, wherein the etching stop material not vertically above the fuse metal is completely removed.
9. The method of forming a semiconductor structure according to claim 1, wherein the pad metal and the fuse metal are formed in different material layers.
10. The method of forming a semiconductor structure according to claim 9, wherein the step of forming the pad metal and the fuse metal on the substrate comprises:
- forming a metal layer on the substrate;
- patterning the metal layer into a wiring metal and the fuse metal;
- forming the liner, the etching stop layer on the liner, and an interlayer dielectric layer on the etching stop layer; and
- forming the pad metal on the interlayer dielectric layer.
11. A semiconductor structure, comprising:
- a substrate comprising a pad metal and a fuse metal formed thereon;
- a liner and an etching stop layer on the liner and at least covering a top surface of the fuse metal;
- a dielectric layer covering the pad metal and the fuse metal;
- a passivation layer on the dielectric layer;
- a pad opening vertically aligned above the pad metal, penetrating through the passivation layer, the dielectric layer and the liner, exposing the pad metal; and
- a fuse metal aligned vertically above the fuse metal, penetrating through the passivation layer, the dielectric layer and the etching stop layer without penetrating through the liner and exposing a surface of the liner.
12. The semiconductor structure according to claim 11, wherein the liner and the dielectric layer comprise silicon oxide, and the etching stop layer comprises silicon nitride.
13. The semiconductor structure according to claim 11, wherein the passivation layer comprises polyimide.
14. The semiconductor structure according to claim 11, wherein the pad metal and the fuse metal are formed in the same material layer.
15. The semiconductor structure according to claim 14, wherein the liner conformally covers the substrate, the top surface and the sidewall of the fuse metal and the sidewall of the pad metal.
16. The semiconductor structure according to claim 14, wherein the etching stop layer is sandwiched between the liner and the dielectric layer and completely separates the liner and the dielectric layer.
17. The semiconductor structure according to claim 14, wherein the etching stop layer further covers the sidewall of the fuse metal, the dielectric layer is in direct contact with the liner on the sidewall of the pad metal while not in direct contact with the liner on the sidewall of the fuse metal.
18. The semiconductor structure according to claim 14, wherein the liner not vertically above the fuse metal is in direct contact with the dielectric layer.
19. The semiconductor structure according to claim 11, wherein the pad metal and the fuse metal are formed in different material layers separated by an interlayer dielectric layer formed therebetween.
20. The semiconductor structure according to claim 19, further comprising a wiring metal formed in the same material layer with the fuse metal, wherein the liner and the etching stop layer cover the sidewall and the top surface of the wiring metal.
Type: Application
Filed: Apr 25, 2017
Publication Date: Sep 27, 2018
Patent Grant number: 10472731
Inventors: Feng-Yi Chang (Tainan City), Fu-Che Lee (Taichung City), Ming-Feng Kuo (Tainan City)
Application Number: 15/497,182