NON-PLANAR METAL-INSULATOR-METAL CAPACITOR FORMATION
A method for forming a semiconductor structure having a non-planar MIM capacitor is provided. The method includes forming a first dielectric layer on a base structure that has one or more recesses each comprising contours formed at two or more planar levels. The first dielectric layer is formed along the contours of the one or more recesses. A first electrode is formed on the first dielectric layer. A second dielectric layer is formed over the first dielectric layer and the first electrode. A second electrode is formed over the second dielectric layer. The first electrode, the second dielectric layer and the second electrode form a non-planar capacitor.
The present invention relates to forming components in semiconductor integrated circuits, and more specifically to forming metal-insulator-metal (MIM) capacitors.
In semiconductor integrated circuits (ICs or chips), a MIM capacitor may typically be formed as a planar capacitor patterned during a middle-of-line (MOL) process or back-end-of-line (BEOL) process. The term BEOL generally refers to the portion of integrated circuit fabrication during which interconnects are formed. However, the planar MIM capacitor can consume a significant amount of chip area in order to achieve a required amount of capacitance. Attempts have been made to increase the capacitance density by reducing the thickness of the dielectric layer formed between top and bottom metal electrodes and by using high dielectric constant materials. However, reducing the dielectric thickness can lead to undesired effects such as increased leakage currents. Additionally, the use of special dielectric materials may not be cost effective.
SUMMARYIllustrative embodiments of the invention provide techniques for fabricating semiconductor structures comprising non-planar MIM capacitors. While illustrative embodiments are well-suited to improve operations of MIM capacitors, alternative embodiments may be implemented with other types of semiconductor structures.
For example, in one illustrative embodiment, a method for fabricating a semiconductor structure comprising a non-planar MIM capacitor is provided. The method comprises forming a first dielectric layer on a base structure that has one or more recesses each comprising contours formed at two or more planar levels. The first dielectric layer is formed along the contours of the one or more recesses. A first electrode is formed on the first dielectric layer. A second dielectric layer is formed over the first dielectric layer and the first electrode. A second electrode is formed over the second dielectric layer. The first electrode, the second dielectric layer and the second electrode form a non-planar capacitor.
Embodiments will now be described in further detail with regard to techniques for forming a non-planar MIM capacitor in a subtractive BEOL process flow. It is to be understood that the various layers, structures, and/or regions shown in the accompanying drawings are schematic illustrations that are not necessarily drawn to scale. In addition, for ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures.
Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be used to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.
Moreover, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, layers, regions, or structures, and thus, a detailed explanation of the same or similar features, elements, layers, regions, or structures will not be repeated for each of the drawings. It is to be understood that the terms “about” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error is present such as, by way of example only, 1% or less than the stated amount. Also, in the figures, the illustrated scale of one layer, structure, and/or region relative to another layer, structure, and/or region is not necessarily intended to represent actual scale.
Before describing illustrative embodiments, a semiconductor structure with a planar MIM capacitor will be described in the context of
Referring now to
MIM capacitor 120 is formed between via 106 and via 112. Via 106 may be connected to a power supply (Vdd) (not shown) through metal lines 104 and 108, while via 112 may be connected to power supply ground (Gnd) (not shown) through metal lines 110 and 114. However, connections to MIM capacitor 120 are not limited to being between power and ground, but may also be between a signal line and ground, a signal line and power, a first signal and a second signal, etc.
In order to increase capacitance, MIM capacitor 120 is formed with top electrode 122 and bottom electrode 124, both connected to via 106, and middle electrode 126 connected to via 112. Middle electrode 126 is stacked in between top electrode 122 and bottom electrode 124 as illustrated in
With reference to
Although the embodiments described in
Generally, the base structure may have one or more recesses each formed at two or more planar levels. As shown in this illustrative example, base structure 205 has four recesses, including recess 225. Referring back to the illustrative example of
It is to be assumed that the base structure shown in
Electrode 232, dielectric layer 234 and electrode 236 form capacitor 238. Capacitor 238 may be referred to as a MIM capacitor, due to the metal-insulator-metal arrangement of electrode 232, dielectric layer 234 and electrode 236. Capacitor 238 is non-planar due to the deposition of each component following the contours of the recesses of the base structure, since the recesses have multiple planar levels.
It is to be understood that the illustrative embodiments of
The embodiments described herein provide for the formation of a non-planar MIM capacitor. Such a non-planar structure provides for an increased surface area of the MIM capacitor over a given region, as compared to a conventional MIM capacitor, such as MIM capacitor 120 depicted in
It is to be understood that the methods discussed herein for fabricating semiconductor structures can be incorporated within semiconductor processing flows for fabricating other types of semiconductor devices and integrated circuits with various analog and digital circuitry or mixed-signal circuitry. In particular, integrated circuit dies can be fabricated with various devices such as transistors, diodes, capacitors, inductors, etc. An integrated circuit in accordance with embodiments can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein.
Furthermore, various layers, regions, and/or structures described above may be implemented in integrated circuits (chips). The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
Although illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in art without departing from the scope or spirit of the invention.
Claims
1. A method comprising:
- forming a first dielectric layer on a base structure, wherein the base structure has one or more recesses each comprising contours formed at two or more planar levels, wherein the base structure comprises:
- a dielectric;
- a first set of base structures formed in the dielectric, the first set of first base structures comprising at least a first base structure, a second base structure and a third base structure; and
- a second set of base structures formed on the dielectric and the first set of base structures, the second set of base structures comprising at least a fourth base structure, a fifth base structure and a sixth base structure, and wherein the first dielectric layer is formed along the contours of the one or more recesses;
- forming a first electrode on the first dielectric layer;
- forming a second dielectric layer over the first dielectric layer and the first electrode; and
- forming a second electrode over the second dielectric layer;
- wherein the first electrode, the second dielectric layer and the second electrode form a non-planar capacitor.
2. The method of claim 1, wherein the first dielectric layer comprises a low-k dielectric material.
3. The method of claim 1, wherein the second dielectric layer comprises a high-k dielectric material.
4. (canceled)
5. The method of claim 1, wherein forming the first electrode comprises depositing a first electrode layer on the first dielectric layer, etching a first portion of the deposited first electrode layer around the fourth base structure, and etching a second portion of the deposited first electrode layer around the fifth base structure.
6. The method of claim 1, wherein forming the second electrode comprises depositing a second electrode layer on the second dielectric layer, etching a first portion of the deposited second electrode layer around the fifth base structure, and etching a second portion of the deposited second electrode layer around the sixth base structure.
7. The method of claim 1, wherein the first base structure comprises a first via having a first surface formed on a first metal line, wherein the second base structure comprises a second via having a first surface formed on a second metal line, and wherein the third base structure comprises a third metal line.
8. The method of claim 7, wherein the fourth base structure comprises a fourth via having a first surface formed on a first surface of a fourth metal line, wherein the fifth base structure comprises a fifth via having a first surface formed on a first surface of a fifth metal line, and wherein the sixth base structure comprises a sixth via having a first surface formed on a first surface of a sixth metal line.
9. The method of claim 8, wherein the fourth metal line is a Vdd line, wherein the fifth metal line is a signal line, and wherein the sixth metal line is a Gnd line.
10. The method of claim 8, wherein the first via has a second surface abutting a second surface of the fourth metal line, and wherein the second via has a second surface formed on a second surface of the fifth metal line.
11. The method of claim 8, further comprising filling the one or more recesses with an insulator after forming the second electrode, and planarizing down the entire structure to the top surfaces of the fourth via, the fifth via and the sixth via.
12. The method of claim 11, further comprising depositing first, second and third metals on each of the fourth, fifth and sixth vias, respectively.
13. The method of claim 12, wherein the first metal makes an electrical connection with the second electrode and the fourth metal line, wherein the second metal makes an electrical connection with the first electrode and the fifth metal line, and wherein the third metal makes an electrical connection with the first electrode and the sixth metal line.
14. The method of claim 1, wherein the one or more recesses of the base structure are formed via a subtractive back-end-of-line process.
15.-20. (canceled)
Type: Application
Filed: Mar 30, 2017
Publication Date: Oct 4, 2018
Inventor: Effendi Leobandung (Stormville, NY)
Application Number: 15/473,782