Patents by Inventor Effendi Leobandung

Effendi Leobandung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220181275
    Abstract: A security key associated with a plurality of programmable switches included in an integrated circuit is received. The plurality of programmable switches are set causing the plurality of programmable switches to be conductive. Reset pulses are applied to a first set of programmable switches included in the plurality of programmable switches based on the received security key.
    Type: Application
    Filed: December 8, 2020
    Publication date: June 9, 2022
    Inventors: Guy M. Cohen, Effendi Leobandung
  • Publication number: 20220181213
    Abstract: Embodiments of the invention are directed to a transistor that includes a source or drain (S/D) region having an S/D formation assistance region, wherein the S/D formation assistance region includes a top surface, sidewalls, and a bottom surface. The S/D formation assistance region is at least partially within a portion of a substrate. An S/D isolation region is formed around the sidewalls and the bottom surface of the S/D formation assistance region and configured to electrically isolate the S/D formation assistance region from the substrate.
    Type: Application
    Filed: February 23, 2022
    Publication date: June 9, 2022
    Inventors: Ruilong Xie, Alexander Reznicek, Effendi Leobandung, Jingyun Zhang
  • Patent number: 11355401
    Abstract: A method of forming a field effect transistor (FET) includes providing a substrate; forming an nFET source/drain region on the substrate; forming a pFET source/drain region on the substrate and adjacent to the nFET region, the nFET source/drain region directly contacting the pFET source/drain region; forming a first insulator layer on the nFET source/drain region and the pFET source/drain region; etching away a portion of the first insulator layer between the nFET source/drain region and the pFET source/drain region down to a level of the substrate, thereby breaking the contact between the nFET source/drain region and the pFET source/drain region; and forming a second insulator layer between the nFET source/drain region and the pFET source/drain region in a space formed by the etching, the second insulator layer extending from the substrate to a top of the first insulator layer. The second insulator layer is harder than the first insulator layer.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: June 7, 2022
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Veeraraghavan S. Basker, Junli Wang, Albert Chu
  • Publication number: 20220163460
    Abstract: A method can include obtaining a first reference image of a first wafer. The method can include obtaining a first image of the first wafer in a fabrication state. The first wafer can have a first verification structure. The method can include obtaining, when the first wafer is in the fabrication state, a first physical measurement. The first physical measurement can correspond to the first verification structure. The method can include determining that the first image matches the first reference image. The method can include obtaining an electrical parameter measurement corresponding to a verification structure of a received wafer in a post-fabrication state. The method can include calculating a physical parameter value based on the electrical parameter measurement. The method can include generating a verification response by comparing the physical parameter value to the first physical measurement.
    Type: Application
    Filed: November 23, 2020
    Publication date: May 26, 2022
    Inventor: Effendi Leobandung
  • Patent number: 11313810
    Abstract: A method for verifying semiconductor wafers includes receiving a semiconductor wafer including a plurality of layers. A first set of measurement data is obtained for at least one layer of the plurality of layers, where the first set of measurement data includes at least one previously recorded thickness measurement for one or more portions of the at least one layer. The first set of measurement data is compared to a second set of measurement data for the at least one layer. The second set of measurement data includes at least one new thickness measurement for the one or more portions of the at least one layer. The semiconductor wafer is determined to be an authentic wafer based on the second set of measurement data corresponding to the first set of measurement data, otherwise the semiconductor is determined to not be an authentic wafer.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: April 26, 2022
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 11309408
    Abstract: A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 19, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Effendi Leobandung, Chun-chen Yeh
  • Patent number: 11301752
    Abstract: Weights of a neural network are initialized by programming a plurality of unit cells. A given one of the plurality of unit cells includes one or more static random-access memory cells and a digital to analog converter device. The digital to analog converter device is configured to receive one or more outputs produced by respective ones of the one or more static random-access memory cells. An amount of error associated with the initialized weights is determined. The initialized weights are adjusted in response to the amount of error exceeding a threshold amount of error.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 11295983
    Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor, wherein the fabrication operations include forming a source or drain (S/D) region having an S/D formation assistance region at least partially within a portion of a substrate. An S/D isolation region is formed around sidewalls and a bottom surface of the S/D formation assistance region and configured to electrically isolate the S/D formation assistance region from the substrate.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: April 5, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Alexander Reznicek, Effendi Leobandung, Jingyun Zhang
  • Publication number: 20220093627
    Abstract: Semiconductor devices and methods of forming the same include forming an etch mask on a stack of alternating dielectric layers and conductor layers. An exposed portion of a dielectric layer and a conductor layer is etched away to form a wordline. The forming and etching steps are repeated, adding additional etch mask material at each iteration, to form respective wordlines at each iteration.
    Type: Application
    Filed: December 6, 2021
    Publication date: March 24, 2022
    Inventor: Effendi Leobandung
  • Patent number: 11271116
    Abstract: A semiconductor device includes a stack of layers stacked vertically and including a source layer, a drain layer and a channel layer between the source layer and the drain layer. A gate electrode is formed in a common plane with the channel layer and a gate dielectric is formed vertically between the gate electrode and the channel layer. A first contact contacts the stack of layers on a first side of the stack of layers, and a second contact formed on an opposite side vertically from the first contact.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: March 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 11250316
    Abstract: Method, systems, crosspoint arrays, and systems for tuning a neural network. A crosspoint array includes: a set of conductive rows, a set of conductive columns intersecting the set of conductive rows to form a plurality of crosspoints, a circuit element coupled to each of the plurality of crosspoints configured to store a weight of the neural network, a voltage source associated with each conductive row, a first integrator attached at the end of at least one of the conductive column, and a first variable resistor attached to the integrator and the end of the at least one conductive column.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: February 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Zhibin Ren, Seyoung Kim, Paul Michael Solomon
  • Patent number: 11243063
    Abstract: The wafer comprises a first line in a first layer of the wafer. The first line has a first terminal connected to the first line. The wafer comprises a second line in the first layer of the wafer. The second line has a second terminal connected to the second line. The second terminal has a probe connected to apply a voltage ramp. The wafer comprises a third line in the first layer of the wafer. The third line has a terminal connected to the third line.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: February 8, 2022
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 11239369
    Abstract: A semiconductor device includes a stack of layers stacked vertically and including a source layer, a drain layer and a channel layer between the source layer and the drain layer. A gate electrode is formed in a common plane with the channel layer and a gate dielectric is formed vertically between the gate electrode and the channel layer. A first contact contacts the stack of layers on a first side of the stack of layers, and a second contact formed on an opposite side vertically from the first contact.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: February 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 11227212
    Abstract: Semiconductor devices and methods of forming the same include forming a drain/gate contact, in an opening of a layer of dielectric material, that includes a portion that extends up along sidewalls of the opening. A drain layer is formed on a bottom surface of the drain/gate contact. A trapped insulator layer is formed on sidewalls of the drain/gate contact. A channel layer is formed in the opening. A source layer is formed on the channel layer.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: January 18, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Publication number: 20220013519
    Abstract: Interposer-less multi-chip module are provided. In one aspect, an interposer-less multi-chip module includes: a substrate; a base film disposed on the substrate; and chips pressed into the base film, wherein top surfaces of the chips are coplanar. For instance, the chips can have varying thicknesses and are pressed into the base film to different depths such that top surfaces of the chips are coplanar. An interconnect layer having back-end-of line (BEOL) metal wiring can be present on the wafer over the chips. Methods of forming an interposer-less multi-chip module are also provided.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 13, 2022
    Inventor: Effendi Leobandung
  • Patent number: 11211390
    Abstract: Semiconductor devices and methods of forming the same include forming an etch mask on a stack of alternating dielectric layers and conductor layers. An exposed portion of a dielectric layer and a conductor layer is etched away to form a wordline. The forming and etching steps are repeated, adding additional etch mask material at each iteration, to form respective wordlines at each iteration.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: December 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 11195842
    Abstract: A method of forming a semiconductor structure includes forming a wordline stack for a non-volatile memory structure over a capping layer, the wordline stack including sets of alternating layers of insulating and gate materials each having a different width. The method also includes forming a first bitline contact layer between first and second portions of the wordline stack each including at least one of the sets. The method further includes forming a floating gate device structure vertically in a channel hole through the wordline stack, the first bitline contact layer and the capping layer. The method further includes forming wordline contacts to the gate layers and a first bitline contact to the first bitline contact layer in holes paced apart from vertical sidewalls of the floating gate device structure, and forming a second bitline contact over at least a portion of a top surface of the floating gate device structure.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Publication number: 20210375685
    Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor, wherein the fabrication operations include forming a source or drain (S/D) region having an S/D formation assistance region at least partially within a portion of a substrate. An S/D isolation region is formed around sidewalls and a bottom surface of the S/D formation assistance region and configured to electrically isolate the S/D formation assistance region from the substrate.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Inventors: Ruilong Xie, Alexander Reznicek, Effendi Leobandung, Jingyun Zhang
  • Patent number: 11183419
    Abstract: Embodiments of the present invention are directed to fabrication methods and resulting semiconductor structures having a bulb-shaped buried interconnect positioned below a shallow trench isolation region. In a non-limiting embodiment of the invention, a cavity is formed below a surface of a substrate. The cavity extends under a portion of a semiconductor fin. The cavity is filled with a sacrificial material and a shallow trench isolation region is formed on the sacrificial material in the cavity. A portion of the shallow trench isolation region is removed to expose a surface of the sacrificial material in the cavity. The sacrificial material is removed from the cavity and replaced with a buried interconnect.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: November 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 11176451
    Abstract: Systems and methods for a capacitor based resistive processing unit with symmetrical weight updating include a first capacitor that stores a charge corresponding to a weight value. A readout circuit reads the charge stored in the first capacitor to apply a weight to an input value corresponding to an input signal using the weight value to produce an output. An update circuit updates the weight value stored in the first capacitor, including a second capacitor in communication with the first capacitor to transfer an amount of charge to the first capacitor according to an error of the output by changing a voltage difference across the first capacitor by a voltage change corresponding to the amount of charge, the voltage difference corresponding to the charge stored in the first capacitor.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yulong Li, Paul M. Solomon, Effendi Leobandung