INTEGRATED GALLIUM NITRIDE POWER AMPLIFIER AND SWITCH
A multi-band RF power amplifier circuit fabricated using GaN technology includes a RF power amplifier coupled to a multi-band RF switch without an intervening impedance matching network between the RF power amplifier and the multi-band RF switch. The multi-band RF switch includes a plurality of Unit HEMT cells. In one IC package, the RF power amplifier, the multi-band RF switch, a controller for controlling the switch and all connection therebetween are totally contained within the IC package. In another IC package, the RF power amplifier and the multi-band RF switch are disposed on a single substrate.
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This invention relates generally to active solid-state devices, and more specifically to a gallium nitride radio frequency power amplifier and a gallium nitride multi-band radio frequency switch.
Related ArtA gallium nitride (hereinafter “GaN”) high-electron-mobility transistor (hereinafter “HEMT”) is a depletion mode device, which is normally on, that may be used as a switch.
The multi-band power amplifier circuit 100 includes a transformer 106 between the PA-FET 104 and the multi-band RF switch 102. The transformer acts as a wideband matching network. The transformer 106 is typically a transmission line transformer. For practical construction purposes, the transformer 106 typically transforms 12.5Ω to 50Ω. The transformer 106 could also be a lumped-element matching network. The transformer 106 is needed because an optimum load impedance of the PA-FET 104 is not son. The optimum load impedance of the PA-FET 104 is approximately 30Ω. The transformer 106 transforms an impedance (usually 30Ω) seen at a drain terminal of the PA-FET 104 to an impedance (usually 50Ω) needed to optimally drive filters 111 and 112 and an antenna (not shown) at each PA_Out port 121 and 122. There is no reference impedance associated with the switch 102. The presence of the transformer 106 prevents a direct connection between the PA-FET 104 and the multi-band RF switch 102. Disadvantageously, the transformer 106 is physically large, because it usually consists of multiple transmission lines which must be surrounded by magnetic material, or be at least approximately ⅛ wavelength at the lowest operating frequency. As a result of its large size, the transformer 130 cannot be housed in an IC package, such as an IC package (not shown) that houses the PA-FET 104 or an IC package (not shown) that houses the multi-band RF switch 102. Consequently, any indirect connection between the PA-FET 104 and the multi-band RF switch 102 must disadvantageously exist at least partially outside all known IC packages within which the PA-FET and the multi-band RF switch may be mounted.
A capacitor 108 is coupled between the drain of the PA-FET 104 and an input terminal of the transformer 106. The capacitor 108 prevents a DC voltage of a power supply from appearing at circuitry coupled to an output terminal of the transformer 106, which circuitry could contain paths to ground that would draw unnecessary current from the DC supply. The capacitor 108 may not be present if the transformer element provides its own DC isolation function.
The multi-band RF switch 102 is coupled between the transformer 106 and a plurality of filters 111 and 112 and selectively couples an output of the transformer to one of the plurality of filters. The filters 111 and 112 are typically lowpass or bandpass filters and are used to prevent harmonic and spurious signals outside a selected frequency band from reaching a PA_Out port 121 and a PA_Out port 122. Each filter 111 and 112 is tuned to pass a specific range of frequencies, as required by a radio system that uses the known multi-band power amplifier circuit 100.
A low power RF signal is applied to a PA_In port 124 which is coupled to an input port of an input matching circuit 126. Typically, the input matching circuit 126 comprises lumped elements. The input matching circuit 126 transforms an impedance (usually 50Ω) seen at the PA_In port 124 to a range of impedances needed to optimally drive a gate of the PA-FET 104 across the operating frequency range of PA 100. An output port of the input matching circuit 126 also provides a direct current (hereinafter “DC”) bias to the gate of the PA-FET 104.
A DC supply voltage is applied to a DC_In port 128. An inductor 130 is coupled between the DC_In port 128 and the drain of the PA-FET 104. An amplified RF voltage appears at the drain of the PA-FET 104. The inductor 130 isolates the RF voltage at the drain of the PA-FET 104 from the DC supply voltage so that a very low impedance of the DC power supply does not affect the amplified RF voltage.
The multi-band RF switch 102 can be one of many multi-band RF switches available from various manufacturers. The multi-band RF switch 102 shown in
All known multi-band power amplifier circuits that operate at frequencies below 2GHz include a transformer, such a transformer 106. Disadvantageously, the transformer 106 of the multi-band power amplifier circuit 100 is physically large, because it usually consists of multiple transmission lines which are surrounded by magnetic material, or be at least approximately ⅛ wavelength at the lowest operating frequency. The transformer 106 of the known multi-band power amplifier circuit 100 is typically 1.2cm by 2.5cm. As a result of its large size, the transformer 130 cannot be housed in an IC package, such as an IC package (not shown) that houses the PA-FET 104 or an IC package (not shown) that houses the multi-band RF switch 102. Consequently, any indirect connection between the PA-FET 104 and the multi-band RF switch 102 must disadvantageously exist at least partially outside all known IC packages in which the PA-FET is housed and must disadvantageously exist at least partially outside all known IC packages in which the multi-band RF switch is housed.
In known implementations of the multi-band power amplifier circuit 100, the PA-FET 104 and the multi-band RF switch 102 are disposed on separate die. Additionally, in known implementations of the multi-band power amplifier circuit 100, the PA-FET 104 and the multi-band RF switch 102 are housed in separate IC packages.
In known implementations of the multi-band power amplifier circuit 100, the capacitor 108 is typically a chip capacitor. A chip capacitor must be located outside any IC package due to its large size. Therefore, in integrated circuit implementations of the multi-band power amplifier circuit 100, the capacitor 108 is located outside the IC package that houses the PA-FET 104 and outside the IC package that houses the multi-band RF switch 102.
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
A high-power, high-voltage multi-band RF power amplifier circuit includes a RF power amplifier coupled to a multi-band RF switch. The RF power amplifier is coupled to the multi-band RF switch without an intervening impedance matching network between the RF power amplifier and the multi-band RF switch.
The term “high-power” means power at the output of the RF power amplifier of approximately 10 W or higher. The term “high-voltage” means a DC voltage at a drain of the PA-FET 204 and at the input of the switch 202 of approximately 30V or higher.
Advantageously, the multi-band power amplifier circuit 200 lacks the transformer 106 of the known multi-band power amplifier circuit 100. The multi-band power amplifier circuit 200 comprises narrowband impedance matching networks 210 and 220 coupled between the switch 202 and filters 231 and 232. The narrowband impedance matching networks 210 and 220 functionally replace the wideband transformer 106 of the known multi-band power amplifier circuit 100 shown in
The impedance matching networks 210 and 220 are used to transform an impedance (typically 30Ω) necessary to obtain a required output power from the PA-FET 204 to an input impedance (usually 50Ω) of each filter 231 and 232 after accounting for losses in a corresponding path within the switch 202. In
In one embodiment, the impedance matching networks 210 and 220 are built on a PC board external to one of the PA-switch-controller ICs described hereinbelow (see
Filters 231 and 232 are typically lowpass or bandpass filters used to prevent harmonic and spurious signals outside a selected frequency band from reaching a PA_Out port 121 and a PA_Out port 122. Each filter 231 and 232 is tuned to pass a specific range of frequencies, as required by a radio system that uses the multi-band power amplifier circuit 200. For simplicity of illustration, only two filters 231 and 232 are shown; however, the multi-band power amplifier circuit 200 includes more than two filters when the multi-band power amplifier circuit has more than two output paths. In general, the number of filters equals the number of output paths of the multi-band power amplifier circuit 200. For example, when the multi-band power amplifier circuit 200 includes three (3) output paths, filter 231 is tuned to a range of approximately 740-870 MHz, filter 232 is tuned to a range of approximately 380-520 MHz and a third filter (not shown) is tuned to a range of approximately 130-175 MHz. In one embodiment, the impedance matching networks 220 and 220 are integrated into the filters 231 and 232.
A capacitor 208 is coupled between the drain of the PA-FET 204 and a common RF port, or input terminal, of the switch 202. The capacitor 208 prevents a DC supply voltage from appearing at the switch 202 which could, in one embodiment of the switch, contain paths to ground that would draw unnecessary current from a DC supply. In
The switch 202 may have larger FETs than the known multi-band RF switch 104 has so that the switch 202 can handle a higher RF current present at the output of the PA-FET 204. In one embodiment, the switch 202 is a model TS7423L switch available from Tagore Technology, Inc., of Arlington Heights, Ill. An SP2T switch is shown in
The RF signals from the PA_Out ports 121 and 122 may be directly connected to separate antennas (not shown) tuned for each frequency range. Alternatively, each PA_Out port 121 and 122 may be connected to the inputs of an additional switch (not shown) which connects a selected PA_Out port to an antenna that can operate in multiple frequency ranges. The additional switch can also contain an extra port that is connected to an RF input of a receiver.
A DC supply voltage is applied to the DC In port 128. In one embodiment, the DC supply voltage is +28V. The drain of the PA-FET is biased at +28V.
One end of line 405 is coupled to a source terminal of PA-FET 204. The other end of line 405 is coupled to a die attach pad (hereinafter “DAP”) of the IC package 400. The other short, unterminated lines, e.g., lines 406, 407 and 408, of the IC package 400 are also coupled to the DAP of the IC package. Pins 435, 436, 437 and 438 of the IC package 400 are connected to the DAP. Pins 435, 436, 437 and 438 are typically connected to a ground terminal of a PC board.
The left edge of the IC package 400 contains three pins 411, 412 and 413 that are connected to gate terminals of PA-FET 204. The gate terminals of PA-FET 204 are typically connected to each other. The pins 411, 412 and 413 are also connected to the output port of the input matching circuit 126 shown in
The top edge of the IC package 400 contains a pin 415 for receiving a DC voltage, DC_In, and pin 421 for outputting an amplified, switched RF signal. The pin 415 is coupled to the drain of the PA-FET 204. The DC_In port 128 shown in
The bottom edge of the IC package 400 contains a pin 422 for outputting an amplified, switched RF signal and a pin 423. The pin 421 and the pin 422 are coupled, respectively, to two RF outputs 205 and 207 of switch 202. Pin 423 and pin 424 are not connected to die 402, because the switch die contains a SP2T switch. Pins 423 and 424 are used when the die 402 contains a SP4T switch.
The controller of die 403 corresponds to controller 206 shown in the schematic of
The right edge of the IC package 400 contains a pin 430 and four pins 431, 432, 433 and 434. Pin 430 is connected to die 403 and provides a VDD voltage (see
The controller on die 503 corresponds to controller 306 shown in the schematic of
In
The embodiment illustrated in
Controller 206 includes a charge pump 1830. The controller 206 provides DC bias to selected Unit HEMTs cells of the switch 202 in a pattern to connect, through the DC block, the power amplifier output to one, and only one, of the RF outputs 205 and 207. The input lines V1, V2, V3 and V4 are coupled to a decoder 1832 and are used to select a desired output of the controller 206 through a binary control algorithm. An example of one such binary control algorithm for an SP4T switch is shown in TABLE 1, below. The extension to SP2T and/or SPNT switches is straightforward.
To turn off a HEMT used as a switch, a gate of the HEMT is biased at a negative voltage that is usually generated by a charge pump.
Turning on the RF Port 1 series HEMTs and turning off the RF Port 1 shunt HEMTs allows RF power to pass easily between the common RF Port 203 and RF Port 1, without being attenuated by the RF Port 1 shunt HEMTs. Turning off the RF Port 2 series HEMTs and turning on the RF Port 2 shunt HEMTs blocks RF power from flowing between the common RF Port 203 and RF Port 2.
In order to connect the common RF Port 203 to RF Port 2, and isolate it from RF Port 1, the output of RF Port 2 control is set high and the output of RF Port 1 control is set low. The resulting action is the same as described above, but with “RF Port 1” replaced by “RF Port 2”.
In the general case of an SPNT switch, in order to connect the common RF Port 203 to RF Port N, and isolate it from all the other RF ports, the output of RF Port N control is set high and the outputs of the other RF Port controls are set low. This turns on the RF Port N series HEMTs, and turns off the RF Port N shunt HEMTs. All the remaining series HEMTs are turned off and all the remaining shunt HEMTs are turned on.
The resistors placed across all the HEMT drain-source terminals are used to balance the voltages across these HEMTs. The resistors placed in series with each pair of gate terminals are used to isolate these terminals from the others on the same control line, and control the current flow from each gate to the corresponding control line.
The SP2T switch 202 and the controller 206 are more fully described in U.S. Pat. No. 9,548,731, entitled HIGH PERFORMANCE RADIO FREQUENCY SWITCH, issued Jan. 17, 2017 to Shah et al., and assigned to the assignee of the present application, and which is hereby fully incorporated by reference herein.
In one embodiment, the SP2T switch 202 comprises GaN HEMTs and the controller 206 comprises CMOS FETs on separate die. In another embodiment, the SP2T switch 202 comprises GaN HEMTs and the controller 206 comprises CMOS FETs, and the SP2T switch and the controller are integrated on a same die.
In one embodiment, the switch 302 comprises GaN HEMTs and the controller 306 comprises CMOS FETs on separate die. In another embodiment, the switch 302 comprises GaN HEMTs and the controller 306 comprises CMOS FETs, and the switch and the controller are integrated on a same die.
Switch 302 includes capacitor 1904 coupled between shunt Unit HEMT cell 1921 and a ground terminal. Switch 302 also includes capacitor 1905 coupled between shunt Unit HEMT cell 1924 and the ground terminal. In one embodiment, capacitors 1904 and 1905 have a size of 1 nF to 10 nF. Capacitors 1904 and 1905 prevent the shunt Unit HEMT cells 1921 and 1924 from burning out due to the +28V to +50V DC potential on their drain terminals.
GaN-on-silicon technology allows the GaN HEMT switch devices and the CMOS controller devices, to be integrated on a same die, thereby making a total solution very small. The GaN HEMT devices are grown on a silicon circuit supporting substrate with a GaN layer. Because the GaN HEMT devices are grown on a silicon substrate, the same silicon substrate can be used to grow CMOS devices. In a first technique, the GaN layer is etched off and NMOS and PMOS devices are grown using a standard CMOS process. In a second alternative technique, first an insulating layer of undoped GaN is used over a whole wafer, and then new silicon layers for the CMOS are grown on top of the insulating layer. Either technique allows an RF GaN device to be integrated together with a CMOS controller device, thereby advantageously eliminating a two-die total solution.
Using either of the above techniques, a seventh integrated circuit package (not shown) is foreseen. The seventh integrated circuit package includes, within the package, a GaN power amplifier, a GaN switch, an interconnect portion between the GaN power amplifier and the GaN switch, and a CMOS controller on a single die. The interconnect portion may include a DC blocking coupling capacitor. The GaN switch may include one or more DC blocking shunt capacitors.
The circuits and IC packages disclosed herein result in cost and size reduction compared to known multi-band power amplifier circuits as a result of elimination of a wideband matching network, i.e., a transformer, between a power amplifier and a multi-band RF switch.
Advantageously a direct connection of the one or more GaN FETs of a power amplifier and the plurality of GaN HEMTs of a switch (through a DC block) enables both PA and switch to occupy the same package.
Advantageously a direct connection of GaN FETs of the one or more GaN FETs of a power amplifier and the plurality of GaN HEMTs of a switch (through a DC block) enables both PA and switch to be on the same GaN die.
Advantageously a direct connection of GaN FETs of the one or more GaN FETs of a power amplifier and the plurality of GaN HEMTs of a switch (without a DC block) eliminates the need for negative bias on the gates of the HEMTs of the switch.
The circuits and packages disclosed herein can also be used with a distributed amplifier (not shown) which comprises of a plurality of FETs interconnected by transmission lines. A distributed amplifier is typically used for microwave applications where a paralleled FET architecture cannot function due to large parasitic reactances. In one embodiment, the distributed amplifier and the switch 202 and 302 are advantageously on a same die.
Advantageously, the multi-band power amplifier circuit 200 and 300 is capable of operating at any one or more bands of frequencies between 30 MHz and 10 GHz.
The PA-FET 204 and the multi-band RF switch 202 and 302 combined in a single IC package and, in one embodiment, also disposed on a same die, may be used for a variety of wireless applications using a variety of wireless communication protocols, including short range communication protocols such as Wi-Fi (i.e., IEEE 802.11 standards), BLUETOOTH™, near field communications (NFC), and cellular protocols, including but not limited to Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), Enhanced Data rates for GSM Evolution (EDGE), Long Term Evolution (LTE), Wi-MAX (i.e., IEEE 802.16 standards) and Land Mobile Radio (LMR).
Some features of the present invention may be used in an embodiment thereof without use of other features of the present invention. As such, the foregoing description should be considered as merely illustrative of the principles, teachings, examples, and exemplary embodiments of the present invention, and not a limitation thereof.
These embodiments are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others.
The circuit as described above is part of the design for an integrated circuit chip. The chip design is created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
The methods as discussed above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products (such as, but not limited to, an information processing system) having a display, a keyboard, or other input device, and a central processor.
Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which can be embodied in various forms. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed structure. Further, the terms and phrases used herein are not intended to be limiting; but rather, to provide an understandable description of the invention.
The terms “a” or “an”, as used herein, are defined as one as or more than one. The term plurality, as used herein, is defined as two as or more than two. Plural and singular terms are the same unless expressly stated otherwise. The term another, as used herein, is defined as at least a second or more. The terms including and/or having, as used herein, are defined as comprising (i.e., open language). The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically. The terms program, software application, and the like as used herein, are defined as a sequence of instructions designed for execution on a computer system. A program, computer program, or software application may include a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library and/or other sequence of instructions designed for execution on a computer system.
Although specific embodiments of the invention have been disclosed, those having ordinary skill in the art will understand that changes can be made to the specific embodiments without departing from the spirit and scope of the invention. The scope of the invention is not to be restricted, therefore, to the specific embodiments, and it is intended that the appended claims cover any and all such applications, modifications, and embodiments within the scope of the present invention.
Claims
1. A circuit, comprising:
- a radio frequency (hereinafter “RF”) power amplifier fabricated using gallium nitride (hereinafter “GaN”) technology, the RF power amplifier having an output impedance at its output port;
- an interconnection portion connected directly to the output port of the RF power amplifier;
- a multi-band RF switch fabricated using GaN technology, the multi-band RF switch having a common RF port connected directly to the interconnect portion and having a plurality of RF output ports;
- a plurality of narrowband impedance matching networks, each narrowband impedance matching network having an input port coupled to one RF output port of the multi-band RF switch and having an output port, each narrowband impedance matching network configured for optimum impedance matching within a narrow RF band; and
- a plurality of RF filters, each RF filter having an input port and an output port, the input port of one RF filter coupled to the output port of one narrowband impedance matching network, each RF filter configured to pass only RF signals within the narrow RF band of the narrowband impedance matching network to which it is coupled, wherein each RF filter has an input impedance at its input port,
- wherein each narrowband impedance matching network matches the output impedance of the RF power amplifier with the input impedance of the input port of the RF filter that is coupled to the narrowband impedance matching network.
2. The circuit of claim 1, wherein the interconnection portion consists solely of an electrical conductor with one end of the electrical conductor connected to the output port of the RF power amplifier and another end of the electrical conductor connected to the common RF port of the multi-band RF switch.
3. The circuit of claim 2, wherein the multi-band RF switch includes:
- a plurality of Unit HEMT cells, each Unit HEMT cell comprising:
- a GaN layer;
- a two-dimensional electron gas (2DEG) layer disposed on the GaN layer;
- an insulating layer disposed on the 2DEG layer;
- a GaN high-electron-mobility transistor (hereinafter “HEMT”), the GaN HEMT having a gate disposed on the insulating layer, a drain adjacent to one side of the gate and a source adjacent to an opposing side of the gate, the GaN HEMT disposed on and including the GaN layer, and the GaN HEMT having its gate connected to one contact of a 2DEG gate bias resistor, the 2DEG gate bias resistor disposed in the 2DEG layer;
- a HEMT cell gate electrically connected to another contact of the 2DEG gate bias resistor;
- a HEMT cell drain electrically connected to one contact of a 2DEG linearity resistor and to the drain of the GaN HEMT; and
- a HEMT cell source electrically connected to another contact of the 2DEG linearity resistor and to the source of the GaN HEMT, the 2DEG linearity resistor being disposed in the 2DEG layer.
4. The circuit of claim 2, wherein the RF power amplifier includes a GaN field-effect transistor (hereinafter “PA-FEY”) having a gate terminal coupled to an input port of the RF power amplifier, a drain coupled to a direct current (DC) supply voltage for biasing the PA-FET at a positive voltage, and a source terminal coupled to ground potential.
5. The circuit of claim 4, wherein the multi-band RF switch includes at least two series Unit HEMT cells and at least two shunt Unit HEMT cells, wherein a cell drain of each series Unit HEMT cell is coupled to the DC supply voltage for biasing the at least two series Unit HEMT cells at a same positive voltage at which the PA-FET is biased.
6. The circuit of claim 2, including a controller for controlling operation of the multi-band RF switch, the controller separately coupled to the HEMT cell gate of each Unit HEMT cell of the multi-band RF switch for separately controlling each Unit HEMT cell.
7. The circuit of claim 1, wherein the interconnection portion consists solely of a capacitor with one end of the capacitor connected to the output port of the RF power amplifier and another end of the capacitor connected to the common RF port of the multi-band RF switch.
8. The circuit of claim 7, wherein the RF power amplifier includes a GaN field-effect transistor (hereinafter “PA-FET”) having a gate terminal coupled to an input port of the RF power amplifier, a drain coupled to a direct current (DC) supply voltage for biasing the PA-FET at a positive voltage, and a source terminal coupled to ground potential.
9. The circuit of claim 8, wherein the multi-band RF switch includes:
- a plurality of Unit HEMT cells, each Unit HEMT cell comprising:
- a GaN layer;
- a two-dimensional electron gas (2DEG) layer disposed on the GaN layer;
- an insulating layer disposed on the 2DEG layer;
- a GaN high-electron-mobility transistor (hereinafter “HEMT”), the GaN HEMT having a gate disposed on the insulating layer, a drain adjacent to one side of the gate and a source adjacent to an opposing side of the gate, the GaN HEMT disposed on and including the GaN layer, and the GaN HEMT having its gate connected to one contact of a 2DEG gate bias resistor, the 2DEG gate bias resistor disposed in the 2DEG layer;
- a HEMT cell gate electrically connected to another contact of the 2DEG gate bias resistor;
- a HEMT cell drain electrically connected to one contact of a 2DEG linearity resistor and to the drain of the GaN HEMT; and
- a HEMT cell source electrically connected to another contact of the 2DEG linearity resistor and to the source of the GaN HEMT, the 2DEG linearity resistor being disposed in the 2DEG layer.
10. The circuit of claim 9, including a controller separately coupled to the HEMT cell gate of each Unit HEMT cell of the multi-band RF switch for separately controlling each Unit HEMT cell.
11. An integrated circuit (hereinafter “IC”) package, comprising:
- a field-effect transistor disposed on a gallium nitride (hereinafter “GaN”) layer over a first silicon substrate (hereinafter “PA-FET”) housed within the IC package, the PA-FET having a gate terminal, a drain terminal coupled to a direct current (hereinafter “DC”) supply voltage for biasing the PA-FET at a positive voltage, and a source terminal coupled to ground potential, the PA-FET having an output impedance at the drain terminal; and
- a multi-band RF switch disposed on a GaN layer over a second silicon substrate housed within the IC package, the multi-band RF switch including a plurality of Unit HEMT cells, the multi-band RF switch having a common RF port connected directly to the drain terminal of the PA-FET without any intervening impedance matching network and having a plurality of RF output ports, wherein a connection between the PA-FET and the multi-band RF switch is totally within the IC package.
12. The IC package of claim 11, wherein each Unit HEMT cell of the plurality of Unit HEMT cells includes:
- a two-dimensional electron gas (2DEG) layer disposed on the GaN layer;
- an insulating layer disposed on the 2DEG layer;
- a GaN high-electron-mobility transistor (hereinafter “HEMT”), the GaN HEMT having a gate disposed on the insulating layer, a drain adjacent to one side of the gate and a source adjacent to an opposing side of the gate, the GaN HEMT disposed on and including the GaN layer, and the GaN HEMT having its gate connected to one contact of a 2DEG gate bias resistor, the 2DEG gate bias resistor disposed in the 2DEG layer;
- a HEMT cell gate electrically connected another contact of the 2DEG gate bias resistor;
- a HEMT cell drain electrically connected to one contact of a 2DEG linearity resistor and to the drain of the GaN HEMT; and
- a HEMT cell source electrically connected to another contact of the 2DEG linearity resistor and to the source of the GaN HEMT, the 2DEG linearity resistor being disposed in the 2DEG layer.
13. The IC package of claim 12, wherein the multi-band RF switch includes at least two series Unit HEMT cells and at least two shunt Unit HEMT cells, wherein a cell drain of each series Unit HEMT cell is coupled to the DC supply voltage for biasing the at least two series Unit HEMT cells at a same positive voltage at which the PA-FET is biased.
14. The IC package of claim 12, including a controller disposed on a third silicon substrate housed within the IC package, wherein the controller is separately coupled to the HEMT cell gate of each Unit HEMT cell of the multi-band RF switch for separately controlling each Unit HEMT cell.
15. The IC package of claim 11 including
- a plurality of narrowband impedance matching networks housed within the IC package, each narrowband impedance matching network having an input port coupled to one RF output port of the multi-band RF switch and having an output port, each narrowband impedance matching network configured for optimum impedance matching within a narrow RF band; and
- a plurality of RF filters housed within the IC package, each RF filter having an input port and an output port, the input port of one RF filter coupled to the output port of one narrowband impedance matching network, each RF filter configured to pass only RF signals within the narrow RF band of the narrowband impedance matching network to which it is coupled, wherein each RF filter has an input impedance at its input port,
- wherein each narrowband impedance matching network matches the output impedance of the drain terminal of the PA-FET with the input impedance of the input port of the RF filter coupled to the narrowband impedance matching network.
16. An integrated circuit (hereinafter “IC”) package, comprising:
- a field-effect transistor disposed on a gallium nitride (hereinafter “GaN”) layer over a silicon substrate (hereinafter “PA-FET”), the PA-FET having a gate terminal, a drain terminal coupled to a direct current (hereinafter “DC”) supply voltage for biasing the PA-FET at a positive voltage, and a source terminal coupled to ground potential, the PA-FET having an output impedance at the drain terminal; and
- a multi-band RF switch including a plurality of Unit HEMT cells, the multi-band RF switch disposed on a GaN layer over the silicon substrate, the multi-band RF switch having a common RF port connected directly to the drain terminal of the PA-FET without any intervening impedance matching network and having a plurality of RF output ports,
- wherein the silicon substrate is housed within the IC package.
17. The IC package of claim 16, wherein each Unit HEMT cell of the plurality of Unit HEMT cells, includes:
- a two-dimensional electron gas (2DEG) layer disposed on the GaN layer;
- an insulating layer disposed on the 2DEG layer;
- a GaN high-electron-mobility transistor (hereinafter “HEMT”), the GaN HEMT having a gate disposed on the insulating layer, a drain adjacent to one side of the gate and a source adjacent to an opposing side of the gate, the GaN HEMT disposed on and including the GaN layer, and the GaN HEMT having its gate connected to one contact of a 2DEG gate bias resistor, the 2DEG gate bias resistor disposed in the 2DEG layer;
- a HEMT cell gate electrically connected to another contact of the 2DEG gate bias resistor;
- a HEMT cell drain electrically connected to one contact of a 2DEG linearity resistor and to the drain of the GaN HEMT; and
- a HEMT cell source electrically connected to the other contact of the 2DEG linearity resistor and to the source of the GaN HEMT, the 2DEG linearity resistor being disposed in the 2DEG layer.
18. The IC package of claim 17, wherein the multi-band RF switch includes at least two series Unit HEMT cells and at least two shunt Unit HEMT cells, wherein a cell drain of each series Unit HEMT cell is coupled to the DC supply voltage for biasing the at least two series Unit HEMT cells at a same positive voltage at which the PA-FET is biased.
19. The IC package of claim 16, including at least one metal-insulator-metal (hereinafter “MIM”) capacitor disposed on the silicon substrate, the at least one MIM capacitor coupling the multi-band RF switch to ground potential.
20. The IC package of claim 16, including a controller, fabricated using CMOS technology and disposed on the silicon substrate, wherein the controller is separately coupled to the HEMT cell gate of each Unit HEMT cell of the multi-band RF switch for separately controlling each Unit HEMT cell.
Type: Application
Filed: Apr 13, 2017
Publication Date: Oct 18, 2018
Applicant: Tagore Technology, Inc. (Arlington Heights, IL)
Inventor: James E. MITZLAFF (Arlington Heights, IL)
Application Number: 15/487,112