Power MOSFET Having Improved Manufacturability, Low On-Resistance and High Breakdown Voltage
Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). The power MOSFET has two and only two epitaxial semiconductor layers, and the BSSCCRs are disposed at the interface between these layers. Looping around the area occupied by these parallel-extending BSSCCRs is a P type ring-shaped BSSCCR. At the upper semiconductor surface are disposed three P type surface rings. The inner surface ring and outer surface ring are coupled together by a bridging metal member, but the center surface ring is floating. The bridging metal member is disposed at least in part over the ring-shaped BSSCCR. The MOSFET has a high breakdown voltage, a low RDS(ON), and is acceptable and suitable for manufacture at semiconductor fabrication. plants that cannot or typically do not make superjunction MOSFETs.
This application is a continuation of, and claims priority under 35 U.S.C. § 120 from, nonprovisional U.S. patent application Ser. No. 15/815,391 entitled “Power MOSFET Having Improved Manufacturability, Low On-Resistance and High Breakdown Voltage,” filed on Nov. 16, 2017, now U.S. Pat. No. 10,038,088. U.S. patent application Ser. No. 15/815,391, in turn, is a continuation of, and claims priority under 35 U.S.C. § 120 from, nonprovisional U.S. patent application Ser. No. 15/284,488 entitled “Power MOSFET Having Improved Manufacturability, Low On-Resistance and High Breakdown Voltage,” filed on Oct. 3, 2016, now U.S. Pat. No. 9,837,529. The subject matter of each of the foregoing documents is incorporated herein by reference.
BACKGROUND INFORMATIONFor the same breakdown voltage (BVDSS) rating and the same die size, the drain-to-source on-resistance (RDDS(ON)) of a so-called “superjunction” field effect transistor (also called a “superjunction MOSFET”) will generally be lower than the RDS(ON) of a conventional non-superjunction MOSFET device. For this reason, superjunction MOSFETs are taking a larger and larger share of the overall MOSFET market as compared to the share attributed to conventional trench-type and planar-type MOSFETs.
As compared to current state-of-the-art non-superjunction power field effect transistors (so-called power MOSFETS), a novel power field effect transistor device has a reduced drain-to-source on resistance RDS(ON) of about one third of its current value (for a conventional power field effect transistor of a given active area), and this is accomplished for the same target breakdown voltage (BVDSS) rating of the device, and without requiring either a deep trench etching manufacturing step or the deposition of more than two epitaxial silicon layers. The novel power field effect transistor device has a typical specific on-resistance (RON,SP) of not more than 0.8 milliohms-cm2 when the transistor device is on. For a power field effect transistor device having an active area of 0.20 cm2, this translates into an on-resistance RDS(ON) of about four milliohms. The drain-to-source IDs voltage at which the device first suffers breakdown is about 110 volts. If a ten percent margin on breakdown voltage is required for a marketable power field effect transistor device, then the novel field effect transistor device has a 100 volt breakdown voltage rating.
Despite conventional wisdom and common practice in the industry, it is recognized by the inventor that many semiconductor manufacturing facilities (so-called semiconductor “fabs”) cannot and/or will not manufacture power transistor devices of the types set forth in
In accordance with one novel aspect, it is recognized that such a high volume manufacturer will accept the importing into its plant of an in-process wafer two times, the first time being when the substrate wafer has a first epitaxial layer deposited on it, and the second being when the substrate wafer has a second epitaxial layer deposited on the first epitaxial layer. Buried charge compensation layers of the novel power field effect transistor device do not extend up to the surface of the second epitaxial layer so the device does not have the familiar P type “column” or “pillar” structures of the superjunction MOSFETs of
In accordance with a novel aspect, the high breakdown voltage rating of the device is achieved by recognizing that breakdown occurs first here at the ends of the parallel-extending BSSCCRs, and then providing a floating P type surface ring structure directly above the buried inner P type BSSCCR ring. In addition, there is a P type surface ring located just inside the floating P type surface ring, and there is another P type surface ring located just outside the floating P type surface ring. The three P type surface rings are concentric. The inner and outer P type surface rings are electrically connected. together by a metal bridging member. The metal bridging member bridges up and over the floating P type surface ring. Due to the fact that the floating P type surface ring is floating, in a high VDS condition the strength of the electric field in the vicinity of the buried inner BSSCCR (at the ends of the parallel-extending BSSCCRs) is reduced as compared the strength of the electric field immediately inside the inner BSSCCR ring and immediately outside the inner BSSCCR ring. As a result, the novel power field effect transistor device has the breakdown voltage rating of 100 volts despite the fact that the P type charge compensation regions do not extend up to the semiconductor surface of the device. Due to the device having two and only two epitaxial layers, the implanting and fine geometry processing involved in making the device can be done at semiconductor wafer fabrication plants that cannot make superjunction MOSFETs of the type set forth in
In one novel aspect, a power field effect transistor die structure comprises a substrate semiconductor layer, a first epitaxial semiconductor layer, a second epitaxial semiconductor layer, a plurality of parallel-extending BSSCCRs, a surface transistor structure, an inner BSSCCR, and outer BSSCCR, a first surface region, a second surface region, a third surface region, and a bridging metal member. The substrate semiconductor layer is of a first conductivity type. The first epitaxial semiconductor layer is disposed on the substrate semiconductor layer and is of the first conductivity type. The second epitaxial semiconductor layer is disposed on the first epitaxial semiconductor layer and is of the first conductivity type. The second epitaxial semiconductor layer has an upper semiconductor surface that is also the upper semiconductor surface of the die structure. The first and second epitaxial semiconductor layers are the only epitaxial semiconductor layers of the power field effect transistor die structure.
Each BSSCCR of the plurality of parallel-extending BSSCCRs is a straight, stripe-shaped, region of a second conductivity type. Each of the parallel-extending BSSCCRs is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer but is entirely covered by semiconductor material of the first conductivity type of the second epitaxial semiconductor laver. Each of the parallel-extending BSSCCRs has an end. One of the parallel-extending BSSCCRs extends in a first straight line from a first end to a second end.
The surface transistor structure is disposed over the plurality of parallel-extending BSSCCRs, and has a gate region and a source region. In one example the surface transistor structure is an array or trench-type transistor devices, and in another example the surface transistor structure is an array of planar-type transistor devices.
The inner BSSCCR is of the second conductivity type. The inner BSSCCR extends for a distance in a second. straight line. The second straight line is perpendicular to the first straight line. The inner BSSCCR is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer but is entirely covered by semiconductor material of the first conductivity type of the second epitaxial semiconductor laver.
The outer BSSCCR is of the second conductivity type. The outer BSSCCR extends parallel to the inner BSSCCR such that the inner BSSCCR is disposed between the outer BSSCCR and the plurality of parallel-extending BSSCCRs. The outer BSSCCR is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer but is entirely covered by semiconductor material of the first conductivity type of the second epitaxial semiconductor layer. In one example, the inner and outer buried BSSCCRs are a pair of buried P type concentric ring-shaped regions. For stretches, each of these buried P type concentric ring-shaped regions extends in a straight line. All BSSCCRs of the device are floating, including all the BSSCCRs of the plurality of parallel-extending BSSCCRs, and including the inner BSSCCR, and including the outer BSSCCR.
The first surface region is of the second conductivity type. The first surface region is disposed at the upper semiconductor surface of die structure.
The second surface region is of the second. conductivity type. The second surface region extends parallel to the first surface region at the upper semiconductor surface of the die structure. The second surface region is floating and is stripe-shaped.
The third surface region is of the second conductivity type. The third surface region extends parallel to the second surface region at the upper semiconductor surface of the die structure such that the second surface region is disposed between the first and third surface regions. The third surface region is stripe-shaped. In one example, the first, second and third surface regions are three concentric surface rings of P type material disposed in N− type material of the second epitaxial semiconductor layer, where the second ring-shaped P type surface region is disposed directly over the ring-shaped P type inner BSSCCR.
The metal bridging member electrically couples the first and third surface regions together, but is not physically contacting the second surface region. In one example the metal bridging member contacts the first surface region at the upper semiconductor surface, and bridges up and over the second surface region, and contacts the third surface region at the upper semiconductor surface. The metal bridging member is disposed at least in. part over the inner BSSCCR.
Each BSSCCR (whether it be a BSSCCR of the plurality of parallel-extending BSSCCRs, or the inner BSSCCR, or the outer BSSCCR) has a cross-sectional width and a cross-sectional height. The cross-sectional height is greater than the cross-sectional width. This cross-sectional shape of the BSSCCRs, and the spacing between adjacent BSSCCRs, reduces current crowding in the on-state of the device and therefore reduces the RDS(ON) of the device. In one example this is accomplished by blanket implanting N type dopants (phosphorus) into the top of the first epitaxial layer. This blanket implant can be performed either before or after the masked implant of the P type dopants (boron) that will diffuse to form the BSSCCRs. After the blanket implanting of N type dopants and the masked implanting of the P type dopants for the buried regions, the second epitaxial semiconductor layer is formed on the first epitaxial semiconductor layer. P type dopants are implanted into the upper surface of the second epitaxial layer (to form the P type body regions in the active area and to form the first, second and third surface rings), and then the wafer structure is heat treated to diffuse the dopants. Due to the blanket N type dopant implant and the narrow 0.5 micron wide implant windows used in implanting P type dopants, each resulting BSSCCR has a cross-sectional height that is greater than its cross-sectional width.
Further details and embodiments and techniques are described in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims.
The accompanying drawings, where like numerals indicate like components, illustrate embodiments of the invention.
Reference will now be made in detail to some embodiments of the invention, examples of which are illustrated in the accompanying drawings. In the description and claims below, when a first object is referred to as being disposed “over” or “on” a second. object, it is to be understood that the first object can be directly on the second object, or an intervening object may be present between the first and second objects. Similarly, terms such as “upper”, “top”, “up”, “on”, “over”, “cover”, “down.”, “vertical”, “horizontal”, “laterally”, “lower”, “bottom”, “underneath”, “height” and “width” are used herein to describe relative orientations between different parts of the structure being described, and it is to be understood that the overall structure being described can actually be oriented in any way in three-dimensional space. The notations N+, N, N−, P, and P− are only relative, and are to be considered in context, and do not denote any particular dopant concentration range.
Power field effect transistor die structure 1 includes a substrate layer 6 of N+ type single crystal silicon wafer material, a 3.0 micron thick first epitaxial silicon layer 7 disposed on the substrate laver, a 3.0 micron thick second epitaxial silicon layer disposed on the first epitaxial silicon layer, insulative silicon oxide features 9-11, a source metal electrode 12, a gate metal electrode 13, a metal bridging member 14, and a drain metal electrode 15. The first and second epitaxial silicon layers 7 and 8 are the only epitaxial silicon layers of the die 1. At the interface 59 between the first and second epitaxial layers 7 and 8 are a plurality of P− type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). Each of these BSSCCRs extends from the interface 59 up into the bottom of the second epitaxial layer 8 and also extends from the interface 59 down into the top of the first epitaxial layer 7. Each BSSCCR is a stripe in the sense that it is a long and narrow region of the same width throughout its length.
As shown in
In addition to the parallel-extending P− type BSSCCRs 17-32, the power field effect transistor die structure 1 also includes six stripe-shaped BSSCCR rings 33-38. As illustrated in
One of the third through the fourteenth BSSCCRs (for example, the ninth BSSCCR 25) of the parallel-extending BSSCCRs 17-32 extends in a first straight line 60. This first straight line 60 is vertical in the illustrated orientation of
The outer BSSCCR 34 also has a stripe-shape. It extends parallel to the inner BSSCCR 33 as illustrated. There is no other P type region disposed between the first ends of the parallel-extending P− type BSSCCRs 17-32 and the inner P-type BSSCCR ring 33.
The BSSCCRs are made to have this cross-sectional shape by performing a blanket implant of phosphorus into the top surface of the first epitaxial layer 7 prior to the formation of the second epitaxial layer 8. This blanket implant is performed with a 330 keV implant energy so that the phosphorus dopants are implanted to a depth of approximately 0.4 microns. The implant dose is 2.0×1012 ions/cm2 . After this blanket implant, boron for the P− type BSSCCRs is implanted using a mask. The boron is implanted into the top of the first epitaxial layer 7. This boron implant is performed with a 120 keV implant energy and a dose of 1.5×1013 ions/cm2, so that the boron dopants are implanted to a depth of approximately 0.5 microns. The implant mask has narrow 0.5 micron wide strip-shaped implant windows with a cell pitch of 2.5 microns. After implantation, the second epitaxial layer 8 is formed on top of the first epitaxial layer 7 and the combined structure (the substrate, first epitaxial layer, and second epitaxial layer) is annealed and temperature treated by further processing such that the boron and phosphorus dopants diffuse so as to form the BSSCCR structures pictured in
In the central active area of the die, disposed over the region of the parallel-extending BSSCCRs 17-32 there is an array of parallel-extending trench-type transistor structures.
When the overall transistor structure is turned on and conductive, a voltage on the gate induces conductive channels to form in the P type semiconductor material of the trench sidewalls. Electrons can flow from N type source region 48, downward along one of these conductive channels on the left side of the trench, and downward to the N− type epitaxial layer portion 41, and further downward through the die to the drain metal electrode 15. Likewise, electrons can flow on the other side of the structure from N type source region 49, downward along a conductive channel on the right side of the trench, and downward to the N− type epitaxial layer portion 41, and further downward through the die to the drain metal electrode 15.
Surrounding these trench-type transistor structures is a set of concentric stripe-shaped P type surface regions (rings) 50-58. As shown in
First P type surface ring 52 is coupled by the metal bridging member 14 to the third P type surface ring 54. The intervening second. P type surface ring 53, however, is floating and is not connected to any other surface ring, nor is it connected to the metal bridging member 14. The first P type surface ring 52 extends over the end portions of the BSSCCRs 17-32 as shown in
Note that the spacing and widths of the surface rings 55-58 is greater than the spacing and widths of the corresponding BSSCCRs 33-38 beneath the surface rings. Accordingly, surface ring 55 is disposed over BSSCCR 33 in a centered fashion, but each successive surface ring extending outward toward the edge of the die is displaced more and more from its corresponding underlying BSSCCR. In the example of
In other embodiments, each successive one of the surface rings 55-58 extending outward toward the edge of the die is narrower that the preceding surface ring. The outer edge of the implant window of each such surface ring has the same location (from the top-down perspective) relative to the outer edge of the implant window for the buried layer implant region below.
Although certain specific embodiments are described above for instructional purposes, the teachings of this patent document have general applicability and are not limited to the specific embodiments described above. It is to be understood that the structure of
Claims
1-18. (canceled)
19. A power field effect transistor die structure comprising:
- a substrate semiconductor layer of a first conductivity type;
- a first epitaxial semiconductor layer disposed on the substrate;
- a second epitaxial semiconductor layer disposed on the first epitaxial semiconductor layer, wherein an upper surface of the second epitaxial semiconductor layer is an upper semiconductor surface of the die structure, and wherein the first and second epitaxial semiconductor layers are the only epitaxial semiconductor layers of the power field effect transistor die structure;
- a plurality of buried charge compensation regions of a second conductivity type, wherein each of the buried charge compensation regions of the plurality of buried charge compensation regions is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer but is entirely covered by semiconductor material of the first conductivity type of the second epitaxial semiconductor layer;
- a transistor structure that is disposed over the plurality of buried charge compensation regions, wherein the transistor structure includes a gate region and a source region;
- an inner buried charge compensation region of the second conductivity type, wherein the inner buried charge compensation region extends adjacent a periphery of the plurality of buried charge compensation regions, wherein the inner buried charge compensation region is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer but is entirely covered by semiconductor material of the first conductivity type of the second epitaxial semiconductor layer;
- an outer buried charge compensation region of the second conductivity type that extends parallel to the inner buried charge compensation region such that the inner buried charge compensation region is disposed between the outer buried charge compensation region and the plurality of buried charge compensation regions, wherein the outer buried charge compensation region is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer but is entirely covered by semiconductor material of the first conductivity type of the second epitaxial semiconductor layer;
- a first surface region of the second conductivity type, wherein the first surface region is disposed at the upper semiconductor surface of the die structure;
- a second surface region of the second conductivity type, wherein the second surface region extends parallel to the first surface region at the upper semiconductor surface of the die structure, and wherein the second surface region is floating and is stripe-shaped;
- a third surface region of the second conductivity type, wherein the third surface region extends parallel to the second surface region at the upper semiconductor surface of the die structure such that the second surface region is disposed between the first and third surface regions, wherein the third surface region is stripe-shaped;
- a drain metal electrode;
- a source metal electrode;
- a gate metal electrode; and
- a metal bridging member that electrically couples the first and third surface regions together, wherein the metal bridging member bridges over the second surface region but is not physically contacting the second surface region, wherein the metal bridging member is disposed at least in part over the inner buried charge compensation region, and wherein the metal bridging member does not contact or adjoin either the source metal electrode or the gate metal electrode.
20. The power field effect transistor die structure of claim 19, wherein all the buried charge compensation regions of the plurality of buried charge compensation regions are floating, wherein the inner buried charge compensation region is floating, wherein the outer buried charge compensation region is floating, and wherein there is no semiconductor region of the second conductivity type disposed between the first and third surface regions other than the second surface region.
21. The power field effect transistor die structure of claim 19, wherein the source metal electrode contacts a body region of the second conductivity type at the upper semiconductor surface of the die structure, wherein an active area of the power field effect transistor die structure has a specific on-resistance (RON,SP) of not more than 0.8 milliohms-cm2 when the power field effect transistor die structure is on, and wherein the power field effect transistor die structure has a drain-to-source breakdown voltage of at least one hundred volts.
22. The power field effect transistor die structure of claim 19, wherein the second surface region is a ring, and wherein the third surface region is a ring that surrounds the second surface region.
23. The power field effect transistor die structure of claim 19, wherein each of the plurality of buried charge compensation regions has an end, and wherein there is no buried P type semiconductor region disposed between any end of any of the plurality of buried charge compensation regions and the inner buried charge compensation region.
24. The power field effect transistor die structure of claim 19, wherein the power field effect transistor die structure includes no transistor gate region that is disposed outside the first surface region.
25. The power field effect transistor die structure of claim 19, wherein each of the plurality of buried charge compensation regions has a cross-sectional width and a cross-sectional height, wherein the cross-sectional height is greater than the cross-sectional width.
26. The power field effect transistor die structure of claim 19, wherein the first epitaxial semiconductor layer comprises an N− type layer portion and an N type layer portion, wherein the N− type layer portion of the first epitaxial semiconductor layer is disposed on the substrate semiconductor layer, and wherein the N type layer portion of the first epitaxial semiconductor layer is disposed on the N− type layer portion of the first epitaxial semiconductor layer.
27. The power field effect transistor die structure of claim 19, wherein the second epitaxial semiconductor layer comprises an N− type layer portion and an N type layer portion, wherein the N type layer portion of the second epitaxial semiconductor layer is disposed on the first epitaxial semiconductor layer, and wherein the N− type layer portion of the second epitaxial semiconductor layer is disposed on the N type layer portion of the second epitaxial semiconductor layer.
28. The power field effect transistor die structure of claim 19, wherein the second surface region is disposed at least in part over the inner buried charge compensation region.
29. The power field effect transistor die structure of claim 19, wherein the transistor structure is taken from the group consisting of: 1) an array of stripe trench transistor devices, and 2) an array of stripe planar transistor devices.
30. The power field effect transistor die structure of claim 19, wherein the gate metal electrode extends over an end portion of one of the plurality of buried charge compensation regions.
31. A die structure comprising:
- a substrate semiconductor layer of a first conductivity type;
- a first epitaxial semiconductor layer disposed on the substrate;
- a second epitaxial semiconductor layer disposed on the first epitaxial semiconductor layer, wherein an upper surface of the second epitaxial semiconductor layer is an upper semiconductor surface of the die structure;
- a plurality of buried charge compensation regions of a second conductivity type, wherein each of the buried charge compensation regions of the plurality of buried charge compensation regions is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer;
- an inner buried charge compensation region of the second conductivity type, wherein the inner buried charge compensation region extends adjacent a periphery of the plurality of buried charge compensation regions, and wherein the inner buried charge compensation region is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer; and
- an outer buried charge compensation region of the second conductivity type that extends parallel to the inner buried charge compensation region such that the inner buried charge compensation region is disposed between the outer buried charge compensation region and the plurality of buried charge compensation regions, wherein the outer buried charge compensation region is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer.
32. The die structure of claim 31, wherein the die structure does not include any epitaxial semiconductor layers other than the first and second epitaxial semiconductor layers.
33. The die structure of claim 31, wherein each of the plurality of buried charge compensation regions has an end, and wherein there is no buried P type semiconductor region disposed between any end of any of the plurality of buried charge compensation regions and the inner buried charge compensation region.
34. The die structure of claim 31, wherein each of the plurality of buried charge compensation regions has a cross-sectional width and a cross-sectional height, and wherein the cross-sectional height is greater than the cross-sectional width.
35. The die structure of claim 31, wherein the first epitaxial semiconductor layer comprises an N− type layer portion and an N type layer portion, wherein the N− type layer portion of the first epitaxial semiconductor layer is disposed on the substrate semiconductor layer, wherein the N type layer portion of the first epitaxial semiconductor layer is disposed on the N− type layer portion of the first epitaxial semiconductor layer, wherein the second epitaxial semiconductor layer comprises an N− type layer portion and an N type layer portion, wherein the N type layer portion of the second epitaxial semiconductor layer is disposed on the first epitaxial semiconductor layer, and wherein the N− type layer portion of the second epitaxial semiconductor layer is disposed on the N type layer portion of the second epitaxial semiconductor layer.
36. A power field effect transistor die structure comprising:
- a drain metal electrode;
- a source metal electrode;
- a gate metal electrode;
- a substrate semiconductor layer of a first conductivity type;
- a first epitaxial semiconductor layer disposed on the substrate;
- a second epitaxial semiconductor layer disposed on the first epitaxial semiconductor layer, wherein an upper surface of the second epitaxial semiconductor layer is an upper semiconductor surface of the die structure;
- a plurality of buried charge compensation regions of a second conductivity type, wherein each of the buried charge compensation regions of the plurality of buried charge compensation regions is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer;
- an inner buried charge compensation region of the second conductivity type, wherein the inner buried charge compensation region extends adjacent a periphery of the plurality of buried charge compensation regions, wherein the inner buried charge compensation region is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer;
- an outer buried charge compensation region of the second conductivity type that extends parallel to the inner buried charge compensation region such that the inner buried charge compensation region is disposed between the outer buried charge compensation region and the plurality of buried charge compensation regions, wherein the outer buried charge compensation region is disposed partly in the first epitaxial layer and is disposed partly in the second epitaxial layer; and
- a metal bridging member that electrically couples two surface regions of the second conductivity type together, wherein the two surface regions are disposed at the upper semiconductor surface of the die structure, and wherein the metal bridging member is disposed at least in part over the inner buried charge compensation region.
37. The power field effect transistor die structure of claim 36, wherein the metal bridging member bridges over a floating surface region, wherein the metal bridging member does not physically contact the floating surface region, and wherein the floating surface region is disposed at the upper semiconductor surface of the die structure.
Type: Application
Filed: Jul 13, 2018
Publication Date: Nov 29, 2018
Inventor: Kyoung Wook Seok (Milpitas, CA)
Application Number: 16/035,566