LOW VOLTAGE DIFFERENCE OPERATED EEPROM AND OPERATING METHOD THEREOF
The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof, wherein at least one transistor structure is formed in a semiconductor substrate and each includes a first electric-conduction gate. An ion implantation is performed by masking partial regions to prevent the existence of the conventional lightly doped drain (LDD) structure. An undoped region is formed in the semiconductor substrate under the two sides of the first electric-conductive gate, to increase the intensity of electric field between the gate and the substrate or between the gate and the transistor, whereby to reduce the voltage differences required for writing and erasing. The present invention also discloses an operating method for the low voltage difference-operated EEPROM. The present invention applies to the EEPROM with a single gate transistor structure.
The present invention relates to an EEPROM technology, particularly to a low voltage difference operated EEPROM and operating method thereof wherein the transistor does not have the lightly doped drain (LDD) structure.
Description of the Related ArtNon-volatile memories, such as Flash memories and EEPROM (Electrically Erasable Programmable Read Only Memory), are semiconductor storage devices that can be electrically written and erased repeatedly. Nowadays, non-volatile memories have been widely used in electronic products because their data will not volatilize after the power source is turned off.
A non-volatile memory is programmable via storing charges to vary the gate voltage of the transistors or via not storing charges to keep the original gate voltage. A non-volatile memory is erasable by removing the charges stored there inside to restore the original gate voltage thereof. The current EEPROM is erased with a higher voltage difference, which causes the memory to have a larger area and a more complicated fabrication process.
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In order to avoid increasing the complexity of the existing process without affecting the stability of the memory element, the present invention proposes a low voltage difference and low current operated EEPROM and an operating method thereof to overcome the conventional problems.
SUMMARY OF THE INVENTIONThe primary objective of the present invention is to provide a low voltage difference operated EEPROM and an operating method thereof, wherein an ion implantation is performed by masking partial regions to prevent the existence of the conventional lightly doped drain (LDD) region to increase the intensity of the electric field between the gate and the substrate or between the gate and the transistor and thus decrease the required voltage difference for erasing or writing EEPROM, and wherein the operating method is able to massively erase or write memory cells simultaneously.
Another objective of the present invention is to provide a low voltage difference operated EEPROM and an operating method thereof, which use the voltage difference between the gate and the source/drain or the voltage difference between the gate and the substrate/well to write or erase EEPROM in a lower current.
To achieve the abovementioned objectives, the present invention proposes a low voltage difference operated EEPROM, which comprises a semiconductor substrate, at least one transistor structure and a capacitor structure. The transistor structure and the capacitor structure are formed in the semiconductor substrate, wherein the transistor structure includes a first dielectric layer formed on the surface of the semiconductor substrate; a first electric-conduction gate formed on the first dielectric layer; two undoped regions formed inside the semiconductor substrate under two sides of the first electric-conduction gate; and at least two first ion-doped regions formed inside the semiconductor substrate under the two sides of the first electric-conduction gate and separated from the undoped regions to separately function as the source and the drain. The capacitor structure is separated from the transistor structure, and includes a second ion-doped region formed inside the semiconductor substrate, a second dielectric layer formed on a surface of the second ion-doped region, and a second electric-conduction gate stacked on the second dielectric layer. The second electric-conduction gate is electrically connected with the first electric-conduction gate to function as a single floating gate.
The EEPROM of the present invention is characterized in performing an ion implanting by masking partial regions to prevent the existence of the lightly doped drain (LDD) region of the conventional transistor structure, and forming an undoped region to increase the intensity of the electric field between the gate and the substrate or between the gate and the transistor, whereby to decrease the voltage difference required for writing or erasing the EEPROM.
While the transistor structure of the present invention is an N-type transistor, the first ion-doped region or the second ion-doped region is an N-type doped region, and the semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate having a P-type well. While the transistor structure of the present invention is a P-type transistor, the first ion-doped region or the second ion-doped region is a P-type doped region, and the semiconductor substrate is an N-type semiconductor substrate or a semiconductor substrate having an N-type well.
In addition, the capacitor structure further comprises a lightly doped drain (LDD) to replace the well structure. The lightly-doped region is formed inside the semiconductor substrate under one side of the second electric-conduction gate and adjacent to the second ion-doped region. While the transistor structure is an N-type transistor, the operating method of the present invention comprises a step: respectively applying a gate voltage Vg, a source voltage Vs, a drain voltage Vd and a substrate voltage Vsub to the first electric-conduction gate (or the floating gate), the source, the drain and the semiconductor substrate, wherein in writing, Vsub=ground, Vs=Vd≥0, and Vg=HV (High Voltage), or Vsub=ground, Vs=Vd=HV, and Vg>2V, and wherein in erasing, Vsub=ground, Vs=Vd=HV, and Vg=0, floating voltage, or <2V.
While the transistor structure is a P-type transistor, the operating method of the present invention comprises a step: respectively applying a gate voltage Vg, a source voltage Vs, a drain voltage Vd and a substrate voltage Vsub to the first electric-conduction gate (or the floating gate), the source, the drain and the semiconductor substrate, wherein in writing, Vsub=HV, Vs=Vd≤HV, and Vg=0, or Vsub=HV, Vs=Vd=0, and Vg is smaller than HV=2V, and wherein in erasing, Vsub=HV, Vs=Vd=0, and Vg is floating voltage or smaller than HV=2V.
Below, embodiments are described in detail in cooperation with the attached drawings to make easily understood the objectives, technical contents, and accomplishments of the present invention.
The present invention proposes a low voltage difference operated EEPROM (Electrically Erasable Programmable Read Only Memory) and an operating method thereof. The EEPROM of the present invention is characterized in forming the undoped region to prevent the existence of the lightly doped drain (LDD) region of the conventional transistor structure. The intensity of the electric field between the gate and the transistor or between the gate and the substrate is increased, so as to decrease the voltage difference for writing or erasing. The operating method of the present invention simultaneously applies operating voltages to the gate, the source and the drain, which are connected with a memory cell, to massively write or erase memory cells.
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Spacers 22 are respectively formed on two side walls of the first dielectric layer 14 and the first electric-conduction gate 16. Before forming of the spacers 22, a light ion doping is performed on the first ion-doped regions by masking the undoped regions 17 with a mask. Then, a heavy ion doping is performed to implant with the same type of ions by using the spacers 22 as a shield to increase an ion concentration of the first ion-doped regions. There does not have any lightly doped drain (LDD) region in the first ion doped regions 18, 20. Therefore, the present invention does not affect the stability of the memory element, while to avoid increasing the complexity of the existing process to achieve the purpose of writing or erasing EEPROM in a low current.
The memory cell of the EEPROM with a single-floating gate structure further comprises a capacitor structure. The second electric-conduction gate of the capacitor is electrically connected with the first electric-conduction gate and functions as a single floating gate. The detail of different structures and the operating methods thereof will be described below.
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The embodiments have been described above to demonstrate the technical thoughts and characteristics of the present invention and enable the persons skilled in the art to understand, make, and use the present invention. However, these embodiments are only to exemplify the present invention but not to limit the scope of the present invention. Any equivalent modification or variation according to the spirit of the present invention is to be also included within the scope of the present invention.
Claims
1. A low voltage difference-operated electrically erasable programmable read only memory(EEPROM) comprising:
- a semiconductor substrate;
- at least one transistor structure formed in said semiconductor substrate and including a first dielectric layer formed on a surface of said semiconductor substrate, a first electric-conduction gate formed on said first dielectric layer, two undoped regions formed inside said semiconductor substrate under two sides of said first electric-conduction gate, and at least two first ion-doped regions formed inside said semiconductor substrate under said two sides of said first electric-conduction gate and separated from said undoped regions to function as a source and a drain; and
- a capacitor structure formed in said semiconductor substrate and separated from said transistor structure, wherein said capacitor structure includes a second ion-doped region formed inside said semiconductor substrate, a second dielectric layer formed on a surface of said second ion-doped region, and a second electric-conduction gate stacked on said second dielectric layer;
- wherein said second electric-conduction gate is electrically connected with said first electric-conduction gate to function as a single floating gate.
2. The low voltage difference-operated EEPROM according to claim 1, wherein while said transistor structure is an N-type transistor, said first ion-doped regions are N-type ion-doped regions, and said semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate with a P-type well, and wherein while said transistor structure is a P-type transistor, said first ion-doped regions are P-type ion-doped regions, and said semiconductor substrate is an N-type semiconductor substrate or a semiconductor substrate with an N-type well.
3. The low voltage difference-operated EEPROM according to claim 1, wherein said capacitor structure further comprising a lightly doped drain (LDD), and said lightly-doped region is formed inside said semiconductor substrate under one side of said second electric-conduction gate and adjacent to said second ion-doped region.
4. The low voltage difference-operated EEPROM according to claim 1, wherein two spacers are formed between said first dielectric layer and two side walls of said first electric-conduction gate of said transistor structure respectively, and said undoped regions are located inside said semiconductor substrate under said spacers.
5. The low voltage difference-operated EEPROM according to claim 4, wherein before said spacers are formed, a light ion doping is performed on said first ion-doped regions by masking said undoped regions with a mask, and then a heavy ion doping is performed to implant with the same type of ions by using the spacers as a shield to increase an ion concentration of said first ion-doped regions.
6. The low voltage difference-operated EEPROM according to claim 1, wherein said transistor structure is a metal-oxide-semiconductor field-effect transistor (MOSFET).
7. An operating method for a low voltage difference-operated electrically erasable programmable read only memory (EEPROM), wherein said low voltage difference-operated electrically erasable programmable read only memory comprises a semiconductor substrate, at least one N-type transistor and a capacitor structure, wherein said N-type transistor structure and said capacitor structure formed in said semiconductor substrate, and wherein said N-type transistor structure includes a first electric-conduction gate, two undoped regions and at least two ion-doped regions, said undoped regions formed inside said semiconductor substrate under two sides of said first electric-conduction gate, said first ion-doped regions formed inside said semiconductor substrate under said two sides of said first electric-conduction gate and separated from said undoped regions to function as a source and a drain, and wherein said capacitor structure includes a second ion-doped region, a second dielectric layer and a second electric-conduction gate, wherein said second ion-doped region formed inside said semiconductor substrate, said second dielectric layer formed on a surface of said second ion-doped region, and said second electric-conduction gate stacked on said second dielectric layer, and wherein said second electric-conduction gate is electrically connected with said first electric-conduction gate to function as a single floating gate, and wherein said method comprises a step:
- respectively applying a gate voltage Vg, a source voltage Vs, a drain voltage Vd and a substrate voltage Vsub to said first electric-conduction gate or said single floating gate, said source, said drain and said semiconductor substrate,
- wherein in writing, Vsub=ground, Vs=Vd≥0, and Vg=HV (High Voltage), or Vsub=ground, Vs=Vd=HV, and Vg>2V, and
- wherein in erasing, Vsub=ground, Vs=Vd=HV, and Vg=0, a floating voltage, or <2V.
8. The operating method for a low voltage difference-operated EEPROM according to claim 7, wherein said first ion-doped regions are N-type ion-doped regions, and said semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate with a P-type well.
9. The operating method for a low voltage difference-operated EEPROM according to claim 7, wherein said capacitor structure further comprising a lightly doped drain (LDD), and said lightly-doped region is formed inside said semiconductor substrate under one side of said second electric-conduction gate and adjacent to said second ion-doped region.
10. An operating method for a low voltage difference-operated electrically erasable programmable read only memory (EEPROM), wherein said low voltage difference-operated electrically erasable programmable read only memory comprises a semiconductor substrate, at least one P-type transistor and a capacitor structure, wherein said P-type transistor structure and said capacitor structure formed in said semiconductor substrate, and wherein said P-type transistor structure includes a first electric-conduction gate, two undoped regions and at least two ion-doped regions, said undoped regions formed inside said semiconductor substrate under two sides of said first electric-conduction gate, said first ion-doped regions formed inside said semiconductor substrate under said two sides of said first electric-conduction gate and separated from said undoped regions to function as a source and a drain, and wherein said capacitor structure includes a second ion-doped region, a second dielectric layer and a second electric-conduction gate, wherein said second ion-doped region formed inside said semiconductor substrate, said second dielectric layer formed on a surface of said second ion-doped region, and said second electric-conduction gate stacked on said second dielectric layer, and wherein said second electric-conduction gate is electrically connected with said first electric-conduction gate to function as a single floating gate, and wherein said method comprises a step:
- respectively applying a gate voltage Vg, a source voltage Vs, a drain voltage Vd and a substrate voltage Vsub to said first electric-conduction gate or said single floating gate, said source, said drain and said semiconductor substrate,
- wherein in writing, Vsub=HV (High Voltage), Vs=Vd≤HV, and Vg=0, or Vsub=HV, Vs=Vd=0, and Vg is smaller than HV=2V, and
- wherein in erasing, Vsub=HV, Vs=Vd=0, and Vg is a floating voltage or smaller than HV=2V.
11. The operating method for a low voltage difference-operated EEPROM according to claim 10, wherein said first ion-doped regions are P-type ion-doped regions, and said semiconductor substrate is a N-type semiconductor substrate or a semiconductor substrate with a N-type well.
12. The operating method for a low voltage difference-operated EEPROM according to claim 10, wherein said capacitor structure further comprising a lightly doped drain (LDD), and said lightly-doped region is formed inside said semiconductor substrate under one side of said second electric-conduction gate and adjacent to said second ion-doped region.
Type: Application
Filed: Sep 19, 2017
Publication Date: Mar 21, 2019
Inventors: HSIN-CHANG LIN (CHU-PEI CITY), WEN-CHIEN HUANG (CHU-PEI CITY), CHIA-HAO TAI (CHU-PEI CITY)
Application Number: 15/708,493