STACKED DIES AND DUMMY COMPONENTS FOR IMPROVED THERMAL PERFORMANCE
Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer. The first, second and third insulating bonding layers include a first insulating layer and a second insulating layer bonded to the first insulating layer. An insulating layer is in the first gap and another insulating layer is in the second gap.
Many current integrated circuits are formed as multiple dice on a common wafer. After the basic process steps to form the circuits on the dice are complete, the individual die are singulated from the wafer. The singulated die are then usually mounted to structures, such as circuit boards, or packaged in some form of enclosure.
One frequently-used package consists of a substrate upon which a die is mounted. The upper surface of the substrate includes electrical interconnects. The die is manufactured with a plurality of bond pads. A collection of solder joints are provided between the bond pads of the die and the substrate interconnects to establish ohmic contact. After the die is mounted to the substrate, a lid is attached to the substrate to cover the die. Some conventional integrated circuits, such as microprocessors, generate sizeable quantities of heat that must be transferred away to avoid device shutdown or damage. The lid serves as both a protective cover and a heat transfer pathway.
Stacked dice arrangements involve placing or stacking one or more semiconductor chips on a base semiconductor chip. In some conventional variants, the base semiconductor chip is a high heat dissipating device, such as a microprocessor. The stacked chips are sometimes memory devices. In a typical conventional microprocessor design, the chip itself has a floor plan with various types of logic blocks, such as floating point, integer, I/O management, and cache blocks frequently interspersed among each other. The power densities of the blocks vary: some have relatively higher power densities and some have relatively lower power densities.
The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:
Stacked semiconductor chip devices present a host of design and integration challenges for scientists and engineers. Common problems include providing adequate electrical interfaces between the stacked semiconductor chips themselves and between the individual chips and some type of circuit board, such as a motherboard or semiconductor chip package substrate, to which the semiconductor chips are mounted. Another critical design issue associated with stacked semiconductor chips is thermal management. Most electrical devices dissipate heat as a result of resistive losses, and semiconductor chips and the circuit boards that carry them are no exception. Still another technical challenge associated with stacked semiconductor chips is testing.
A process flow to transform a bare semiconductor wafer into a collection of chips and then mount those chips on packages or other boards involves a large number of individual steps. Because the processing and mounting of a semiconductor chip proceeds in a generally linear fashion, that is, various steps are usually performed in a specific order, it is desirable to be able to identify defective parts as early in a flow as possible. In this way, defective parts may be identified so that they do not undergo needless additional processing. This economic incentive to identify defective parts as early in the processing phase as possible is certainly present in the design and manufacture of stacked semiconductor chip devices.
Thermal management of semiconductor chips in a stacked arrangement remains a technical challenge during required electrical testing and operation of one or more of the semiconductor chips. A given semiconductor chip in a stacked arrangement, whether the first, an intermediary or the last in the particular stack, may dissipate heat to such an extent that active thermal management is necessary in order to either prevent the one or all of the semiconductor chips in the stack from entering thermal runaway or so that one or more of the semiconductor chips in the stack may be electrically tested at near or true operational power levels and frequencies.
One possible solution for thermal dissipation with stacks including high powered processors involves placing the processor as the top die in a stack of dies (i.e. closest to heat sink), although such techniques introduce a new power delivery challenge. Power, ground and signals will require routing up through the underlying lower power dies. This requires dense microbumps and through-chip-vias through the stacked dies, which represents significant area overheads for the stacked dies.
In accordance with one aspect of the present invention, a semiconductor chip device is provided that includes a first semiconductor chip, a second semiconductor chip stacked on the first semiconductor chip, and a first insulating bonding layer positioned between the first semiconductor chip and the second semiconductor chip and bonds the first semiconductor chip to the second semiconductor chip. The first insulating bonding layer includes a first insulating layer and a second insulating layer bonded to the first insulating layer. There are plural interconnects between and electrically connecting the first semiconductor chip and the second semiconductor chip. A first dummy component is stacked on the first semiconductor chip and separated from the second semiconductor chip by a first gap. A second insulating bonding layer is positioned between the first dummy component and the first semiconductor chip and bonds the first dummy component to the first semiconductor chip. The second insulating bonding layer includes a first insulating layer and a second insulating layer bonded to the first insulating layer. A second dummy component is stacked on the first semiconductor chip and separated from the second semiconductor chip by a second gap. A third insulating bonding layer is positioned between the second dummy component and the first semiconductor chip and bonds the second dummy component to the first semiconductor chip. The third insulating bonding layer includes a first insulating layer and a second insulating layer bonded to the first insulating layer. An insulating layer is in the first gap and another insulating layer is in the second gap.
In accordance with another aspect of the present invention, a semiconductor chip device is provided that includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. The first insulating bonding layer includes a first insulating layer and a second insulating layer bonded to the first insulating layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips is physically connected by a second insulating bonding layer. The second insulating bonding layer includes a first insulating layer and a second insulating layer bonded to the first insulating layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips is physically connected by a third insulating bonding layer. The third insulating bonding layer includes a first insulating layer and a second insulating layer bonded to the first insulating layer. An insulating layer is in the first gap and another insulating layer is in the second gap.
In accordance with another aspect of the present invention, a method of manufacturing is provided that includes stacking a second semiconductor chip on a first semiconductor chip, and forming a first insulating bonding layer between the first semiconductor chip and the second semiconductor chip that bonds the first semiconductor chip to the second semiconductor chip. The first insulating bonding layer includes a first insulating layer and a second insulating layer bonded to the first insulating layer. Plural interconnects are formed between and electrically connect the first semiconductor chip and the second semiconductor chip. A first dummy component is stacked on the first semiconductor chip and separated from the second semiconductor chip by a first gap. A second insulating bonding layer is formed between the first dummy component and the first semiconductor chip and bonds the first dummy component to the first semiconductor chip. The second insulating bonding layer includes a first insulating layer and a second insulating layer bonded to the first insulating layer. A second dummy component is stacked on the first semiconductor chip and separated from the second semiconductor chip by a second gap. A third insulating bonding layer is formed between the second dummy component and the first semiconductor chip and bonds the first dummy component to the first semiconductor chip. The third insulating bonding layer includes a first insulating layer and a second insulating layer bonded to the first insulating layer. An insulating layer is formed in the first gap and another insulating layer is formed in the second gap.
In the drawings described below, reference numerals are generally repeated where identical elements appear in more than one figure. Turning now to the drawings, and in particular to
The semiconductor chip 15 has a floor plan that includes two high heat producing areas 60 and 65 positioned to either side of a centrally located low heat producing area 70. As used herein, the terms “high” and “low” signify that the low high heat producing area 70 generates less heat than either or the combination of the high heat producing portions 60 and 65. The high heat producing area 60 can be a processor core containing portion that contains, for example, processor cores 75 and 80. A processor core is an execution portion of the semiconductor chip 15. The high heat producing area 65 can similarly be a processor core containing portion that contains, for example, processor cores 85 and 90. It should also be understood that greater than four logic cores, such as the cores 75, 80, 85 and 90 depicted, can be implemented in the semiconductor chip 15. Of course, other arrangements can be logic other than processor cores. The low heat producing area 70 can include bus logic, I/O logic, cache logic or the like. A technical goal of establishing the depicted footprint or floor plan for the semiconductor chip 15 is to, at the layout design phase, position the low heat producing area 70 in a separate location from the high heat producing areas 60 and 65 so that the chip stack 20 can be mounted where there is relatively lesser heat dissipation. To interface electrically with another component such as a circuit board or other device, the semiconductor chip 15 can include plural I/O structures 95. The I/O structures 95 can be solder balls, solder bumps, conductive pillars, or other types of interconnect structures. Well-known lead free solders, such as Sn—Ag, Sn—Ag—Cu or others can be used. Conductive pillars of copper, gold, aluminum, combinations of the these or the like can be used with or without solder caps.
Additional details of the semiconductor chip device 10 can be understood by referring now also to
As noted above, the insulating layers 56 and 58 are positioned in the gaps 180 and 185 respectively between the chip stack 20 and the dummy components 30 and 35. The dummy components 30 and 35 are advantageously positioned quite close to the chip stack 20 so that the gaps 180 and 285 are quite small and, depending upon overall device geometry, in the neighborhood of 20 to 40 microns in width. Note also that the dummy components 30 and 35 are not only sized but also positioned so that a left edge 190 of at least the lower most dummy chip 40 is coterminous or very close to coterminous with a left edge 195 of the semiconductor chip 15. The dummy component 35 is similarly constructed and positioned so that a right edge 200 of the lower most dummy chip 48 is coterminous with a right edge 205 of the semiconductor chip 15. This selection of geometry and positioning is designed to increase the available surface area for heat transfer between a semiconductor chip 15 and the dummy components 30 and 35.
The semiconductor chip 15 includes plural through-chip-vias 210, the semiconductor chip 22 includes plural through-chip-vias 215, the semiconductor chip 24 includes plural through-chip-vias 220, the semiconductor chip 26 includes plural through-chip-vias 225 and the semiconductor chip 28 includes plural through-chip-vias 230. The through-chip-vias 210, 215, 220, 225 and 230 can be composed of a variety of different conductor materials such as copper, gold, aluminum, platinum, palladium, combinations of these or the like and will typically include an insulating liner layer of silicon dioxide or other insulating material to provide isolation from the surrounding semiconductor materials. Note the location of the dashed rectangle 235, which circumscribes one of the interconnects 145 and portions of the semiconductor chips 20, 22 and 24. That portion circumscribed by the dashed rectangle 235 is shown at greater magnification in
An exemplary process for fabricating the semiconductor chip device 10 depicted in
After the dummy chips 40 and 48 and the semiconductor chip 22 are mounted to the carrier wafer 260, the dummy chips 40 and 48 and the semiconductor chip 22 are thinned to reveal the through-chip-vias 215 as shown in
Next and as shown in
Next and as shown in
As shown in
With the dummy components 30 and 35 and the chip stack 20 completed, the carrier wafer 260 depicted in
The foregoing process describes the creation of the combination of the dummy components 30 and 35 and a chip stack 20. The process to create the semiconductor chip 15 upon which that combination is ultimately mounted will now be described in conjunction with
Next and as shown in
Thereafter, the carrier wafers 322 and 330 can be removed by grinding or other removal processes to produce the essentially completed semiconductor chip device 10 depicted in
The techniques described herein can be expanded to include structures with other than two dummy components 30 and 35 depicted in
While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.
Claims
1. A semiconductor chip device, comprising:
- a first semiconductor chip;
- a second semiconductor chip stacked on the first semiconductor chip;
- a first insulating bonding layer positioned between the first semiconductor chip and the second semiconductor chip and bonding the first semiconductor chip to the second semiconductor chip, the first insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer;
- plural interconnects between and electrically connecting the first semiconductor chip and the second semiconductor chip;
- a first dummy component stacked on the first semiconductor chip and separated from the second semiconductor chip by a first gap;
- a second insulating bonding layer positioned between the first dummy component and the first semiconductor chip and bonding the first dummy component to the first semiconductor chip, the second insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer; and
- an inorganic insulating layer in the first gap.
2. The semiconductor chip device of claim 1, comprising a second dummy component stacked on the first semiconductor chip and separated from the second semiconductor chip by a second gap, another inorganic insulating layer in the second gap, and a third insulating bonding layer positioned between the second dummy component and the first semiconductor chip and bonding the second dummy component to the first semiconductor chip, the third insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer and anothcr insulating layer in the second gap.
3. The semiconductor chip device of claim 1, comprising wherein the first inorganic insulating layer of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises silicon oxynitride and the second inorganic insulating layer of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises SiOx.
4. The semiconductor chip device of claim 1, wherein the inorganic insulating layer and the another inorganic insulating layer comprise a SiOx inner core lined with silicon oxynitride.
5. The semiconductor chip device of claim 1, wherein the interconnects comprise a copper pad metallurgically bonded to a through-chip-via.
6. The semiconductor chip device of claim 2, wherein the first dummy component comprises plural dummy chips stacked together and the second dummy component comprises plural dummy chips stacked together.
7. The semiconductor chip device of claim 2, wherein the first semiconductor chip having a floor plan with a high heat producing area and a low heat producing area, the second semiconductor chip being stacked on the low heat producing area and the first dummy component and the second dummy component being stacked on the high heat producing area.
8. The semiconductor chip device of claim 7, wherein the high heat producing area comprises at least one processor core.
9. The semiconductor chip device of claim 2, wherein the second semiconductor chip comprises a first edge and a second and opposite edge, the first dummy component having an outer edge substantially coterminous with the first edge and the second dummy component having an outer edge substantially coterminous with the second edge.
10. A semiconductor chip device, comprising:
- a stack of plural semiconductor chips, each two adjacent semiconductor chips of the stack of plural semiconductor chips being electrically connected by plural interconnects and physically connected by a first insulating bonding layer, the first insulating bonding layer including a first insulating layer and a second insulating layer bonded to the first insulating layer;
- a first stack of dummy chips positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap, each two adjacent of the first stack of dummy chips being physically connected by a second insulating bonding layer, the second insulating bonding layer including a first insulating layer and a second insulating layer bonded to the first insulating layer;
- a second stack of dummy chips positioned opposite a second side of the stack of semiconductor chips and separated from the stack of plural semiconductor chips by a second gap, each two adjacent of the second stack of dummy chips being physically connected by a third insulating bonding layer, the third insulating bonding layer including a first insulating layer and a second insulating layer bonded to the first insulating layer; and
- an insulating layer in the first gap and another insulating layer in the second gap.
11. The semiconductor chip device of claim 10, comprising another semiconductor chip, the stack of semiconductor chips being positioned on the another semiconductor chip.
12. The semiconductor chip device of claim 11, wherein the another semiconductor chip having a floor plan with a high heat producing area and a low heat producing area, the stack of semiconductor chips being stacked on the low heat producing area and the first stack of dummy chips and the second stack of dummy chips being stacked on the high heat producing area.
13. The semiconductor chip device of claim 11, wherein the second semiconductor chip comprises a first edge and a second and opposite edge, the first dummy component having an outer edge substantially coterminous with the first edge and the second dummy component having an outer edge substantially coterminous with the second edge.
14. The semiconductor chip device of claim 10, comprising wherein the first insulating layer of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises silicon oxynitride and the second insulating layer of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises SiOx.
15. The semiconductor chip device of claim 10, wherein the insulating layer and the another insulating layer comprise a SiOx inner core lined with silicon oxynitride.
16. The semiconductor chip device of claim 10, wherein the interconnects comprise a copper pad metallurgically bonded to a through-chip-via.
17. A method of manufacturing, comprising:
- stacking a second semiconductor chip on a first semiconductor chip;
- forming a first insulating bonding layer between the first semiconductor chip and the second semiconductor chip bonding the first semiconductor chip to the second semiconductor chip, the first insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer;
- forming plural interconnects between and electrically connecting the first semiconductor chip and the second semiconductor chip;
- stacking a first dummy component on the first semiconductor chip and separated from the second semiconductor chip by a first gap;
- forming a second insulating bonding layer between the first dummy component and the first semiconductor chip and bonding the first dummy component to the first semiconductor chip, the second insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer; and
- forming an inorganic insulating layer in the first gap.
18. The method of claim 17, comprising stacking a second dummy component on the first semiconductor chip and separated from the second semiconductor chip by a second gap and, forming a third insulating bonding layer between the second dummy component and the first semiconductor chip and bonding the second dummy component to the first semiconductor chip, the third insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer, and forming another inorganic insulating layer in the second gap.
19. The method of claim 17, wherein the first inorganic insulating layer of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises silicon oxynitride and the second inorganic insulating layer of the of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises SiOx.
20. The method of claim 17, wherein the inorganic insulating layer and the another inorganic insulating layer comprise a SiOx inner core lined with silicon oxynitride.
21. The method of claim 18, wherein the first dummy component comprises plural dummy chips stacked together and the second dummy component comprises plural dummy chips stacked together.
22. The method of claim 18, wherein the second semiconductor chip comprises a first edge and a second and opposite edge, the first dummy component having an outer edge substantially coterminous with the first edge and the second dummy component having an outer edge substantially coterminous with the second edge.
Type: Application
Filed: Dec 17, 2017
Publication Date: Jun 20, 2019
Inventors: Rahul Agarwal (Livermore, CA), Kaushik Mysore Srinivasa Setty (Austin, TX), Milind S. Bhagavat (Los Altos, CA), Brett P. Wilkerson (Austin, TX)
Application Number: 15/844,575