Patents by Inventor Rahul Agarwal

Rahul Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240152490
    Abstract: A model management system provides a centralized repository for storing and accessing models. The model management system receives an input to store a model object in a first model state generated based on a first set of known variables. The model management system generates a first file including a first set of functions defining the first model state and associates the first file with a model key identifying the model object. The model management system receives an input to store the model object in a second model state having been generated based on the first model state and a second set of known variables. The model management system generates a second file including a second set of functions defining the second model state and associates the second file with the model key. The model management system identifies available versions of the model object based on the model key.
    Type: Application
    Filed: January 17, 2024
    Publication date: May 9, 2024
    Inventors: David Lisuk, Daniel Erenrich, Guodong Xu, Luis Voloch, Rahul Agarwal, Simon Slowik, Aleksandr Zamoshchin, Andre Frederico Cavalheiro Menck, Anirvan Mukherjee, Daniel Chin
  • Publication number: 20240154741
    Abstract: An apparatus for a communication device, the apparatus may include a processor configured to: obtain channel metrics for a plurality of radio communication channels, each obtained channel metric is associated with a respective radio communication channel of the plurality of radio communication channels, generate a plurality of channel hopping sequences, each channel hopping sequence is representative of an allocation of the plurality of radio communication channels for a plurality of time slots, wherein a number of time slots allocated for each radio communication channel within each channel hopping sequence is based on the respective obtained channel metric, and select one of the plurality of channel hopping sequences based on a predefined criterion to communicate with a further communication device.
    Type: Application
    Filed: September 27, 2023
    Publication date: May 9, 2024
    Inventors: Anshu AGARWAL, Kaushal BILLORE, Suranjan CHAKRABORTY, Amit Singh CHANDEL, Prasanna DESAI, Chandrashekar GOWDA, Vishal DHULL, Mallari HANCHATE, Mythili HEGDE, Vishnu K, Srinivas KROVVIDI, Naveen MANOHAR, Mayur MAHESHWARI, Yogesh MALKHEDE, Barath C. PETIT, Balvinder Pal SINGH, Sudhakaran SUBRAMANIAN, Rahul TIWARI, Padmavathi TIWARI, Divya Lakshmi Saranya VEMURI, Ingolf KARLS, Ehud RESHEF
  • Publication number: 20240139498
    Abstract: Systems and methods for assessment and management of adverse event risks in mechanical circulatory support patients are described herein. The method for post-operative risk mitigation in patients with an implanted Ventricular Assist Device (VAD) can include receiving a plurality of features relating to an attribute associated with the patient and ingesting at least some of the features into a multistate model. The multistate model can include a plurality of states, each corresponding to a patient condition. The method can include generating with the multistate model a daily prediction of a likelihood of the patient developing at least one of the conditions corresponding to the plurality of states in a predetermined time period, and controlling a user interface to output an indicator of the likelihood of the patient developing the at least one of the conditions in the predetermined time period.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 2, 2024
    Applicant: TC1 LLC
    Inventors: Rahul Agarwal, Rupinder Bharmi, Robert L. Kormos, Yajing Hu, Qianhul Lu, Palak Shah
  • Publication number: 20240134115
    Abstract: An edge coupler for coupling a light beam (e.g., a laser beam) into a waveguide comprises a first waveguide section characterized by a first thickness and a first constant width, a second waveguide section physically coupled to the first waveguide section and characterized by the first thickness and a gradually decreasing width, and a third waveguide section partially overlapping with the second waveguide section at an overlap region, the third waveguide section characterized by a gradually increasing width and a second thickness different from (e.g., greater than) the first thickness. In some embodiments, a surface (e.g., the top or bottom surface) of the second waveguide section and a surface (e.g., the top or bottom surface) of the third waveguide section are on a same plane.
    Type: Application
    Filed: October 17, 2023
    Publication date: April 25, 2024
    Inventors: Mohit KHURANA, John GOWARD, Rahul AGARWAL, James Ronald BONAR
  • Publication number: 20240071937
    Abstract: Embodiments of the present disclosure include techniques for a package and process for semiconductor dies. An interconnect bridge includes first conductors that electrically connect two or more semiconductor die. The interconnect bridge includes second conductors between opposite surfaces. A substrate of the interconnect bridge is removed to expose conductors of an interconnect layer that are electrically coupled to connections to the first and second semiconductor dies in a region of overlap between the semiconductor dies and interface bridge.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Rahul AGARWAL, Jon Thomas Woodyard
  • Publication number: 20240069935
    Abstract: Systems, computer program products, and methods are described herein for providing data analysis and processing using graphical user interface position mapping identification is provided. The method includes receiving a plurality of data packets from a plurality of data sources. The data packets contain one or more data metrics associated with an entity. The method also includes causing a rendering of a user interface that presents one or more selectable icons for selecting data to use from the plurality of data packets. The method further includes receiving one or more user selections of the one or more selectable icons. The one or more user selections indicate one or more of the plurality of data sources to use for a generation of a report. The method further includes generating the report based on one of more of the plurality of data packets from the selected data sources of the plurality of data sources.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: BANK OF AMERICA CORPORATION
    Inventors: Rajneesh Acharya, Ganesh Agrawal, Vikash Agarwal, Laura A. Bertarelli Hamilton, Rakesh Shah, Suresh Solomon, Susmitha Nalluri, Trishaun Tajae Blake, Mark Labbancz, Mohal Mukundbhai Sayani, Rahul Tandon, Akhil Kudal, Anju Jha, Priyanka Jyoti
  • Publication number: 20240071985
    Abstract: A method for forming a semiconductor assembly that includes forming a first set of layers on a first wafer, where one or more layers of the first set includes one or more devices of the semiconductor assembly. The method further includes forming a second set of layers on a second wafer, where one or more layers of the second set include connections between one or more of the devices of the semiconductor assembly. The method additionally includes coupling a layer of the first set to a layer of the second set using metal to metal hybrid bonding.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Inventors: RAHUL AGARWAL, CHANDRA SEKHAR MANDALAPU, RAJA SWAMINATHAN
  • Publication number: 20240070384
    Abstract: Systems, computer program products, and methods are described herein for providing a platform for generating published reports using report and worksheet building with position mapping identification. The present invention is configured to establish a reporting and analytics platform for a user interface and receive, from the user interface, a single-selection input referencing a set of system identification values associated with a first set of data in the reporting and analytics platform. The system may then display a plurality of formatting options for the set of system identification values on the user interface. The system can assign a selected formatting option to the system identification values and apply the selected formatting option to the first set of data in the reporting and analytics platform. The selected formatting options can be applied to additional sets of data based on system identification values.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: BANK OF AMERICA CORPORATION
    Inventors: Vikash Agarwal, Rahul Tandon, Suresh Solomon, Rajneesh Acharya, Mark Labbancz, Ganesh Agrawal, Laura A. Bertarelli Hamilton
  • Publication number: 20240071940
    Abstract: A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Inventors: RAHUL AGARWAL, RAJA SWAMINATHAN, MICHAEL S. ALFANO, GABRIEL H. LOH, ALAN D. SMITH, GABRIEL WONG, MICHAEL MANTOR
  • Publication number: 20240069698
    Abstract: Systems, computer program products, and methods are described herein for providing data analysis and processing using identification tagging of information on a graphical user interface. The method includes identifying a data point within a data rendering to a graphical user interface. The method also includes generating a point identification indicator for the given data point within the data rendering to the graphical user interface. The method includes receiving a user input associated with the data point within the data rendering to the graphical user interface. The user input includes a user commentary associated with the data associated with the data point within the data rendering to the graphical user interface. The method further includes associating the user input with the data point using the point identification indicator. The user input is associated with the data point within the data rendering to the graphical user interface via the point identification indicator.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Applicant: BANK OF AMERICA CORPORATION
    Inventors: Rajneesh Acharya, Vikash Agarwal, Rahul Tandon, Suresh Solomon, Mark Labbancz, Ganesh Agrawal, Laura A. Bertarelli Hamilton
  • Publication number: 20240071903
    Abstract: A semiconductor package assembly includes a die having a front surface and a back surface opposite to and parallel to the front surface. A first portion of a front surface of an interconnect die is coupled to a portion of the back surface of the die. The interconnect die includes a connectivity region that is coupled to one or more through-die vias in the die through the back surface of the die. A spacer component is coupled to a second portion of the front surface of the interconnect die. The spacer component includes conductive connections, with one or more of the conductive connections are coupled to the conductive pathways of the connectivity region of the interconnect die.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Inventors: GABRIEL H. LOH, RAJA SWAMINATHAN, RAHUL AGARWAL
  • Publication number: 20240071778
    Abstract: Embodiments of the present disclosure include techniques for a package and process for semiconductor dies. An interconnect bridge includes first conductors that electrically connect two or more semiconductor die. The interconnect bridge includes second conductors between opposite surfaces. A substrate of the interconnect bridge is removed to expose conductors of an interconnect layer that are electrically coupled to connections to the first and second semiconductor dies in a region of overlap between the semiconductor dies and interface bridge.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Rahul AGARWAL, Jon Thomas Woodyard
  • Publication number: 20240070385
    Abstract: Systems, computer program products, and methods are described herein for providing a platform for generating published reports using report and worksheet building with position mapping identification. The present invention is configured to establish a reporting and analytics platform for a user interface and receive, from the user interface, a single-selection input referencing a set of system identification values associated with a first set of data in the reporting and analytics platform. The system may then display a plurality of formatting options for the set of system identification values on the user interface. The system can assign a selected formatting option to the system identification values and apply the selected formatting option to the first set of data in the reporting and analytics platform. The selected formatting options can be applied to additional sets of data based on system identification values.
    Type: Application
    Filed: August 8, 2023
    Publication date: February 29, 2024
    Applicant: BANK OF AMERICA CORPORATION
    Inventors: Vikash Agarwal, Rahul Tandon, Suresh Solomon, Rajneesh Acharya, Mark Labbancz, Ganesh Agrawal, Laura A. Bertarelli Hamilton
  • Patent number: 11911839
    Abstract: A semiconductor device includes a first die, the first die including a first dielectric layer and a plurality of first bond pads formed within apertures in the first dielectric layer, and a second die bonded to the first die, the second die including a second dielectric layer and a plurality of second bond pads protruding from the second dielectric layer. The first die is bonded to the second die such that the plurality of second bond pads protrude into the apertures in the first dielectric layer to establish respective metallurgical bonds with the plurality of first bond pads. A reduction in the distance between the respective bond pads of the dies results in a lower temperature for establishing a hybrid bond.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: February 27, 2024
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Priyal Shah, Rahul Agarwal, Raja Swaminathan, Brett P. Wilkerson
  • Publication number: 20240063206
    Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. A first semiconductor die has a second die stacked vertically on top of it in a three-dimensional integrated circuit. The first die includes a through silicon via (TSV) interconnect that does not traverse the first die. The first die includes one or more metal layers above the TSV, which connect to a bonding pad interface through a bonding pad via. If the signals transferred through the TSV of the first die are shared by the second die, then the second die includes a TSV aligned with the bonding pad interface of the first die. If these signals are not shared by the second die, then the second die includes an insulated portion of a wafer backside aligned with the bonding pad interface.
    Type: Application
    Filed: October 30, 2023
    Publication date: February 22, 2024
    Inventors: John J. Wuu, Milind Bhagavat, Brett Wilkerson, Rahul Agarwal
  • Patent number: 11907175
    Abstract: A model management system provides a centralized repository for storing and accessing models. The model management system receives an input to store a model object in a first model state generated based on a first set of known variables. The model management system generates a first file including a first set of functions defining the first model state and associates the first file with a model key identifying the model object. The model management system receives an input to store the model object in a second model state having been generated based on the first model state and a second set of known variables. The model management system generates a second file including a second set of functions defining the second model state and associates the second file with the model key. The model management system identifies available versions of the model object based on the model key.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: February 20, 2024
    Assignee: Palantir Technologies Inc.
    Inventors: David Lisuk, Daniel Erenrich, Guodong Xu, Luis Voloch, Rahul Agarwal, Simon Slowik, Aleksandr Zamoshchin, Andre Frederico Cavalheiro Menck, Anirvan Mukherjee, Daniel Chin
  • Publication number: 20240038596
    Abstract: An apparatus and method for efficiently increasing semiconductor chip functionality in a particular area. A semiconductor fabrication process (or process) grows a silicon substrate layer, and forms multiple p-type and n-type transistors along a front side surface of the silicon substrate layer. The process flips the silicon substrate layer and removes silicon substrate leaving a particular thickness of the silicon substrate layer. The process forms multiple p-type and n-type transistors along the back side surface of the silicon substrate layer, and forms metal layers that connect terminals of the transistors formed along the back side surface to particular signals. The process forms through silicon vias (TSVs) that traverse through the silicon substrate layer. The process again flips the silicon substrate layer, and forms metal layers that connect terminals of the transistors formed along the front side surface to particular signals.
    Type: Application
    Filed: July 26, 2022
    Publication date: February 1, 2024
    Inventors: Chandra Sekhar Mandalapu, Rahul Agarwal, Rajasekaran Swaminathan, Richard T. Schultz
  • Publication number: 20240019649
    Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.
    Type: Application
    Filed: July 24, 2023
    Publication date: January 18, 2024
    Inventors: BRETT P. WILKERSON, RAJA SWAMINATHAN, KONG TOON NG, RAHUL AGARWAL
  • Patent number: 11853788
    Abstract: Disclosed are various embodiments for creating and managing virtual appliances. A command to create a virtual machine image for a hosted instance of an application image is received. The virtual machine image is created in response to receiving the command. The virtual machine image can include an operating system; a container orchestration service configured to host the instance of the application image; and a configuration service. The configuration service can be configured to at least install a management agent in response to a first boot of the virtual machine and configure the management agent to download and install the application image.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: December 26, 2023
    Assignee: VMWARE, INC.
    Inventors: Steven Taylor, Rahul Agarwal, Etienne Robert Le Sueur, Sindhu Shashidhara, Sunny Tulsi Sreedhar Murthy, Gal Yardeni, Sandhya Pai
  • Patent number: 11855061
    Abstract: A three-dimensional integrated circuit includes a first die structure having a first geometry. The first die structure includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The three-dimensional integrated circuit includes a second die structure having a second geometry. A stacked portion of the second die structure is aligned with the first region. The three-dimensional integrated circuit includes an additional die structure stacked with the first die structure and the second die structure. The additional die structure has the first geometry or the second geometry.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: December 26, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Brett P. Wilkerson, Milind S. Bhagavat, Rahul Agarwal, Dmitri Yudanov