Patents by Inventor Rahul Agarwal

Rahul Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250103806
    Abstract: The present invention provides a method and a system for character-to-character modeling for word suggestion and auto correction. The method is based on character-to-character modeling. The method involves data preparation using edit distance and hash table for encoder. The edit distance is employed for suitable candidate creation for touch input and thereafter, hash table is employed for removing invalid candidates. Furthermore, encoder-decoder model is used to encode valid candidates for touch input and then decode into word suggestions for completions. In addition, the present invention provides word suggestions from decoder, further optimized into more probable candidates using a language model with a scoring and ranking algorithm.
    Type: Application
    Filed: October 23, 2023
    Publication date: March 27, 2025
    Inventors: ANKIT PRASAD, RAHUL PRASAD, ACHYUT SAXENA, SIDDHARTH AGARWAL
  • Publication number: 20250085930
    Abstract: Systems, computer program products, and methods for determining data feed sources for interactive automated code generation and modification are provided. The method includes causing a connection with one or more data feeds. Each of the one or more data feeds are capable of providing at least one data set. The method further includes causing a transmission of a recommendation of at least one data feed. The method still further includes causing a rendering of each of the data feed(s) to an end-point device. The method also includes receiving an indication of selected data feed(s). The selected data feed(s) provide data set(s) for the flow execution. The method further includes determining an additional selected data feed from a new data feed input from the end-point device. The method also includes causing an execution of the flow with each of the selected data feeds and the additional selected data feed included.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Applicant: BANK OF AMERICA CORPORATION
    Inventors: Suresh Solomon, Ganesh Agrawal, Vikash Agarwal, Mark Labbancz, Deepak Chandrasheker Kundapur, Rahul Tandon, Rajneesh Acharya, Dharanitharan Sukumar, Manoj Narayanan
  • Publication number: 20250085839
    Abstract: Systems, computer program products, and methods for interactive automated modification of transformed data sets. The present disclosure is configured to identify at least one processed data set, wherein the processed data set comprises at least one processed data organized into at least one processed element; generate a processed data set interface component; transmit the processed data set interface component to a user device and configure a GUI of the user device with the processed data set interface component; identify at least one user input of the user device, the at least one user input comprising at least one adjustment request for the processed data set; automatically implement the at least one adjustment request to the processed data set and generate an adjusted processed data set interface component; and transmit the adjusted processed data set interface component to the user device and configure the GUI of the user device.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Applicant: BANK OF AMERICA CORPORATION
    Inventors: Suresh Solomon, Vikash Agarwal, Ganesh Agrawal, Mark Labbancz, Rahul Tandon, Rajneesh Acharya, Mohal Mukundbhai Sayani
  • Publication number: 20250086494
    Abstract: Disclosed herein are method, system, and computer product embodiments for generating a textual summary of a data set based on traversing a decision tree according to sequence and rank numbers related to a query. Subsets of the data set may receive a rank number indicating the relevancy of the subset of data to the query. In response to traversing the desicion tree, a textual summary representative of the data set and subsets of data may be generated and displayed. The textual summary may also include a course of action recommendation based on the culmination of the data set and relevant data subsets.
    Type: Application
    Filed: September 12, 2023
    Publication date: March 13, 2025
    Applicant: American Express Travel Related Services Co., Inc.
    Inventors: Varun AGARWAL, Krishnaprasad NARAYANAN, Rahul GHOSH, Swetha SRINIVASAN, Anshul JAIN, Bobby CHETAL, Ashni JAUHARY
  • Publication number: 20250085932
    Abstract: Systems, computer program products, and methods for interactive automated code generation and modification for data processing are provided. The method includes causing a rendering of a flow designer interface including a flow portion and a plugin portion. The plugin portion includes engageable plugin icon(s) corresponding to one or more plugins. The method also includes receiving a first plugin input based on engagement of a first plugin icon. The first plugin input is a selection of a first plugin. The method further includes causing a rendering of a representation of the first plugin on the flow portion. The method further includes receiving a second plugin input based on engagement of a second plugin icon. The method also includes causing a rendering of a representation of the second plugin on the flow portion. The method also includes generating a flow operation based on the flow portion of the flow designer interface.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Applicant: BANK OF AMERICA CORPORATION
    Inventors: Ganesh Agrawal, Suresh Solomon, Rajneesh Acharya, Rakesh Shah, Vikash Agarwal, Mark Labbancz, Deepak Chandrasheker Kundapur, Rahul Tandon, Laura A. Bertarelli Hamilton, Akhil Sunil Kudal, Manoj Narayanan, Mohal Mukundbhai Sayani, Anju Jha, Dharanitharan Sukumar, Rakeshkumar Prajapati, Shubhro Protim Ghosh, Arvind Kumar Rai
  • Patent number: 12249519
    Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: March 11, 2025
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Priyal Shah, Milind S. Bhagavat, Brett P. Wilkerson, Lei Fu, Rahul Agarwal
  • Publication number: 20250070031
    Abstract: A semiconductor package includes a package substrate having a first surface and an opposing second surface, and further includes an integrated circuit (IC) die disposed at the second surface and having a third surface facing the second surface and an opposing fourth surface. The IC die has a first region comprising one or more metal layers and circuit components for one or more functions of the IC die and a second region offset from the first region in a direction parallel with the third and fourth surfaces. The semiconductor package further includes a voltage regulator disposed at the fourth surface in the second region and having an input configured to receive a supply voltage and an output configured to provide a regulated voltage, and also includes a conductive path coupling the output of the voltage regulator to a voltage input of circuitry of the IC die.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Inventors: Gabriel H LOH, Raja SWAMINATHAN, Rahul AGARWAL, Brett P. WILKERSON
  • Publication number: 20250070067
    Abstract: Methods for enabling micro-bump architectures without the use of sacrificial pads for probing a wafer are described. A method includes forming: (1) a first bump in accordance with a specified first diameter, and (2) a first set of bumps in accordance with a specified second diameter, smaller than the specified first diameter. The first bump is used for probing a portion of the wafer associated with the first set of bumps. Both the first bump and the first set of bumps are then removed. The method includes forming: (1) a second set of bumps, in place of the first bump, where each of the second set of bumps is formed in accordance with the specified second diameter, and (2) a third set of bumps, in place of the first set of bumps, where each of the third set of bumps is formed in accordance with the specified second diameter.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 27, 2025
    Inventors: Rahul AGARWAL, Sriram SRINIVASAN
  • Publication number: 20250071412
    Abstract: Provided is a system and method for enhancing media. The method includes: identifying whether a scene of a first preview frame captured by at least one primary camera was captured in low light based on at least one pre-defined parameter of the first preview frame; based on identifying that the first preview frame was captured in low light, triggering at least one secondary camera to capture a second preview frame of the scene, wherein the second preview frame has an exposure time higher than an exposure time of the first preview frame, and wherein the second preview frame includes one of a higher field of view (FOV) and a same FOV as compared to the first preview frame; and generating an output frame based on the first preview frame, the second preview frame, and at least one of the at least one pre-defined parameter.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Rahul VARNA, Akshit AGARWAL, Ankur Mani TRIPATHI, Anunay SRIVASTAVA, Shivam ARORA
  • Patent number: 12237286
    Abstract: A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.
    Type: Grant
    Filed: August 25, 2023
    Date of Patent: February 25, 2025
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Rahul Agarwal
  • Patent number: 12218834
    Abstract: A logical routing element (LRE) having multiple designated instances for routing packets from physical hosts (PH) to a logical network is provided. A PH in a network segment with multiple designated instances can choose among the multiple designated instances for sending network traffic to other network nodes in the logical network according to a load balancing algorithm. Each logical interface (LIF) of an LRE is defined to be addressable by multiple identifiers or addresses, and each LIF identifier or address is assigned to a different designated instance.
    Type: Grant
    Filed: August 20, 2023
    Date of Patent: February 4, 2025
    Assignee: Nicira, Inc.
    Inventors: Vivek Agarwal, Ganesan Chandrashekhar, Rahul Korivi Subramaniyam, Ram Dular Singh, Howard Wang
  • Publication number: 20250029900
    Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.
    Type: Application
    Filed: July 25, 2024
    Publication date: January 23, 2025
    Inventors: Deepak Vasant Kulkarni, Rahul Agarwal, Rajasekaran Swaminathan, Chintan Buch
  • Publication number: 20250021569
    Abstract: An example operation may include one or more of executing queries on one or more external data stores to retrieve domain data of one or more ranked lists of assets and variables corresponding to the domain data, generating a plurality of feature groups based on the retrieved domain data and variables, wherein the plurality of feature groups correspond to a plurality of features used to generate the one or more ranked lists, converting the plurality of features groups into a plurality of values via execution of an optimization engine, transforming the plurality of values into a plurality of sentences describing the plurality of feature groups, and displaying the plurality of sentences via a user interface.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 16, 2025
    Inventors: Aaron K. Baughman, Eduardo Morales, Rahul Agarwal, Chandankumar Johakhim Patel
  • Publication number: 20250022847
    Abstract: A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.
    Type: Application
    Filed: September 30, 2024
    Publication date: January 16, 2025
    Inventors: LEI FU, BRETT P. WILKERSON, RAHUL AGARWAL
  • Publication number: 20250004951
    Abstract: An approach is provided for optimizing application caching and locking. Features specifying an operating environment of an application are extracted. The features include actual and forecasted central processing unit usage and memory, disk, and network pressure. A pairwise set of class-based and method-based ASTs and the extracted features are input into a logical neural network. Symbolic feature vectors are generated for the features by establishing bounds and flattening the features. The symbolic feature vectors and the set of class-based and method-based ASTs are input into a stacked transformer having encoders and decoders. The encoders and decoders are trained on word or token distributions of code ASTs and operating environment bounds associated with the ASTs. Using the stacked transformer, code is generated for replacing a portion of a method represented by a method-based AST. The code adds or changes caching or locking in the application.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Inventors: Aaron K. Baughman, Rahul Agarwal, Eduardo Morales, Gabriel Goodhart
  • Patent number: 12183675
    Abstract: Various molded fan-out semiconductor chip devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer that has internal conductor structures, a redistribution layer (RDL) structure positioned on the first molding layer and electrically connected to the internal conductor structures, a semiconductor chip positioned on and electrically connected to the RDL structure, and a second molding layer positioned on the RDL structure and at least partially encapsulating the semiconductor chip.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: December 31, 2024
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Rahul Agarwal, Chia-Hao Cheng, Milind S. Bhagavat
  • Publication number: 20240430538
    Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for determining a list of recommended items in response to a user query. An embodiment can generate an ordered relevance list of items, and determine an initial reward value based on an array of relevance scores and an array of revenue values corresponding to the ordered relevance list of items, a parameter alpha assigned to the array of relevance scores, and a parameter beta assigned to the array of revenue values. The embodiment can generate a next list of recommended items from an initial list of recommended items, and further calculate a next reward value associated with the next list of recommended items, and determine a list of recommended items in response to the query based on a comparison of the initial reward value and the next reward value.
    Type: Application
    Filed: June 14, 2024
    Publication date: December 26, 2024
    Applicant: Roku, Inc.
    Inventors: Rahul AGARWAL, Abhishek Majumdar, Yu Zhou, Ratul Ray, Yuzhong Li, Nitish Aggarwal, Srimaruti Manoj Nimmagadda
  • Patent number: 12174800
    Abstract: A model management system provides a centralized repository for storing and accessing models. The model management system receives an input to store a model object in a first model state generated based on a first set of known variables. The model management system generates a first file including a first set of functions defining the first model state and associates the first file with a model key identifying the model object. The model management system receives an input to store the model object in a second model state having been generated based on the first model state and a second set of known variables. The model management system generates a second file including a second set of functions defining the second model state and associates the second file with the model key. The model management system identifies available versions of the model object based on the model key.
    Type: Grant
    Filed: January 17, 2024
    Date of Patent: December 24, 2024
    Assignee: Palantir Technologies Inc.
    Inventors: David Lisuk, Daniel Erenrich, Guodong Xu, Luis Voloch, Rahul Agarwal, Simon Slowik, Aleksandr Zamoshchin, Andre Frederico Cavalheiro Menck, Anirvan Mukherjee, Daniel Chin
  • Patent number: 12170263
    Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In some embodiments, a method of manufacture includes a face-to-face process in which a first GPU chiplet and a second GPU chiplet are bonded to a temporary carrier wafer. A face surface of an active bridge chiplet is bonded to a face surface of the first and second GPU chiplets before mounting the GPU chiplets to a carrier substrate. In other embodiments, a method of manufacture includes a face-to-back process in which a face surface of an active bridge chiplet is bonded to a back surface of the first and second GPU chiplets.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 17, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Skyler J. Saleh, Ruijin Wu, Milind S. Bhagavat, Rahul Agarwal
  • Publication number: 20240413029
    Abstract: Examples are provided that relate to embedding, in a core of a substrate, an electronic component having a thickness less than a thickness of the core. One example provides an electronic device comprising a substrate comprising a core and one or more buildup layers coupled with the core, each buildup layer comprising a metal layer and a dielectric layer. The core comprises a center comprising a plurality of plies, and an additional layer comprising one or more additional plies. The electronic device further comprises an electronic component embedded in at least one of the center or the additional layer of the core. The electronic component comprises a thickness less than a thickness of the core. The electronic device further comprises an integrated circuit die coupled with the substrate and electrically connected to the electronic component.
    Type: Application
    Filed: June 12, 2023
    Publication date: December 12, 2024
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Jon Thomas WOODYARD, Rahul AGARWAL