Abstract: Creating movement in a physical environment includes extracting, by computer hardware, digital features from interactions of a user with a digital environment that models a physical environment. Physical features are extracted by the computer hardware from sensor data generated from detected interactions of the user with the physical environment. A recommendation is generated by the computer hardware for the user within the physical environment based on a correlation of the digital features with the physical features. The recommendation is provided to the user. Providing the recommendation may include generating haptic signals by decoding, using a decoder stage executed by the computer hardware, the physical features and the recommendation, wherein the haptic signals specify a movement of the user within the physical environment in furtherance of the recommendation.

Abstract: A computer-implemented method to generate training data with increased fairness. The method includes identifying a set of training data comprising at least one independent variable and dependent variable. The method includes analyzing the set of training data to identify correlations between the independent and the dependent variables. The method further includes identifying at least one correlation between the one or more independent variable and the dependent variable. The method includes calculating a fairness score for each first independent variable against the dependent variable. The method further includes creating, based on the analyzing, a fairness profile for the set of training data. The method also includes generating, by a generative adversarial network (GAN) and based on the set of training data and the fairness profile, a set of synthetic training, where the GAN is configured to increases the fairness score for each variable with a disparate effect score above a threshold.

Abstract: An example embodiment provides a method that includes one or more of executing a sequence of job steps for a job by a sequence of job step executors within a data processing pipeline, recording current job execution data generated by the sequence of job step executors during the executing of the sequence of job steps, determining whether the executing of the sequence of job steps includes a deviation based on comparing the current job execution data to historical job execution data of the data processing pipeline stored in a data store, wherein the deviation is determined by comparing a current step execution dataset to a recorded step execution dataset in the data store, and generating a failure alert when the deviation is included.

Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.

Abstract: Traditionally, version numbers for application programming interfaces are determined manually and do not convey semantic meaning. Accordingly, disclosed embodiments automatically generate a version number for an application programming interface based on the changes, if any, from a past deployment to a current deployment of the application programming interface. The version number may comprise a major version number that is incremented when a change is to the interface and affects the operation of clients that utilize the application programming interface. The version number may also comprise a minor version number that is incremented when a change is to the interface, but does not affect the operation of clients. The version number may also comprise a patch version number that is incremented when a change is only to the implementation of the application programming interface.

Abstract: A semiconductor module includes two or more semiconductor dies and an interconnect structure coupled to the two or more semiconductor dies. The interconnect structure implements a plurality of die-to-die connection pathways having a first density and a plurality of fan-out redistribution pathways having a second density that is different from the first density.

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

Abstract: Methods for enabling micro-bump architectures without the use of sacrificial pads for probing a wafer are described. A method includes forming: (1) a first bump in accordance with a specified first diameter, and (2) a first set of bumps in accordance with a specified second diameter, smaller than the specified first diameter. The first bump is used for probing a portion of the wafer associated with the first set of bumps. Both the first bump and the first set of bumps are then removed. The method includes forming: (1) a second set of bumps, in place of the first bump, where each of the second set of bumps is formed in accordance with the specified second diameter, and (2) a third set of bumps, in place of the first set of bumps, where each of the third set of bumps is formed in accordance with the specified second diameter.

Abstract: A semiconductor package includes a package substrate having a first surface and an opposing second surface, and further includes an integrated circuit (IC) die disposed at the second surface and having a third surface facing the second surface and an opposing fourth surface. The IC die has a first region comprising one or more metal layers and circuit components for one or more functions of the IC die and a second region offset from the first region in a direction parallel with the third and fourth surfaces. The semiconductor package further includes a voltage regulator disposed at the fourth surface in the second region and having an input configured to receive a supply voltage and an output configured to provide a regulated voltage, and also includes a conductive path coupling the output of the voltage regulator to a voltage input of circuitry of the IC die.

Abstract: A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.

Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

Abstract: A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.

Abstract: An example operation may include one or more of executing queries on one or more external data stores to retrieve domain data of one or more ranked lists of assets and variables corresponding to the domain data, generating a plurality of feature groups based on the retrieved domain data and variables, wherein the plurality of feature groups correspond to a plurality of features used to generate the one or more ranked lists, converting the plurality of features groups into a plurality of values via execution of an optimization engine, transforming the plurality of values into a plurality of sentences describing the plurality of feature groups, and displaying the plurality of sentences via a user interface.

Abstract: An approach is provided for optimizing application caching and locking. Features specifying an operating environment of an application are extracted. The features include actual and forecasted central processing unit usage and memory, disk, and network pressure. A pairwise set of class-based and method-based ASTs and the extracted features are input into a logical neural network. Symbolic feature vectors are generated for the features by establishing bounds and flattening the features. The symbolic feature vectors and the set of class-based and method-based ASTs are input into a stacked transformer having encoders and decoders. The encoders and decoders are trained on word or token distributions of code ASTs and operating environment bounds associated with the ASTs. Using the stacked transformer, code is generated for replacing a portion of a method represented by a method-based AST. The code adds or changes caching or locking in the application.

Abstract: Various molded fan-out semiconductor chip devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer that has internal conductor structures, a redistribution layer (RDL) structure positioned on the first molding layer and electrically connected to the internal conductor structures, a semiconductor chip positioned on and electrically connected to the RDL structure, and a second molding layer positioned on the RDL structure and at least partially encapsulating the semiconductor chip.

Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for determining a list of recommended items in response to a user query. An embodiment can generate an ordered relevance list of items, and determine an initial reward value based on an array of relevance scores and an array of revenue values corresponding to the ordered relevance list of items, a parameter alpha assigned to the array of relevance scores, and a parameter beta assigned to the array of revenue values. The embodiment can generate a next list of recommended items from an initial list of recommended items, and further calculate a next reward value associated with the next list of recommended items, and determine a list of recommended items in response to the query based on a comparison of the initial reward value and the next reward value.

Abstract: A model management system provides a centralized repository for storing and accessing models. The model management system receives an input to store a model object in a first model state generated based on a first set of known variables. The model management system generates a first file including a first set of functions defining the first model state and associates the first file with a model key identifying the model object. The model management system receives an input to store the model object in a second model state having been generated based on the first model state and a second set of known variables. The model management system generates a second file including a second set of functions defining the second model state and associates the second file with the model key. The model management system identifies available versions of the model object based on the model key.

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In some embodiments, a method of manufacture includes a face-to-face process in which a first GPU chiplet and a second GPU chiplet are bonded to a temporary carrier wafer. A face surface of an active bridge chiplet is bonded to a face surface of the first and second GPU chiplets before mounting the GPU chiplets to a carrier substrate. In other embodiments, a method of manufacture includes a face-to-back process in which a face surface of an active bridge chiplet is bonded to a back surface of the first and second GPU chiplets.

Abstract: A system including one or more processors; and one or more non-transitory computer-readable media storing computing instructions, that when executed on one or more processors, cause the one or more processors to perform certain operations including: training a first submodel of a machine learning model by at least (i) creating a cumulative addition of light gradient boosting models, and (ii) determining weights for aggregation with probabilities from the light gradient boosting models; generating, using the machine learning model, as trained, classifications for nodes, wherein the classifications comprise unions of outputs of the first submodel of the machine learning model and outputs of a second submodel of the machine learning model; and based on the classifications for the nodes, automatically tagging a portion of the nodes as deliverable in an online platform. Other embodiments are described.

Abstract: Examples are provided that relate to embedding, in a core of a substrate, an electronic component having a thickness less than a thickness of the core. One example provides an electronic device comprising a substrate comprising a core and one or more buildup layers coupled with the core, each buildup layer comprising a metal layer and a dielectric layer. The core comprises a center comprising a plurality of plies, and an additional layer comprising one or more additional plies. The electronic device further comprises an electronic component embedded in at least one of the center or the additional layer of the core. The electronic component comprises a thickness less than a thickness of the core. The electronic device further comprises an integrated circuit die coupled with the substrate and electrically connected to the electronic component.