Abstract: Methods for enabling micro-bump architectures without the use of sacrificial pads for probing a wafer are described. A method includes forming: (1) a first bump in accordance with a specified first diameter, and (2) a first set of bumps in accordance with a specified second diameter, smaller than the specified first diameter. The first bump is used for probing a portion of the wafer associated with the first set of bumps. Both the first bump and the first set of bumps are then removed. The method includes forming: (1) a second set of bumps, in place of the first bump, where each of the second set of bumps is formed in accordance with the specified second diameter, and (2) a third set of bumps, in place of the first set of bumps, where each of the third set of bumps is formed in accordance with the specified second diameter.

Abstract: Provided is a system and method for enhancing media. The method includes: identifying whether a scene of a first preview frame captured by at least one primary camera was captured in low light based on at least one pre-defined parameter of the first preview frame; based on identifying that the first preview frame was captured in low light, triggering at least one secondary camera to capture a second preview frame of the scene, wherein the second preview frame has an exposure time higher than an exposure time of the first preview frame, and wherein the second preview frame includes one of a higher field of view (FOV) and a same FOV as compared to the first preview frame; and generating an output frame based on the first preview frame, the second preview frame, and at least one of the at least one pre-defined parameter.

Abstract: A semiconductor package includes a package substrate having a first surface and an opposing second surface, and further includes an integrated circuit (IC) die disposed at the second surface and having a third surface facing the second surface and an opposing fourth surface. The IC die has a first region comprising one or more metal layers and circuit components for one or more functions of the IC die and a second region offset from the first region in a direction parallel with the third and fourth surfaces. The semiconductor package further includes a voltage regulator disposed at the fourth surface in the second region and having an input configured to receive a supply voltage and an output configured to provide a regulated voltage, and also includes a conductive path coupling the output of the voltage regulator to a voltage input of circuitry of the IC die.

Abstract: A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.

Abstract: A logical routing element (LRE) having multiple designated instances for routing packets from physical hosts (PH) to a logical network is provided. A PH in a network segment with multiple designated instances can choose among the multiple designated instances for sending network traffic to other network nodes in the logical network according to a load balancing algorithm. Each logical interface (LIF) of an LRE is defined to be addressable by multiple identifiers or addresses, and each LIF identifier or address is assigned to a different designated instance.

Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

Abstract: An example operation may include one or more of executing queries on one or more external data stores to retrieve domain data of one or more ranked lists of assets and variables corresponding to the domain data, generating a plurality of feature groups based on the retrieved domain data and variables, wherein the plurality of feature groups correspond to a plurality of features used to generate the one or more ranked lists, converting the plurality of features groups into a plurality of values via execution of an optimization engine, transforming the plurality of values into a plurality of sentences describing the plurality of feature groups, and displaying the plurality of sentences via a user interface.

Abstract: A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.

Abstract: An approach is provided for optimizing application caching and locking. Features specifying an operating environment of an application are extracted. The features include actual and forecasted central processing unit usage and memory, disk, and network pressure. A pairwise set of class-based and method-based ASTs and the extracted features are input into a logical neural network. Symbolic feature vectors are generated for the features by establishing bounds and flattening the features. The symbolic feature vectors and the set of class-based and method-based ASTs are input into a stacked transformer having encoders and decoders. The encoders and decoders are trained on word or token distributions of code ASTs and operating environment bounds associated with the ASTs. Using the stacked transformer, code is generated for replacing a portion of a method represented by a method-based AST. The code adds or changes caching or locking in the application.

Abstract: Various molded fan-out semiconductor chip devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer that has internal conductor structures, a redistribution layer (RDL) structure positioned on the first molding layer and electrically connected to the internal conductor structures, a semiconductor chip positioned on and electrically connected to the RDL structure, and a second molding layer positioned on the RDL structure and at least partially encapsulating the semiconductor chip.

Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for determining a list of recommended items in response to a user query. An embodiment can generate an ordered relevance list of items, and determine an initial reward value based on an array of relevance scores and an array of revenue values corresponding to the ordered relevance list of items, a parameter alpha assigned to the array of relevance scores, and a parameter beta assigned to the array of revenue values. The embodiment can generate a next list of recommended items from an initial list of recommended items, and further calculate a next reward value associated with the next list of recommended items, and determine a list of recommended items in response to the query based on a comparison of the initial reward value and the next reward value.

Abstract: A model management system provides a centralized repository for storing and accessing models. The model management system receives an input to store a model object in a first model state generated based on a first set of known variables. The model management system generates a first file including a first set of functions defining the first model state and associates the first file with a model key identifying the model object. The model management system receives an input to store the model object in a second model state having been generated based on the first model state and a second set of known variables. The model management system generates a second file including a second set of functions defining the second model state and associates the second file with the model key. The model management system identifies available versions of the model object based on the model key.

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In some embodiments, a method of manufacture includes a face-to-face process in which a first GPU chiplet and a second GPU chiplet are bonded to a temporary carrier wafer. A face surface of an active bridge chiplet is bonded to a face surface of the first and second GPU chiplets before mounting the GPU chiplets to a carrier substrate. In other embodiments, a method of manufacture includes a face-to-back process in which a face surface of an active bridge chiplet is bonded to a back surface of the first and second GPU chiplets.

Abstract: Examples are provided that relate to embedding, in a core of a substrate, an electronic component having a thickness less than a thickness of the core. One example provides an electronic device comprising a substrate comprising a core and one or more buildup layers coupled with the core, each buildup layer comprising a metal layer and a dielectric layer. The core comprises a center comprising a plurality of plies, and an additional layer comprising one or more additional plies. The electronic device further comprises an electronic component embedded in at least one of the center or the additional layer of the core. The electronic component comprises a thickness less than a thickness of the core. The electronic device further comprises an integrated circuit die coupled with the substrate and electrically connected to the electronic component.

Abstract: A system including one or more processors; and one or more non-transitory computer-readable media storing computing instructions, that when executed on one or more processors, cause the one or more processors to perform certain operations including: training a first submodel of a machine learning model by at least (i) creating a cumulative addition of light gradient boosting models, and (ii) determining weights for aggregation with probabilities from the light gradient boosting models; generating, using the machine learning model, as trained, classifications for nodes, wherein the classifications comprise unions of outputs of the first submodel of the machine learning model and outputs of a second submodel of the machine learning model; and based on the classifications for the nodes, automatically tagging a portion of the nodes as deliverable in an online platform. Other embodiments are described.

Abstract: A semiconductor package includes a package substrate having a first surface and an opposing second surface, and further includes an integrated circuit (IC) die disposed at the second surface and having a third surface facing the second surface and an opposing fourth surface. The IC die has a first region comprising one or more metal layers and circuit components for one or more functions of the IC die and a second region offset from the first region in a direction parallel with the third and fourth surfaces. The semiconductor package further includes a voltage regulator disposed at the fourth surface in the second region and having an input configured to receive a supply voltage and an output configured to provide a regulated voltage, and also includes a conductive path coupling the output of the voltage regulator to a voltage input of circuitry of the IC die.

Abstract: Embodiments of the present disclosure include stacked interposers, electronic circuits using stacked interposers, and techniques for manufacturing stacked interposers. In some embodiments, one or more interposers of the stacked interposers comprise capacitors. The capacitors may be coupled to power terminals of an integrated circuit. In some embodiments, stacked interposers comprise electrical connections in a metallization layer of a silicon integrated circuit. Electrical connections of different interposers may be coupled together using vias. In other embodiments, interposers are coupled together using solder bumps.

Abstract: Three-dimensional integrated circuit (3DIC) systems with the heat spreader configured as a backside power plane are described. An example 3DIC system includes a top die having a first set of through-silicon vias (TSVs) and a bottom die having a second set of TSVs for providing power, signal, and ground connectivity for components formed within the top die and the bottom die, respectively. The 3DIC system further includes a heat spreader, formed above the top die, which is configured to not only dissipate heat associated with the 3DIC system but also to deliver power to the top die using through-dielectric vias (TDVs). The TDVs are formed in an area surrounding both the bottom die and the top die. In addition, none of the second set of TSVs formed in the bottom die is configured to deliver power to the components formed within the top die.

Abstract: Within a video frame, elements are identified. A graph is constructed for a portion of video content including the video frame. Using the graph and an excitement level corresponding to an element in the plurality of elements, the video frame is divided into an alterable region and an unalterable region. By solving an optimization problem, a compute resource and a rendering application are selected, the compute resource represented by a runtime feature vector encoding a plurality of features describing execution of the rendering application on the compute resource. Using the compute resource and the rendering application, a background image corresponding to the alterable region is rendered. The unalterable region and the background image are combined into a rendered video frame, the rendered video frame replacing the video frame within the portion of video content.

Abstract: A method for detecting conflation errors in an augmented reality interface is disclosed. In one embodiment, such a method includes receiving an actual screenshot of an augmented reality interface. The method generates, using a generative adversarial network (GAN), a replica screenshot of the augmented reality interface that indicates how the actual screenshot is expected to appear. The replica screenshot is non-identical to the actual screenshot. The method receives the actual screenshot and the replica screenshot into a fractal-based convolutional neural network (CNN) to determine a correlation between the actual screenshot and the replica screenshot. In the event the correlation is below a designated threshold, the method flags the actual screenshot as having a potential conflation error. This conflation error may involve conflating a digital component for a physical component or vice versa. A corresponding system and computer program product are also disclosed.