SEMICONDUCTOR DEVICE WITH EXTENDED ELECTRICALLY-SAFE OPERATING AREA
In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type. A termination region is formed within the well, the termination region being aligned with the source region and having an end adjacent to and spaced apart from an end of the source region. The termination region comprises a semiconducting material having the second dopant type. A preselected concentration value of the dopant in the termination region is greater than a concentration value of the second dopant type in the well.
This application is a continuation of U.S. Nonprovisional patent application Ser. No. 15/988,543, filed May 24, 2018, which is a divisional of U.S. Nonprovisional patent application Ser. No. 15/596,925, filed May 16, 2017 (now U.S. Pat. No. 10,014,405), which claims the benefit of U.S. Provisional Application Ser. No. 62/441,018, filed Dec. 30, 2016, the contents of all of which are herein incorporated by reference in its entirety.
BACKGROUNDHigh-voltage metal oxide semiconductor field effect transistors (MOSFETs) often exhibit electrically safe operating area (ESOA) limitations and unsatisfactory drain-source conductance characteristics, particularly in applications where the gate-source voltage (VGS) and the drain-source voltage (VDS) are simultaneously high. These effects become more severe as the sizes of devices shrink, limiting the scaling of devices to smaller process nodes.
SUMMARYIn at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type. A termination region is formed within the well, the termination region being aligned with the source region and having an end adjacent to and spaced apart from an end of the source region. The termination region comprises a semiconducting material having the second dopant type. A preselected concentration value of the dopant in the termination region is greater than a concentration value of the second dopant type in the well.
At least some embodiments are directed to a method comprising forming a source region in a well. The source region comprises a semiconducting material having a first dopant type, and the well comprises a semiconducting material having a second dopant type opposite the first dopant type. The method also comprises implanting dopants having the second dopant type in a termination region in the well adjacent to the source region. A concentration of the dopant of the second dopant type in the termination region and a concentration of the dopant of the first dopant type in the source region are substantially the same.
At least some embodiments are directed to a semiconductor device comprising a source region formed within a well, with the source region comprising a first dopant type, and the well comprising a second dopant type opposite the first dopant type. The device also comprises a drain region comprising a first semiconducting material having the first dopant type positioned in a spaced-apart relationship with the source region. The device further comprises a drift region comprising a second semiconducting material having the first dopant type, with the drift region positioned about the drain region. The drift region is positioned in a spaced-apart relationship with the source region. A concentration of the first dopant type in the drift region has a preselected value less than another preselected value of a concentration of the first dopant type in the drain region. A portion of the well between the source region and the drift region comprises a channel region. A polysilicon gate is positioned above the drift region and channel region, where the polysilicon gate comprises a lateral extension overlying a portion of the well, and where the lateral extension extends longitudinally from an end of an end-cap portion of the polysilicon gate to an end of the source region.
For a detailed description of various embodiments, reference will now be made to the accompanying drawings, in which:
In the following discussion and in the claims, the term “based on” means “based at least in part on.” The term “about,” as used herein in conjunction with a numerical value, shall mean the recited numerical value, accounting for generally accepted variation in measurement, manufacture, and the like in the relevant industry. The term “substantially the same” means that the two values or components are either identical or are within generally accepted manufacturing tolerances of each other.
Based on the ESOA limitations described above, there is a need in the art for semiconductor devices that have an extended ESOA to operate over the full range of VGS and VDS without degraded drain-source conductance characteristics. Accordingly, embodiments of scalable, high-voltage (HV) metal-oxide semiconductor field effect transistor (MOSFET) devices with extended electrically-safe operating areas (ESOA) are described. Embodiments of the MOSFET may include poly gate extensions and termination regions aligned with and adjacent to source regions. The poly gate extensions serve as a mask for the implantations of the source and termination regions. The termination regions reduce the electric fields and consequently suppress impact ionization that is at least partially responsible for degraded drain-source conductivity characteristics in existing HV MOSFETS. In another embodiment, lateral extensions of the poly gate are positioned from the end cap region of the poly gate to near the ends of the source regions of the MOSFET. The lateral extensions of the poly gate serve to reduce electric fields in the end cap region to suppress impact ionization. As a consequence, the disclosed MOSFET has an extended ESOA and can operate with both a high drain-source voltage and a high gate-source voltage. Safe operation at both high gate-source and high drain-source voltages is advantageous in various applications, such as a switched-mode DC-DC converter with a high-side switch.
The MOSFET device 102 may include a polysilicon layer 104 (hereinafter referred to as poly gate 104), which forms the gate of device 102. In some embodiments, the poly gate 104 overlies a portion of a drift region 106 and a channel (depicted as the channel region 204 in
In some embodiments, the drift region 106 may comprise a non-uniform n-type dopant dose formed by a plurality of implants. Examples of such implants include a low-energy implant in the energy range of about 10-60 kiloelectron-volts (Kev) at a dopant dose in the range of about 1-5×1012 per square centimeter (1-5×1012/cm2), a medium-energy implant in the energy range of about 80-150 Kev at a dopant dose in the range of about 1-5×1012/cm2, and a high-energy implant in the energy range of about 200-300 Kev at a dopant dose of about 1-5×1012/cm2. The dopant concentration in the drift region, in some embodiments, may be in the rage of about 5×1015 per cc and about 1×1017 per cc. The implant energy controls the depth of the implant, thereby providing a vertical dopant concentration gradient. In at least some embodiments, the concentration of the n-type dopant in the drain region 108 is greater than about 1×1019/cc. Similarly, the source regions 110 may be highly-doped n-type regions with an n-type dopant concentration of greater than about 1×1019/cc as set forth above. However, the source regions 110 may be implanted into a shallow well (SW) 112 (only a portion of which is visible in
A local oxidation of silicon (LOCOS) region 105 may be positioned between the drift region 106 and the poly gate 104, and it may be adjacent to a gate oxide (labeled as 206 in
Positioned above and abutting the SW 112 is a back gate region 114 which, in some embodiments, is a highly-doped p-type region. The relationship between the SW 112, the source regions 110, and the back gate region 114 may be seen in the cross-sectional view of
Termination regions 118 may be formed within the SW 112. The termination regions 118 may be aligned with and adjacent to the source regions 110 and, in at least some embodiments, the termination regions 118 are longitudinally positioned beginning just beyond an end 120 of drain region 108. In embodiments in which the source regions 110 are n-type regions, the termination regions 118 may comprise highly-doped p-type material. Ends 125 of termination regions 118 are adjacent to respective ends 127 of source regions 110 and are in a spaced-apart relationship with ends 127. In at least some embodiments, the poly gate 104 may include multiple lateral extensions 122, each of which is a fin- or tab-like region that overlays at least a portion of the SW 112 and which defines a boundary region between the source regions 110 and the termination regions 118. Each lateral extension 122 serves as a mask during implantation of the n-type and p-type dopants (such as boron) that respectively form the source regions 110 and the termination regions 118. Thus, in some embodiments, the lateral extensions 122 define self-aligned structures for the source regions 110 and termination regions 118 with the spaced-apart relationship of the ends 125 and 127 defined by a longitudinal width of the lateral extensions 122. In at least some embodiments, the lateral extension 122 may have a longitudinal width co in the range of about 0.1 micron to about 1 micron, inclusive.
A portion of the SW 112 comprises a channel region 204 between the source regions 110 and the drift region 106. As described in conjunction with
As
In some embodiments, the PBL 202A is laid down on an n-type buried layer (NBL) 210. The device 102 may include several structural elements including the NBL 210 and deep n-wells 212 that serve to isolate the active region and the back gate region of the device. Highly doped regions 216, which are n-type in an NMOS device, provide a tie between deep n-wells 212 and contacts 116. The device 102 may comprise n-type impurities implanted into and through the PBL 202A and the EPI region 202B and into the NBL 210. This isolation serves, for example, to mitigate against noise propagation through the substrate 214. Further, in an isolated device, the back gate region 114 may be externally tied to the source regions 110. The contacts 116 provide for the coupling of various structures—e.g., the source regions 110, the drain region 108, and the back gate region 114—to external circuitry (not shown in
The above discussion is meant to be illustrative. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
Claims
1. A semiconductor device comprising:
- a polysilicon gate having a first edge on a first side and an opposite second edge on a second side;
- a source region formed within a well on the first side of the polysilicon gate, the source region having a first dopant type, and the well comprising a second dopant type opposite the first dopant type;
- a drain region comprising the first dopant type on the second side of the polysilicon gate;
- a termination region formed within the well, the termination region aligned with the source region on the first side of the polysilicon gate and having an end adjacent to and spaced apart from an end of the source region, the termination region comprising the second dopant type with a concentration greater than a concentration of the second dopant type in the well, wherein the polysilicon gate includes an extension that extends from the first edge between the source region and the termination region.
2. The semiconductor device of claim 1, wherein the first dopant type is an n-type dopant.
3. The semiconductor device of claim 2, wherein a concentration value of the first dopant type in the source region is greater than about 1×1019 per cubic centimeter (cc).
4. The semiconductor device of claim 1, wherein the second dopant type in the termination region is a p-type dopant.
5. The semiconductor device of claim 4, wherein the preselected concentration value of the second dopant type in the termination region is greater than about 1×1019 per cubic centimeter (cc).
6. The semiconductor device of claim 1, further comprising:
- a drift region comprising a third semiconducting material having the first dopant type, the drift region positioned about the drain region, wherein: the drift region is positioned in another spaced-apart relationship with the source region; a concentration of the first dopant type in the drift region is less than a concentration of the first dopant type in the drain region; and a portion of the well between the source region and the drift region comprises a channel region.
7. The semiconductor device of claim 6, wherein the extension has a longitudinal width, the longitudinal width defining the spaced-apart relationship between the end of the termination region adjacent to the source region and the end of the source region.
8. The semiconductor device of claim 7, wherein the longitudinal width of the extension is between about 0.1 micrometer (micron) and about 1.0 micron, inclusive.
9. The semiconductor device of claim 7, wherein the extension defines a self-aligned structure for the source and the termination regions.
10. The semiconductor device of claim 6, wherein the concentration of the first dopant type in the drift region is between about 5×1015 per cubic centimeter (cc) and about 1×1017 per cc.
11. The semiconductor device of claim 1, further comprising a back gate region wherein:
- the back gate region comprises the second dopant type having a concentration greater than the concentration value of the second dopant type in the well; and
- the back gate region is in electrical contact with the well.
12. The semiconductor device of claim 11 wherein the back gate region is electrically coupled to the termination region.
13. A semiconductor device comprising:
- a source region formed within a well, the source region comprising a first dopant type, and the well comprising a second dopant type opposite the first dopant type;
- a drain region comprising the first dopant type positioned in a spaced-apart relationship with the source region;
- a drift region comprising the first dopant type, the drift region positioned about the drain region, wherein: the drift region is positioned in a spaced-apart relationship with the source region; a concentration of the first dopant type in the drift region is less than a concentration of the first dopant type in the drain region; and a portion of the well between the source region and the drift region comprises a channel region for the formation of a channel;
- a termination region within the well, the termination region having an end adjacent to and spaced apart from an end of the source region, the termination region comprising the second dopant type with a concentration greater than a concentration of the second dopant type in the well; and
- a polysilicon gate positioned above the drift region and channel region, wherein the polysilicon gate comprises a lateral extension overlying a portion of the well, wherein the lateral extension extends longitudinally from the end of the termination region to the end of the source region.
14. The semiconductor device of claim 13, wherein:
- the first dopant type is an n-type dopant; and
- a concentration of the first dopant type in the source region is greater than about 1×1019 per cubic centimeter (cc).
15. The semiconductor device of claim 14, wherein a concentration of the second dopant type in the well is in the range of about 5×1016/cc to about 1×1018/cc.
Type: Application
Filed: Mar 15, 2019
Publication Date: Jul 11, 2019
Inventor: Xiaoju Wu (Dallas, TX)
Application Number: 16/354,550