Patents by Inventor Xiaoju Wu

Xiaoju Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10889591
    Abstract: The present invention falls within the technical field of medicine, and in particular relates to PDE9 inhibitor compounds as shown in formula (I) or pharmaceutically acceptable salts or stereoisomers thereof, and also relates to pharmaceutical preparations and pharmaceutical compositions of the compounds and the uses thereof. X1, X2, X3, X4, R1, R2, ring A, L and m are as defined in the description. The compounds can be used to prepare drugs for treating or preventing related diseases mediated by PDE9.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: January 12, 2021
    Assignee: Nanjing TransThera Biosciences Co. Ltd.
    Inventors: Frank Wu, Lin Li, Xiaoju Yang
  • Patent number: 10879387
    Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: December 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, James Robert Todd, Binghua Hu, Xiaoju Wu, Stephanie L. Hilbun
  • Publication number: 20200161471
    Abstract: A semiconductor device includes a local oxidation of silicon (LOCOS) structure and a shallow trench isolation (STI) structure formed over a semiconductor substrate. A source region is located between the LOCOS structure and the STI structure. A gate structure is located between the source region and the LOCOS structure. A contact may be located over the STI structure electrically connect to the gate structure.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Xiaoju Wu, Robert James Todd, Henry Litzmann Edwards
  • Publication number: 20200115384
    Abstract: The present invention falls within the technical field of medicine, and in particular relates to PDE9 inhibitor compounds as shown in formula (I) or pharmaceutically acceptable salts or stereoisomers thereof, and also relates to pharmaceutical preparations and pharmaceutical compositions of the compounds and the uses thereof. X1, X2, X3, X4, R1, R2, ring A, L and m are as defined in the description. The compounds can be used to prepare drugs for treating or preventing related diseases mediated by PDE9.
    Type: Application
    Filed: December 4, 2019
    Publication date: April 16, 2020
    Inventors: Frank Wu, Lin Li, Xiaoju Yang
  • Publication number: 20200075583
    Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 5, 2020
    Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
  • Patent number: 10580890
    Abstract: A semiconductor device includes a NMOS transistor with a back gate connection and a source region disposed on opposite sides of the back gate connection. The source region and back gate connection are laterally isolated by an STI oxide layer which surrounds the back gate connection. The NMOS transistor has a gate having a closed loop configuration, extending partway over a LOCOS oxide layer which surrounds, and is laterally separated from, the STI oxide layer. A lightly-doped drain layer is disposed on opposite sides of the NMOS transistor, extending under the LOCOS oxide layer to a body region of the NMOS transistor. The LOCOS oxide layer is thinner than the STI oxide layer, so that the portion of the gate over the LOCOS oxide layer provides a field plate functionality. The NMOS transistor may optionally be surrounded by an isolation structure which extends under the NMOS transistor.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: March 3, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiaoju Wu, Robert James Todd, Henry Litzmann Edwards
  • Publication number: 20200013890
    Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.
    Type: Application
    Filed: September 18, 2019
    Publication date: January 9, 2020
    Inventors: Henry Litzmann Edwards, James Robert Todd, Binghua Hu, Xiaoju Wu, Stephanie L. Hilbun
  • Publication number: 20200006549
    Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: Texas Instruments Incorporated
    Inventors: Alexei Sadovnikov, Andrew Derek Strachan, Henry Litzmann Edwards, Dhanoop Varghese, Xiaoju Wu, Binghua Hu, James Robert Todd
  • Publication number: 20200006550
    Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which a silicide block material or other protection layer is formed on a field oxide structure above a drift region to protect the field oxide structure from damage during deglaze processing. Further described examples include a shallow trench isolation (STI) structure that laterally surrounds an active region of a semiconductor substrate, where the STI structure is laterally spaced from the oxide structure, and is formed under gate contacts of the transistor.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: Texas Instruments Incorporated
    Inventors: James Robert Todd, Xiaoju Wu, Henry Litzmann Edwards, Binghua Hu
  • Patent number: 10505037
    Abstract: A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+ source and a second pwell is on an opposite side of the nwell finger including a p+ drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: December 10, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chin-Yu Tsai, Imran Khan, Xiaoju Wu
  • Patent number: 10498326
    Abstract: An interface device includes an NPN structure along a horizontal surface of a p-doped substrate. The NPN structure has a first n-doped region coupled to an output terminal, a p-doped region surrounding the first n-doped region and coupled to the output terminal, and a second n-doped region separated from the first n-doped region by the p-doped region. The interface device also includes a PNP structure along a vertical depth of the p-doped substrate. The PNP structure includes the p-doped region, an n-doped layer under the p-doped region, and the p-doped substrate. Advantageously, the interface device can withstand high voltage swing (both positive and negative), prevent sinking and sourcing large load current, and avoid entering into a low resistance mode during power down operations.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: December 3, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Rajesh Keloth, Sudheer Prasad
  • Patent number: 10461182
    Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 29, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, James Robert Todd, Binghua Hu, Xiaoju Wu, Stephanie L. Hilbun
  • Publication number: 20190214471
    Abstract: In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type. A termination region is formed within the well, the termination region being aligned with the source region and having an end adjacent to and spaced apart from an end of the source region. The termination region comprises a semiconducting material having the second dopant type. A preselected concentration value of the dopant in the termination region is greater than a concentration value of the second dopant type in the well.
    Type: Application
    Filed: March 15, 2019
    Publication date: July 11, 2019
    Inventor: Xiaoju Wu
  • Patent number: 10347732
    Abstract: In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type. A termination region is formed within the well, the termination region being aligned with the source region and having an end adjacent to and spaced apart from an end of the source region. The termination region comprises a semiconducting material having the second dopant type. A preselected concentration value of the dopant in the termination region is greater than a concentration value of the second dopant type in the well.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: July 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Xiaoju Wu
  • Patent number: 10326014
    Abstract: In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type. A termination region is formed within the well, the termination region being aligned with the source region and having an end adjacent to and spaced apart from an end of the source region. The termination region comprises a semiconducting material having the second dopant type. A preselected concentration value of the dopant in the termination region is greater than a concentration value of the second dopant type in the well.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: June 18, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Xiaoju Wu
  • Publication number: 20190172946
    Abstract: A semiconductor device includes a NMOS transistor with a back gate connection and a source region disposed on opposite sides of the back gate connection. The source region and back gate connection are laterally isolated by an STI oxide layer which surrounds the back gate connection. The NMOS transistor has a gate having a closed loop configuration, extending partway over a LOCOS oxide layer which surrounds, and is laterally separated from, the STI oxide layer. A lightly-doped drain layer is disposed on opposite sides of the NMOS transistor, extending under the LOCOS oxide layer to a body region of the NMOS transistor. The LOCOS oxide layer is thinner than the STI oxide layer, so that the portion of the gate over the LOCOS oxide layer provides a field plate functionality. The NMOS transistor may optionally be surrounded by an isolation structure which extends under the NMOS transistor.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 6, 2019
    Applicant: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Robert James Todd, Henry Litzmann Edwards
  • Publication number: 20180350794
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Application
    Filed: August 3, 2018
    Publication date: December 6, 2018
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Publication number: 20180350795
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Application
    Filed: August 3, 2018
    Publication date: December 6, 2018
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Patent number: 10090299
    Abstract: An integrated circuit with transistor regions formed on a substrate. Each transistor region includes a channel region and a terminal region. The channel region is positioned along a traverse dimension, and it includes a channel edge region along a longitudinal dimension. The terminal region is positioned adjacent to the channel region, and it is doped with a first dopant of a first conductivity type. Each transistor region may include an edge block region, which is positioned along the longitudinal dimension and adjacent to the channel edge region. The edge block region is doped with a second dopant of a second conductivity type opposite to the first conductivity type. The channel region doped with a dopant and having a first doping concentration. Each transistor region may include an edge recovery region overlapping with the channel edge region and having a second doping concentration higher than the first doping concentration.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: October 2, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiaoju Wu, C. Matthew Thompson
  • Patent number: 10083951
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 25, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu