Patents by Inventor Xiaoju Wu
Xiaoju Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11939260Abstract: Substantially alkali free glasses are disclosed with can be used to produce substrates for flat panel display devices, e.g., active-matrix liquid crystal displays (AMLCDs). The glasses have high annealing temperatures and Young's modulus. Methods for producing substantially alkali free glasses using a downdraw process (e.g., a fusion process) are also disclosed.Type: GrantFiled: August 12, 2022Date of Patent: March 26, 2024Assignee: Corning IncorporatedInventors: Venkatesh Botu, Xiaoju Guo, Ellen Anne King, Lisa Ann Lamberson, Adama Tandia, Kochuparambil Deenamma Vargheese, Jingshi Wu
-
Patent number: 11916067Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.Type: GrantFiled: March 2, 2022Date of Patent: February 27, 2024Assignee: Texas Instruments IncorporatedInventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
-
Publication number: 20220367444Abstract: A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.Type: ApplicationFiled: October 18, 2021Publication date: November 17, 2022Inventors: Robert Martin Higgins, Xiaoju Wu, Li Wang, Venugopal Balakrishna Menon
-
Patent number: 11374124Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which a silicide block material or other protection layer is formed on a field oxide structure above a drift region to protect the field oxide structure from damage during deglaze processing. Further described examples include a shallow trench isolation (STI) structure that laterally surrounds an active region of a semiconductor substrate, where the STI structure is laterally spaced from the oxide structure, and is formed under gate contacts of the transistor.Type: GrantFiled: June 28, 2018Date of Patent: June 28, 2022Assignee: Texas Instruments IncorporatedInventors: James Robert Todd, Xiaoju Wu, Henry Litzmann Edwards, Binghua Hu
-
Publication number: 20220189949Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.Type: ApplicationFiled: March 2, 2022Publication date: June 16, 2022Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
-
Publication number: 20220189946Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.Type: ApplicationFiled: March 4, 2022Publication date: June 16, 2022Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
-
Patent number: 11302688Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.Type: GrantFiled: August 3, 2018Date of Patent: April 12, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
-
Patent number: 11296075Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.Type: GrantFiled: August 31, 2018Date of Patent: April 5, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
-
Patent number: 11152505Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.Type: GrantFiled: June 28, 2018Date of Patent: October 19, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Alexei Sadovnikov, Andrew Derek Strachan, Henry Litzmann Edwards, Dhanoop Varghese, Xiaoju Wu, Binghua Hu, James Robert Todd
-
Patent number: 11094817Abstract: A semiconductor device includes a local oxidation of silicon (LOCOS) structure and a shallow trench isolation (STI) structure formed over a semiconductor substrate. A source region is located between the LOCOS structure and the STI structure. A gate structure is located between the source region and the LOCOS structure. A contact may be located over the STI structure electrically connect to the gate structure.Type: GrantFiled: January 23, 2020Date of Patent: August 17, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaoju Wu, Robert James Todd, Henry Litzmann Edwards
-
Patent number: 11049852Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.Type: GrantFiled: August 3, 2018Date of Patent: June 29, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
-
Patent number: 10879387Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.Type: GrantFiled: September 18, 2019Date of Patent: December 29, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Henry Litzmann Edwards, James Robert Todd, Binghua Hu, Xiaoju Wu, Stephanie L. Hilbun
-
Publication number: 20200161471Abstract: A semiconductor device includes a local oxidation of silicon (LOCOS) structure and a shallow trench isolation (STI) structure formed over a semiconductor substrate. A source region is located between the LOCOS structure and the STI structure. A gate structure is located between the source region and the LOCOS structure. A contact may be located over the STI structure electrically connect to the gate structure.Type: ApplicationFiled: January 23, 2020Publication date: May 21, 2020Inventors: Xiaoju Wu, Robert James Todd, Henry Litzmann Edwards
-
Publication number: 20200075583Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.Type: ApplicationFiled: August 31, 2018Publication date: March 5, 2020Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
-
Patent number: 10580890Abstract: A semiconductor device includes a NMOS transistor with a back gate connection and a source region disposed on opposite sides of the back gate connection. The source region and back gate connection are laterally isolated by an STI oxide layer which surrounds the back gate connection. The NMOS transistor has a gate having a closed loop configuration, extending partway over a LOCOS oxide layer which surrounds, and is laterally separated from, the STI oxide layer. A lightly-doped drain layer is disposed on opposite sides of the NMOS transistor, extending under the LOCOS oxide layer to a body region of the NMOS transistor. The LOCOS oxide layer is thinner than the STI oxide layer, so that the portion of the gate over the LOCOS oxide layer provides a field plate functionality. The NMOS transistor may optionally be surrounded by an isolation structure which extends under the NMOS transistor.Type: GrantFiled: December 4, 2017Date of Patent: March 3, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaoju Wu, Robert James Todd, Henry Litzmann Edwards
-
Publication number: 20200013890Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.Type: ApplicationFiled: September 18, 2019Publication date: January 9, 2020Inventors: Henry Litzmann Edwards, James Robert Todd, Binghua Hu, Xiaoju Wu, Stephanie L. Hilbun
-
Publication number: 20200006550Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which a silicide block material or other protection layer is formed on a field oxide structure above a drift region to protect the field oxide structure from damage during deglaze processing. Further described examples include a shallow trench isolation (STI) structure that laterally surrounds an active region of a semiconductor substrate, where the STI structure is laterally spaced from the oxide structure, and is formed under gate contacts of the transistor.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Applicant: Texas Instruments IncorporatedInventors: James Robert Todd, Xiaoju Wu, Henry Litzmann Edwards, Binghua Hu
-
Publication number: 20200006549Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Applicant: Texas Instruments IncorporatedInventors: Alexei Sadovnikov, Andrew Derek Strachan, Henry Litzmann Edwards, Dhanoop Varghese, Xiaoju Wu, Binghua Hu, James Robert Todd
-
Patent number: 10505037Abstract: A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+ source and a second pwell is on an opposite side of the nwell finger including a p+ drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.Type: GrantFiled: March 8, 2018Date of Patent: December 10, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Chin-Yu Tsai, Imran Khan, Xiaoju Wu
-
Patent number: 10498326Abstract: An interface device includes an NPN structure along a horizontal surface of a p-doped substrate. The NPN structure has a first n-doped region coupled to an output terminal, a p-doped region surrounding the first n-doped region and coupled to the output terminal, and a second n-doped region separated from the first n-doped region by the p-doped region. The interface device also includes a PNP structure along a vertical depth of the p-doped substrate. The PNP structure includes the p-doped region, an n-doped layer under the p-doped region, and the p-doped substrate. Advantageously, the interface device can withstand high voltage swing (both positive and negative), prevent sinking and sourcing large load current, and avoid entering into a low resistance mode during power down operations.Type: GrantFiled: December 21, 2016Date of Patent: December 3, 2019Assignee: Texas Instruments IncorporatedInventors: Xiaoju Wu, Rajesh Keloth, Sudheer Prasad