TEST SYSTEMS AND METHODS FOR CHIPS IN WAFER SCALE PHOTONIC SYSTEMS
A qualification apparatus for a photonic chip on a wafer that leaves undisturbed an edge coupler that provides an operating port for the photonic devices or circuits on the chip during normal operation in order to not introduce extra loss in the optical path of the final circuit. The qualification apparatus provides an optical path that is angled with regard to the surface of the chip, for example by using a grating coupler. The qualification apparatus can be removed after the chip is qualified. Optionally, the qualification apparatus can be left in communication with the chip and optionally employed as an input port for the chip after the chip has been separated from other chips on a common substrate.
The invention relates to systems and methods for testing semiconductor devices in general and particularly to systems and methods that provide systems and methods for qualification tests for devices present on uncut wafers.
BACKGROUND OF THE INVENTIONA significant expense in the production of optical devices is test during manufacture. The devices are fabricated on a single wafer and usually need to be diced into many separate chips that are then tested individually. When manipulating the chips individually there is the possibility of damaging the chip. Some packaging may also be needed, such as wire bonding or fiber attach, before testing can occur. Testing discrete chips that need processing before evaluating for failure is a costly process. A preferred method is to test each system on wafer before dicing the wafer into individual chips.
There is a need for improved systems and methods for qualifying photonic chips.
SUMMARY OF THE INVENTIONAccording to one aspect, the invention features a qualification apparatus for a photonic chip on a substrate, comprising: a wafer having constructed thereon at least one photonic chip, the photonic chip comprising a circuit having an operating port configured to be used during normal operation of the photonic chip, the photonic chip configured to be separated from the wafer; the wafer having constructed thereon a test port comprising a grating coupler in optical communication with the circuit, the grating coupler configured to interact with optical radiation that propagates at an angle to a free surface of the wafer, the grating coupler configured to be used during a qualification test of the photonic chip which is conducted prior to the photonic chip being separated from the wafer.
In one embodiment, the operating port comprises an edge coupler in optical communication with the circuit.
In another embodiment, the operating port comprises the grating coupler in optical communication with said circuit.
In another embodiment, the grating coupler in optical communication with the circuit is in optical communication with a second edge coupler by way of an optical waveguide, and the second edge coupler is in optical communication with the edge coupler of the photonic chip.
In yet another embodiment, the grating coupler is situated on a sacrificial region of the wafer, the sacrificial region configured to be mechanically separated from the photonic chip and discarded upon completion of the qualification test.
In still another embodiment, the grating coupler in optical communication with the circuit is in optical communication with the circuit by way of an optical waveguide and a directional coupler.
In a further embodiment, the grating coupler is situated on the photonic chip.
In yet a further embodiment, the grating coupler is configured to be removed upon completion of the qualification test.
In an additional embodiment, the grating coupler is configured to be placed onto an adjacent chip.
In one more embodiment, the grating coupler is configured to be removed upon completion of the qualification test.
According to another aspect, the invention relates to a method of manufacturing a qualification apparatus for a photonic chip on a substrate. The method comprises the steps of: fabricating on a substrate at least one photonic chip, the photonic chip comprising a circuit having an operating port configured to be used during normal operation of the photonic chip, the photonic chip configured to be separated from other photonic chips on the wafer; and fabricating on the wafer a test port comprising a grating coupler in optical communication with the circuit, the grating coupler configured to interact with optical radiation that propagates at an angle to a free surface of the wafer, the grating coupler configured to be used during a qualification test of the photonic chip which is conducted prior to the photonic chip being separated from other photonic chips on the wafer.
According to another aspect, the invention relates to a method of operating a qualification apparatus for a photonic chip on a substrate. The method comprises the steps of: providing a qualification apparatus for a photonic chip on a substrate, comprising: a photonic chip constructed on the wafer, the photonic chip comprising a circuit having an operating port configured to be used during normal operation of the photonic chip, the photonic chip configured to be separated from other photonic chips on the wafer; and a test port constructed on the wafer, the test port comprising a grating coupler in optical communication with the circuit, the grating coupler configured to interact with optical radiation that propagates at an angle to a free surface of the wafer, the grating coupler configured to be used during a qualification test of the photonic chip which is conducted prior to the photonic chip being separated from other photonic chips on the wafer; and applying an optical test signal to the test port, and providing the circuit in the photonic chip one or more required operating input signals; observing as a result a response signal from the circuit; and performing at least one of recording the result, transmitting the result to a data handling system, or to displaying the result to a user.
In one embodiment, the method of operating a qualification apparatus for a photonic chip further comprises the step of separating the photonic chip from other photonic chips on the wafer in the event that the response signal indicates that the photonic chip is acceptable.
In another embodiment, the method of operating a qualification apparatus for a photonic chip further comprises the step of removing the grating coupler upon completion of the qualification test.
In yet another embodiment, the method of operating a qualification apparatus for a photonic chip further comprises the step of placing the grating coupler onto an adjacent chip.
In still another embodiment, the method of operating a qualification apparatus for a photonic chip on a substrate further comprises the step of removing the grating coupler upon completion of the qualification test.
The foregoing and other objects, aspects, features, and advantages of the invention will become more apparent from the following description and from the claims.
The objects and features of the invention can be better understood with reference to the drawings described below, and the claims. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the drawings, like numerals are used to indicate like parts throughout the various views.
A list of acronyms and their usual meanings in the present document (unless otherwise explicitly stated to denote a different thing) are presented below.
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- AMR Adabatic Micro-Ring
- APD Avalanche Photodetector
- ARM Anti-Reflection Microstructure
- ASE Amplified Spontaneous Emission
- BER Bit Error Rate
- BOX Buried Oxide
- CMOS Complementary Metal-Oxide-Semiconductor
- CMP Chemical-Mechanical Planarization
- DBR Distributed Bragg Reflector
- DC (optics) Directional Coupler
- DC (electronics) Direct Current
- DCA Digital Communication Analyzer
- DRC Design Rule Checking
- DUT Device Under Test
- ECL External Cavity Laser
- FDTD Finite Difference Time Domain
- FOM Figure of Merit
- FSR Free Spectral Range
- FWHM Full Width at Half Maximum
- GaAs Gallium Arsenide
- InP Indium Phosphide
- LiNO3 Lithium Niobate
- LIV Light intensity(L)-Current(I)-Voltage(V)
- MFD Mode Field Diameter
- MPW Multi Project Wafer
- NRZ Non-Return to Zero
- PIC Photonic Integrated Circuits
- PRBS Pseudo Random Bit Sequence
- PDFA Praseodymium-Doped-Fiber-Amplifier
- PSO Particle Swarm Optimization
- Q Quality factor
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- QD Quantum Dot
- RSOA Reflective Semiconductor Optical Amplifier
- SOI Silicon on Insulator
- SEM Scanning Electron Microscope
- SMSR Single-Mode Suppression Ratio
- TEC Thermal Electric Cooler
- WDM Wavelength Division Multiplexing
As used herein the term “substrate” is meant to include a silicon wafer, a silicon on insulator (SOI) wafer, a semiconductor wafer comprising material such as III-V compounds such as GaAs, InP and alloys of such III-V compounds, and wafers made of materials that are not semiconducting such as quartz and alumina.
We describe systems and methods for wafer scale qualification of photonic systems that would otherwise need to be diced and processed before component qualification can occur. In brief, the systems and methods of the invention allow one to measure every chip fabricated on the substrate, decide which chips are good (e.g., pass a qualification test) and which are bad (e.g., fail at least one element of a qualification test), mark the ones that are bad, separate the individual chips (for example by dicing), readily identify the bad chips after the chips are separated, and optionally throw the bad chips away or destroy them, while keeping the good chips. In some embodiments, an edge coupler is used to provide optical input and/or to receive optical output from photonic devices (or circuits) on a chip (e.g., to behave as an operating port for the photonic devices or circuits on the chip during normal operation). In order to not introduce extra loss, it is desirable to keep the optical path of the final circuit unchanged as compared to the optical path of a test circuit. In some embodiments, the optical test circuit remains on the completed chip and may optionally be used as an input port after the chip is fabricated and separated from the other chips on the substrate.
As illustrated in the embodiment shown in
As illustrated in the embodiment shown in
One advantage of using a grating coupler is that the test signal can be applied from a source that does not have to have its optical propagation direction in the plane of the chip. In addition, a resulting optical signal that may be generated by the circuit can be observed without having to place an optical sensor or receiver in the plane of the chip. For example, an optical test source (and/or an optical sensor or receiver) can be used that is oriented at an angle to a surface of the chip, and that can be rastered over the surface of the chip, so that individual grating couplers 150 present on the chip (for example, one grating couple per circuit fabricated on the chip) can each be accessed in a convenient manner, quickly, and at reduced expense. In this manner, a plurality of circuits on the chip can be tested without having to dice or saw the chip, and the location of each circuit and whether it passed or failed a given test can be logged.
In some embodiments, the sacrificial grating coupler chip includes an optical circuit useful in testing, such as a phase modulator to test a coherent mixer or a photodetector for alignment.
As illustrated in another embodiment shown in
As illustrated in the embodiment shown in
In the embodiment of
After testing is completed, and depending on the method of facet fabrication, the testing interface (e.g., a grating coupler and/or a second edge coupler) can be removed in a variety of ways. If polishing is the approach used for facet preparation, the extra area or the test grating coupler 150, 250 can simply be polished away. If the facet is etched, the second set of edge couplers could exist on the other side of the etch trench, or the etch could proceed after circuit test. If the wafer is cleaved or sawed, the couplers could sit on opposite sides of the cleave (or saw) line. In some embodiments, such as illustrated in
In the embodiment of
In some embodiments, the gap between the edge couplers can be in the range of 50 to 100 μm. Due to the significant distance, the edge couplers can be designed to have large mode fields to minimize the optical divergence to just a few degrees.
In a further embodiment, the etched facets are angled, so that one can deflect the optical beam of the edge coupler of the optical circuit in one direction or another. The second edge coupler can be designed to be higher or lower in the back end to match the location where the optical beam will hit. Further, the second edge couple may be configured such that the optical output propagates at an angle opposite the first edge coupler so that the two modes will overlap for minimal optical loss.
Various additional embodiments and features can be used with the systems and methods of the invention.
One can use on-chip photodiodes as monitors for edge couplers, using either taps or the structure shown in
In some embodiments, one can use a plurality of coupler structures in sequence in order to characterize system losses.
In some embodiments, one can use couplers facing one another across a wafer-scale etched trench, in order to directly characterize coupling losses.
In some embodiments, grating coupled taps can be used to observe signals from an actual system such as a coherent transceiver, so as to allow testing of the actual edge facet that will be used and will be coupled to an optical fiber.
In some embodiments, one can provide lithographically designed in-plane lenses on one or two axes in combination with the chip.
In some embodiments, one may integrate polarization controllers and rotators with these structures.
In some embodiments, one may integrate additional electro-optical circuitry in the test structure to aid in the qualification of the chips, such as an on-chip phase modulator.
In some embodiments, one may integrate large photodiodes across the trench from the optical circuit's edge couplers, so as to monitor parameters such as insertion loss.
Design and FabricationMethods of designing and fabricating devices having elements similar to those described herein are described in one or more of U.S. Pat. Nos. 7,200,308, 7,339,724, 7,424,192, 7,480,434, 7,643,714, 7,760,970, 7,894,696, 8,031,985, 8,067,724, 8,098,965, 8,203,115, 8,237,102, 8,258,476, 8,270,778, 8,280,211, 8,311,374, 8,340,486, 8,380,016, 8,390,922, 8,798,406, and 8,818,141, each of which documents is hereby incorporated by reference herein in its entirety.
Test Apparatus and MethodsMethods of testing photonic devices having elements similar to those described herein, and various kinds of test apparatus, are described in one or more of U.S. Pat. Nos. 7,200,308, 7,339,724, 7,424,192, 7,480,434, 7,643,714, 7,760,970, 7,894,696, 8,031,985, 8,067,724, 8,098,965, 8,203,115, 8,237,102, 8,258,476, 8,270,778, 8,280,211, 8,311,374, 8,340,486, 8,380,016, 8,390,922, 8,798,406, and 8,818,141, each of which documents is hereby incorporated by reference herein in its entirety.
DefinitionsAs used herein, the term “optical communication channel” is intended to denote a single optical channel, such as light that can carry information using a specific carrier wavelength in a wavelength division multiplexed (WDM) system.
As used herein, the term “optical carrier” is intended to denote a medium or a structure through which any number of optical signals including WDM signals can propagate, which by way of example can include gases such as air, a void such as a vacuum or extraterrestrial space, and structures such as optical fibers and optical waveguides.
Theoretical DiscussionAlthough the theoretical description given herein is thought to be correct, the operation of the devices described and claimed herein does not depend upon the accuracy or validity of the theoretical description. That is, later theoretical developments that may explain the observed results on a basis different from the theory presented herein will not detract from the inventions described herein.
Any patent, patent application, patent application publication, journal article, book, published paper, or other publicly available material identified in the specification is hereby incorporated by reference herein in its entirety. Any material, or portion thereof, that is said to be incorporated by reference herein, but which conflicts with existing definitions, statements, or other disclosure material explicitly set forth herein is only incorporated to the extent that no conflict arises between that incorporated material and the present disclosure material. In the event of a conflict, the conflict is to be resolved in favor of the present disclosure as the preferred disclosure.
While the present invention has been particularly shown and described with reference to the preferred mode as illustrated in the drawing, it will be understood by one skilled in the art that various changes in detail may be affected therein without departing from the spirit and scope of the invention as defined by the claims.
Claims
1-16. (canceled)
17. A wafer comprising:
- a plurality of photonic chips defined in or upon the wafer, the plurality of photonic chips including at least one photonic chip comprising: a photonic integrated circuit (PIC); an operating port configured to be used during normal operation of the at least one photonic chip after a separation thereof from the wafer; a test port configured for testing the PIC prior to the separation from the wafer; a first optical waveguide connecting the operating port to the PIC; and, a device disposed to couple test light from the test port into the first optical waveguide to be guided into the PIC.
18. The wafer of claim 17 comprising wherein the at least one photonic chip is separated from another photonic chip defined in or upon the wafer by a dicing line, and wherein the operating port comprises an edge port disposed at the dicing line.
19. The wafer of claim 17 wherein the test port comprises a grating coupler configured to receive the test light that propagates at an angle to a free surface of the wafer.
20. The wafer of claim 17 further comprising a second optical waveguide connecting the test port to the directional coupler.
21. The wafer of claim 20 wherein the test port is configured to couple the test light that propagates at an angle to a free surface of the wafer into the second optical waveguide.
22. The wafer of claim 17 comprising a semiconductor material.
23. The wafer of claim 17 comprising silicon on insulator.
24. The wafer of claim 17 wherein the device comprises a directional coupler.
Type: Application
Filed: Jun 12, 2019
Publication Date: Sep 26, 2019
Inventors: Ari Novack (New York, NY), Matthew Akio Streshinsky (New York, NY), Michael J. Hochberg (New York, NY)
Application Number: 16/439,196