VIDEO PREDICTION USING SPATIALLY DISPLACED CONVOLUTION

Abstract

A neural network architecture is disclosed for performing video frame prediction using a sequence of video frames and corresponding pairwise optical flows. The neural network processes the sequence of video frames and optical flows utilizing three-dimensional convolution operations, where time (or multiple video frames in the sequence of video frames) provides the third dimension in addition to the two-dimensional pixel space of the video frames. The neural network generates a set of parameters used to predict a next video frame in the sequence of video frames by sampling a previous video frame utilizing spatially-displaced convolution operations. In one embodiment, the set of parameters includes a displacement vector and at least one convolution kernel per pixel. Generating a pixel value in the next video frame includes applying the convolution kernel to a corresponding patch of pixels in the previous video frame based on the displacement vector.

Description

CLAIM OF PRIORITY

This application claims the benefit of U.S. Provisional Application No. 62/646,309 titled “Video Prediction using Spatially Displaced Convolution,” filed Mar. 21, 2018, the entire contents of which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to generating frames of video using a deep learning neural network. More particularly, the present disclosure relates to generation of high-resolution video frames based on past frames in the sequence of video frames and past optical flows.

BACKGROUND

Video prediction is the task of inferring future frames of video in a video sequence based on past frames of video in the video sequence. The ability to predict future frames of video has applications in various domains ranging from future state estimation for self-driving vehicles (i.e., predicting the location of objects in the vehicles' paths) to video analysis. For a video prediction algorithm or model to perform well, the algorithm or model should accurately capture not only the optical flow of objects from frame to frame, but also predict how the displacement between frames affects the visibility and appearance of surrounding objects. In other words, the algorithm or model need not only predict motion of objects from one location to the next, but also must predict occlusions or dis-occlusions.

Prior art solutions in the video prediction space typically rely on re-sampling past frames, guided by a predicted optical flow for the new frame. For example, an optical flow can be predicted that estimates a motion vector associated with each pixel of the predicted frame, and the motion vector can be used to sample a pixel value from a past frame based on an offset specified by the motion vector. However, these algorithms typically fail where dis-occlusions result in the incorrect pixel color for the pixel in the predicted frame, as that pixel color was occluded by a different object in the past frame. Alternatively, the prior art solutions can implement techniques for direct generation of pixels, such as by using a generative adversarial network (GAN) that create estimates for the predicted frame and then reject or accept the estimates based on a comparison with a known set of acceptable results. However, GAN models typically produce blurry results that can be easy to identify as fake.

More recent approaches synthesize pixel values by convolving an input patch with a predicted kernel, where the coefficients of the kernel are learned by a neural network. However, memory requirements increase with kernel size and satisfactory results usually require extremely large kernels in order to properly capture large displacements in the optical flow. Thus, there is a need for addressing these issues and/or other issues associated with the prior art.

SUMMARY

A method, computer readable medium, and system are disclosed for implementing a deep learning neural network to perform video frame prediction to produce high-resolution video frames based on a sequence of previous video frames. The deep learning neural network model estimates a displacement vector and a convolution kernel for each pixel of the predicted video frame. A separate spatially-displaced convolution module, for each pixel of the predicted video frame then applies the predicted convolution kernel for the pixel to a patch of pixels in a previous video frame. The patch of pixels in the previous video frame corresponds to a window that is offset from a corresponding pixel in the previous video frame based on the predicted displacement vector.

In one embodiment, a computer-implemented method for generating a predicted video frame in a sequence of video frames is described. The method includes the steps of receiving an input that includes the sequence of video frames and at least one optical flow; processing the input by layers of a first neural network to generate a set of parameters; and generating the predicted video frame based on the set of parameters. Each optical flow maps pixels from a particular video frame to motion vectors that identify corresponding pixels in a corresponding video frame in the sequence of video frames. The set of parameters includes a displacement vector and at least one convolution kernel for each pixel of a plurality of pixels in the predicted video frame.

In one embodiment, generating the predicted video frame includes, for each pixel of the plurality of pixels in the predicted video frame, identifying a patch of pixels in a previous video frame in the sequence of video frames based on the displacement vector for the pixel and applying a convolution operation to the patch of pixels utilizing the at least one convolution kernel. In one embodiment, the at least one convolution kernel includes a two-dimensional convolution kernel. In other embodiments, the at least one convolution kernel includes a first one-dimensional convolution kernel associated with a horizontal dimension and a second one-dimensional convolution kernel associated with a vertical dimension. In some embodiments, the convolution operation includes generating a two-dimensional convolution kernel based on the first one-dimensional convolution kernel and the second one-dimensional convolution kernel.

In one embodiment, the method further includes the steps of receiving the sequence of video frames and processing the sequence of video frames by layers of a second neural network to generate the at least one optical flow. In other words, the second neural network can be implemented in a pre-processing step to generate the input, at least in part, for the first neural network.

In one embodiment, the first neural network includes an encoder section and a decoder section. The encoder section includes a plurality of stages, where each stage in the plurality of stages of the encoder section includes one or more convolution layers and a down-sampling layer. The decoder section also includes a plurality of stages, where each stage in the plurality of stages of the decoder section includes a convolution layer and an up-sampling layer. In one embodiment, each stage in the plurality of stages of the decoder section also includes a deconvolution layer.

In one embodiment, an output of each stage in the plurality of stages of the decoder section concatenates a feature map generated by the up-sampling layer to a feature map generated by the deconvolution layer. An input of each stage in the plurality of stages of the decoder section concatenates a feature map generated by the down-sampling layer of a corresponding stage of the encoder section to the output of a previous stage of the decoder section.

In one embodiment, the first neural network is trained, at least in part, based on a loss function that includes a perceptual loss component and a style loss component.

In one embodiment, a system is described for predicting video frames in a sequence of video frames. The system includes a memory storing a sequence of video frames and at least one optical flow. The system also includes at least one parallel processing unit coupled to the memory. The at least one parallel processing unit is configured to implement, at least in part, a first neural network configured to process the sequence of video frames and the at least one optical flow to generate a set of parameters and a spatially-displaced convolution (SDC) module configured to generate the predicted video frame based on the set of parameters. Each optical flow in the at least one optical flow corresponding to a pair of video frames in the sequence of video frames. The set of parameters includes a displacement vector and at least one convolution kernel for each pixel of a plurality of pixels in a predicted video frame.

In one embodiment, the at least one parallel processing unit is further configured to implement, at least in part, a second neural network configured to process the sequence of video frames to generate the at least one optical flow. In one embodiment, the at least one parallel processing unit includes a first parallel processing unit configured to implement the first neural network and a second parallel processing unit configured to implement the second neural network. In one embodiment, the at least one parallel processing unit includes a first parallel processing unit coupled to a second parallel processing unit via a high-speed interconnect.

In one embodiment, a non-transitory computer-readable media storing computer instructions for performing video prediction is described. The computer instruction, when executed by one or more processors, cause the one or more processors to perform the steps of: receiving an input that includes the sequence of video frames and at least one optical flow; processing the input by layers of a first neural network to generate a set of parameters; and generating the predicted video frame based on the set of parameters. Each optical flow maps pixels from a particular video frame to motion vectors that identify corresponding pixels in a corresponding video frame in the sequence of video frames. The set of parameters includes a displacement vector and at least one convolution kernel for each pixel of a plurality of pixels in the predicted video frame.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a flowchart of a method for predicting a video frame based on a sequence of video frames, in accordance with an embodiment.

FIG. 2 illustrates a video prediction system, in accordance with some embodiments.

FIG. 3 illustrates a parallel processing unit, in accordance with an embodiment.

FIG. 4A illustrates a general processing cluster within the parallel processing unit of FIG. 3, in accordance with an embodiment.

FIG. 4B illustrates a memory partition unit of the parallel processing unit of FIG. 3, in accordance with an embodiment.

FIG. 5A illustrates the streaming multi-processor of FIG. 4A, in accordance with an embodiment.

FIG. 5B is a conceptual diagram of a processing system implemented using the PPU of FIG. 3, in accordance with an embodiment.

FIG. 5C illustrates an exemplary system in which the various architecture and/or functionality of the various previous embodiments may be implemented.

FIG. 6A illustrates a motion-vector based sampling approach to the video prediction problem, in accordance with the prior art.

FIG. 6B illustrates a kernel based sampling approach to pixel synthesis, in accordance with the prior art.

FIG. 6C illustrates an SDC-based sampling approach to pixel synthesis, in accordance with some embodiments.

FIG. 7 illustrates an SDC-based sampling approach to pixel synthesis using 1D convolution kernels, in accordance with some embodiments.

FIG. 8 illustrates a deep learning neural network architecture of the second neural network of FIG. 2, in accordance with some embodiments.

FIG. 9 illustrates a flowchart of a method for training the second neural network of FIG. 2, in accordance with some embodiments.

DETAILED DESCRIPTION

The following Figures describe an approach for performing video prediction by conditioning a deep learning neural network to learn based on past frames and past optical flows. Re-sampling previous frames based on optical flow alone is insufficient because the technique cannot adequately handle dis-occlusions. Generative models currently produce blurry results that are easy to identify as synthetic. The described spatially-displaced convolution approach utilizes a deep learning neural network to predict a displacement vector and a convolution kernel to apply to a patch of pixels in the previous video frame specified by the displacement vector. This approach combines the best aspects of vector-based or convolution-based techniques, while ameliorating the respective disadvantages of those techniques.

The methods and systems described below include a neural network that processes a sequence of video frames and optical flows to generate parameters for sampling a previous video frame. The sampling of the previous video frame, based on the parameters, is performed to generate pixel values for a predicted video frame, which is the next video frame following the sequence of video frames. The parameters include a displacement vector and one or more convolution kernels for each pixel of the predicted video frame. A spatially-displaced convolution module receives the set of parameters for a pixel of the predicted video frame and samples the previous video frame by performing a convolution operation on a corresponding patch of pixels displaced from a corresponding pixel in the previous video frame. The patch of pixels is identified using the displacement vector from the set of parameters for the pixel and is offset from the corresponding pixel in the previous video frame by a magnitude of the displacement vector. In some embodiments, the methods and system also include a second neural network that pre-processes the sequence of video frames to generate the optical flows.

It will be appreciated that conventional convolution operations apply a convolution kernel to a sliding window in an image to produce many different pixel values for a filtered image. As used herein, the predicted convolution kernels are only applied to a single patch of pixels in a previous video frame to generate one pixel value in the predicted video frame. Each pixel of the predicted video frame is therefore associated with a different predicted convolution kernel and a corresponding displacement vector.

FIG. 1 illustrates a flowchart of a method 100 for predicting a video frame based on a sequence of video frames, in accordance with an embodiment. Although method 100 is described in the context of a processing unit, the method 100 may also be performed by a program, custom circuitry, or by a combination of custom circuitry and a program. For example, the method 100 may be executed by a GPU (graphics processing unit), CPU (central processing unit), or any processor capable of implementing a deep learning neural network or the spatially-displaced convolution (SDC) module, as described in more detail below. Furthermore, persons of ordinary skill in the art will understand that any system that performs method 100 is within the scope and spirit of embodiments of the present disclosure.

At step 102, an input is received that includes a sequence of video frames and at least one optical flow. Each optical flow maps pixels from a particular video frame to motion vectors that identify corresponding pixels in a corresponding video frame (e.g., an earlier frame in the case of backward flow and a later frame in the case of forward flow) in the sequence of video frames. In one embodiment, each optical flow is a pairwise pure backward optical flow for two adjacent video frames in the sequence of video frames.

In one embodiment, the sequence of video frames is received and the at least one optical flow is generated by processing the sequence of video frames via a neural network. In one embodiment, a number of video frames in the sequence of video frames is greater than a number of optical flows in the at least one optical flow, where the difference between the number of video frames and the number of optical flows is equal to one.

At step 104, the input is processed by layers of a first neural network to generate a set of parameters. In one embodiment, the set of parameters includes a displacement vector and at least one convolution kernel for each pixel of a plurality of pixels in a predicted video frame. In one embodiment, the at least one convolution kernel is a two-dimensional convolution kernel. In another embodiment, the at least one convolution kernel includes a first one-dimensional convolution kernel associated with a horizontal dimension and a second one-dimensional convolution kernel associated with a vertical dimension. In one embodiment, the pair of one-dimensional convolution kernels can be utilized to generate a two-dimensional, separable convolution kernel.

At step 106, the predicted video frame is generated based on the set of parameters. In one embodiment, an SDC module generates pixel values for the predicted video frame by, for each pixel of the plurality of pixels in the predicted video frame: identifying a patch of pixels in a previous video frame in the sequence of video frames based on the displacement vector for the pixel, and applying a convolution operation to the patch of pixels utilizing the at least one convolution kernel. In one embodiment, the previous video frame is a last video frame in the sequence of video frames that will immediately precede the predicted video frame in the updated sequence of video frames.

More illustrative information will now be set forth regarding various optional architectures and features with which the foregoing framework may be implemented, per the desires of the user. It should be strongly noted that the following information is set forth for illustrative purposes and should not be construed as limiting in any manner. Any of the following features may be optionally incorporated with or without the exclusion of other features described.

FIG. 2 illustrates a video prediction system 200, in accordance with some embodiments. As depicted in FIG. 2, the video prediction system 200 includes first neural network 210, a second neural network 220, and a spatially-displaced convolution (SDC) module 230. The video prediction system 200 receives a sequence of video frames 202 I_1:t(x, y) as an input and generates a next predicted video frame 232 I_t+1(x, y) in the sequence, where t is equal to the number of video frames in the sequence.

In one embodiment, the first neural network 210 receives the sequence of video frames 202 and generates a plurality of optical flows 212 corresponding to pairs of video frames in the sequence. In other words, the first neural network 210 calculates inter-frame optical flows for each corresponding pair of adjacent video frames in the sequence of video frames 202. In one embodiment, the first neural network 210 is implemented as Flownet, as described in Ilg et al., “Flownet 2.0: Evolution of optical flow estimation with deep networks,” IEEE Conference on Computer Vision and Pattern Recognition (CVPR), vol. 2 (2017), which is herein incorporated by reference in its entirety. In other embodiments, the first neural network 210 can have any other technically feasible implementation of a deep learning neural network that generates inter-frame optical flow fields as an output of the deep learning neural network.

In one embodiment, the first neural network 210 is configured to receive five video frames [I_t(x, y), I_t−1(x, y), I_t−2(x, y), I_t−3(x, y), I_t−4(x, y)] in the sequence of video frames 202. The first neural network 210 then generates four optical flows [F_t(x, y), F_t−1(x, y), F_t−2(x, y), F_t−3(x, y)] 212. The first optical flow F_t(x, y) corresponds with frames I_t(x, y) and I_t−1(x, y); the second optical flow F_t−1(x, y) corresponds with frames I_t−1(x, y) and I_t−2(x, y); the third optical flow F_t−2(x, y) corresponds with frames I_t−2(x, y) and I_t−3(x, y); and the fourth optical flow F_t−3(x, y) corresponds with frames I_t−3(x, y) and I_t−4(x, y). Each optical flow F_j(x, y) maps each pixel p having pixel coordinates (x, y) in video frame I_j to a motion vector (u, v) that represents a displacement for that pixel to a corresponding pixel {dot over (p)} having pixel coordinates (x+u, y+v) in video frame I_j−1.

In one embodiment, the second neural network 220 is configured to receive the sequence of video frames 202 and the corresponding set of optical flows 212 as an input to the second neural network 220. The second neural network 220 generates a set of parameters 222 for an SDC operation. In one embodiment, the set of parameters 222 includes a displacement vector and a corresponding predicted convolution kernel for each pixel of the predicted video frame I_t+1(x, y) 232. In one embodiment, the set of parameters 222 includes a first two-dimensional (2D) map for u-coordinates and a second 2D map for v-coordinates that, in combination, define the displacement vector for each pixel of the predicted video frame I_t+1(x, y) 232. In one embodiment, the set of parameters 222 also includes a set of 2D maps corresponding to each coefficient index of a 2D convolution kernel. For example, the set of 2D maps can include nine 2D maps corresponding to the nine different coefficient indices of a 3×3 convolution kernel.

In yet another embodiment, the 2D convolution kernel can be separable into two one-dimensional (1) convolution kernels corresponding to the x-axis and the y-axis of the predicted video frame I_t+1(x, y) 232. For example, the 3×3 2D convolution kernel can be separable into two 3-element 1D convolutions in the horizontal and vertical directions. It will be appreciated that larger 2D convolution kernels can be approximated using a pair of 1D convolution kernels. For example, an 11×11 2D convolution kernel having 121 coefficients can instead be approximated by two 11 element 1D convolution kernels totaling 22 coefficients. Using a pair of 1D convolution kernels instead of a full 2D convolution kernel can decrease the complexity of the processing performed by the second neural network 220 considerably as a much smaller number of coefficients needs to be estimated. Furthermore, training of the second neural network 220 is significantly sped up by reducing the number of learned attributes (e.g., weights and/or biases) within the network when the output comprises a much smaller subset of convolution coefficients.

In one embodiment, the SDC module 230 receives the set of parameters 222 from the second neural network 220 and the previous video frame I_t(x, y) 224 from the sequence of video frames 202, and the SDC module 230 generates the predicted video frame 232 utilizing the predicted convolution kernels and corresponding displacement vectors. The SDC module 230 generates each pixel in the predicted video frame 232 by sampling a spatially-displaced patch of pixels from the previous video frame I_t(x, y) 224, defined by the predicted displacement vector for the pixel, utilizing the predicted convolution kernel for the pixel. The SDC module 230 repeats the convolution operation for each of the pixels of the predicted video frame 232 using different predicted convolution kernels and displacement vectors for each pixel.

It will be appreciated that the video prediction system 200 utilizes at least two video frames in a sequence and at least one optical flow to generate a next video frame in the sequence. In exemplary embodiments, the video prediction system 200 utilizes at least three video frames in the sequence and at least two optical flows to generate the next video frame in the sequence.

Although the video prediction system 200 is described in the context of processing units, one or more of the first neural network 210, the second neural network 220, and the third neural network 230 may be implemented as a program, custom circuitry, or by a combination of custom circuitry and a program. For example, the neural networks may be implemented by a GPU (graphics processing unit), CPU (central processing unit), or any processor capable of implementing layers of a neural network. Furthermore, persons of ordinary skill in the art will understand that any system that performs the operations of the video prediction system 200 is within the scope and spirit of embodiments of the present disclosure. One such example of a parallel processing unit for implemented one or more of the units included in the video prediction system 200 is described in more detail below.

Parallel Processing Architecture

FIG. 3 illustrates a parallel processing unit (PPU) 300, in accordance with an embodiment. In an embodiment, the PPU 300 is a multi-threaded processor that is implemented on one or more integrated circuit devices. The PPU 300 is a latency hiding architecture designed to process many threads in parallel. A thread (e.g., a thread of execution) is an instantiation of a set of instructions configured to be executed by the PPU 300. In an embodiment, the PPU 300 is a graphics processing unit (GPU) configured to implement a graphics rendering pipeline for processing three-dimensional (3D) graphics data in order to generate two-dimensional (2D) image data for display on a display device such as a liquid crystal display (LCD) device. In other embodiments, the PPU 300 may be utilized for performing general-purpose computations. While one exemplary parallel processor is provided herein for illustrative purposes, it should be strongly noted that such processor is set forth for illustrative purposes only, and that any processor may be employed to supplement and/or substitute for the same.

One or more PPUs 300 may be configured to accelerate thousands of High Performance Computing (HPC), data center, and machine learning applications. The PPU 300 may be configured to accelerate numerous deep learning systems and applications including autonomous vehicle platforms, deep learning, high-accuracy speech, image, and text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimizations, and personalized user recommendations, and the like.

As shown in FIG. 3, the PPU 300 includes an Input/Output (I/O) unit 305, a front end unit 315, a scheduler unit 320, a work distribution unit 325, a hub 330, a crossbar (Xbar) 370, one or more general processing clusters (GPCs) 350, and one or more memory partition units 380. The PPU 300 may be connected to a host processor or other PPUs 300 via one or more high-speed NVLink 310 interconnect. The PPU 300 may be connected to a host processor or other peripheral devices via an interconnect 302. The PPU 300 may also be connected to a local memory comprising a number of memory devices 304. In an embodiment, the local memory may comprise a number of dynamic random access memory (DRAM) devices. The DRAM devices may be configured as a high-bandwidth memory (HBM) subsystem, with multiple DRAM dies stacked within each device.

The NVLink 310 interconnect enables systems to scale and include one or more PPUs 300 combined with one or more CPUs, supports cache coherence between the PPUs 300 and CPUs, and CPU mastering. Data and/or commands may be transmitted by the NVLink 310 through the hub 330 to/from other units of the PPU 300 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). The NVLink 310 is described in more detail in conjunction with FIG. 5B.

The I/O unit 305 is configured to transmit and receive communications (e.g., commands, data, etc.) from a host processor (not shown) over the interconnect 302. The I/O unit 305 may communicate with the host processor directly via the interconnect 302 or through one or more intermediate devices such as a memory bridge. In an embodiment, the I/O unit 305 may communicate with one or more other processors, such as one or more the PPUs 300 via the interconnect 302. In an embodiment, the I/O unit 305 implements a Peripheral Component Interconnect Express (PCIe) interface for communications over a PCIe bus and the interconnect 302 is a PCIe bus. In alternative embodiments, the I/O unit 305 may implement other types of well-known interfaces for communicating with external devices.

The I/O unit 305 decodes packets received via the interconnect 302. In an embodiment, the packets represent commands configured to cause the PPU 300 to perform various operations. The I/O unit 305 transmits the decoded commands to various other units of the PPU 300 as the commands may specify. For example, some commands may be transmitted to the front end unit 315. Other commands may be transmitted to the hub 330 or other units of the PPU 300 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). In other words, the I/O unit 305 is configured to route communications between and among the various logical units of the PPU 300.

In an embodiment, a program executed by the host processor encodes a command stream in a buffer that provides workloads to the PPU 300 for processing. A workload may comprise several instructions and data to be processed by those instructions. The buffer is a region in a memory that is accessible (e.g., read/write) by both the host processor and the PPU 300. For example, the I/O unit 305 may be configured to access the buffer in a system memory connected to the interconnect 302 via memory requests transmitted over the interconnect 302. In an embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the PPU 300. The front end unit 315 receives pointers to one or more command streams. The front end unit 315 manages the one or more streams, reading commands from the streams and forwarding commands to the various units of the PPU 300.

The front end unit 315 is coupled to a scheduler unit 320 that configures the various GPCs 350 to process tasks defined by the one or more streams. The scheduler unit 320 is configured to track state information related to the various tasks managed by the scheduler unit 320. The state may indicate which GPC 350 a task is assigned to, whether the task is active or inactive, a priority level associated with the task, and so forth. The scheduler unit 320 manages the execution of a plurality of tasks on the one or more GPCs 350.

The scheduler unit 320 is coupled to a work distribution unit 325 that is configured to dispatch tasks for execution on the GPCs 350. The work distribution unit 325 may track a number of scheduled tasks received from the scheduler unit 320. In an embodiment, the work distribution unit 325 manages a pending task pool and an active task pool for each of the GPCs 350. The pending task pool may comprise a number of slots (e.g., 32 slots) that contain tasks assigned to be processed by a particular GPC 350. The active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by the GPCs 350. As a GPC 350 finishes the execution of a task, that task is evicted from the active task pool for the GPC 350 and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC 350. If an active task has been idle on the GPC 350, such as while waiting for a data dependency to be resolved, then the active task may be evicted from the GPC 350 and returned to the pending task pool while another task in the pending task pool is selected and scheduled for execution on the GPC 350.

The work distribution unit 325 communicates with the one or more GPCs 350 via XBar 370. The XBar 370 is an interconnect network that couples many of the units of the PPU 300 to other units of the PPU 300. For example, the XBar 370 may be configured to couple the work distribution unit 325 to a particular GPC 350. Although not shown explicitly, one or more other units of the PPU 300 may also be connected to the XBar 370 via the hub 330.

The tasks are managed by the scheduler unit 320 and dispatched to a GPC 350 by the work distribution unit 325. The GPC 350 is configured to process the task and generate results. The results may be consumed by other tasks within the GPC 350, routed to a different GPC 350 via the XBar 370, or stored in the memory 304. The results can be written to the memory 304 via the memory partition units 380, which implement a memory interface for reading and writing data to/from the memory 304. The results can be transmitted to another PPU 304 or CPU via the NVLink 310. In an embodiment, the PPU 300 includes a number U of memory partition units 380 that is equal to the number of separate and distinct memory devices 304 coupled to the PPU 300. A memory partition unit 380 will be described in more detail below in conjunction with FIG. 4B.

In an embodiment, a host processor executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 300. In an embodiment, multiple compute applications are simultaneously executed by the PPU 300 and the PPU 300 provides isolation, quality of service (QoS), and independent address spaces for the multiple compute applications. An application may generate instructions (e.g., API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU 300. The driver kernel outputs tasks to one or more streams being processed by the PPU 300. Each task may comprise one or more groups of related threads, referred to herein as a warp. In an embodiment, a warp comprises 32 related threads that may be executed in parallel. Cooperating threads may refer to a plurality of threads including instructions to perform the task and that may exchange data through shared memory. Threads and cooperating threads are described in more detail in conjunction with FIG. 5A.

FIG. 4A illustrates a GPC 350 of the PPU 300 of FIG. 3, in accordance with an embodiment. As shown in FIG. 4A, each GPC 350 includes a number of hardware units for processing tasks. In an embodiment, each GPC 350 includes a pipeline manager 410, a pre-raster operations unit (PROP) 415, a raster engine 425, a work distribution crossbar (WDX) 480, a memory management unit (MMU) 490, and one or more Data Processing Clusters (DPCs) 420. It will be appreciated that the GPC 350 of FIG. 4A may include other hardware units in lieu of or in addition to the units shown in FIG. 4A.

In an embodiment, the operation of the GPC 350 is controlled by the pipeline manager 410. The pipeline manager 410 manages the configuration of the one or more DPCs 420 for processing tasks allocated to the GPC 350. In an embodiment, the pipeline manager 410 may configure at least one of the one or more DPCs 420 to implement at least a portion of a graphics rendering pipeline. For example, a DPC 420 may be configured to execute a vertex shader program on the programmable streaming multiprocessor (SM) 440. The pipeline manager 410 may also be configured to route packets received from the work distribution unit 325 to the appropriate logical units within the GPC 350. For example, some packets may be routed to fixed function hardware units in the PROP 415 and/or raster engine 425 while other packets may be routed to the DPCs 420 for processing by the primitive engine 435 or the SM 440. In an embodiment, the pipeline manager 410 may configure at least one of the one or more DPCs 420 to implement a neural network model and/or a computing pipeline.

The PROP unit 415 is configured to route data generated by the raster engine 425 and the DPCs 420 to a Raster Operations (ROP) unit, described in more detail in conjunction with FIG. 4B. The PROP unit 415 may also be configured to perform optimizations for color blending, organize pixel data, perform address translations, and the like.

The raster engine 425 includes a number of fixed function hardware units configured to perform various raster operations. In an embodiment, the raster engine 425 includes a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, and a tile coalescing engine. The setup engine receives transformed vertices and generates plane equations associated with the geometric primitive defined by the vertices. The plane equations are transmitted to the coarse raster engine to generate coverage information (e.g., an x, y coverage mask for a tile) for the primitive. The output of the coarse raster engine is transmitted to the culling engine where fragments associated with the primitive that fail a z-test are culled, and transmitted to a clipping engine where fragments lying outside a viewing frustum are clipped. Those fragments that survive clipping and culling may be passed to the fine raster engine to generate attributes for the pixel fragments based on the plane equations generated by the setup engine. The output of the raster engine 425 comprises fragments to be processed, for example, by a fragment shader implemented within a DPC 420.

Each DPC 420 included in the GPC 350 includes an M-Pipe Controller (MPC) 430, a primitive engine 435, and one or more SMs 440. The MPC 430 controls the operation of the DPC 420, routing packets received from the pipeline manager 410 to the appropriate units in the DPC 420. For example, packets associated with a vertex may be routed to the primitive engine 435, which is configured to fetch vertex attributes associated with the vertex from the memory 304. In contrast, packets associated with a shader program may be transmitted to the SM 440.

The SM 440 comprises a programmable streaming processor that is configured to process tasks represented by a number of threads. Each SM 440 is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads concurrently. In an embodiment, the SM 440 implements a SIMD (Single-Instruction, Multiple-Data) architecture where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same set of instructions. All threads in the group of threads execute the same instructions. In another embodiment, the SM 440 implements a SIMT (Single-Instruction, Multiple Thread) architecture where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but where individual threads in the group of threads are allowed to diverge during execution. In an embodiment, a program counter, call stack, and execution state is maintained for each warp, enabling concurrency between warps and serial execution within warps when threads within the warp diverge. In another embodiment, a program counter, call stack, and execution state is maintained for each individual thread, enabling equal concurrency between all threads, within and between warps. When execution state is maintained for each individual thread, threads executing the same instructions may be converged and executed in parallel for maximum efficiency. The SM 440 will be described in more detail below in conjunction with FIG. 5A.

The MMU 490 provides an interface between the GPC 350 and the memory partition unit 380. The MMU 490 may provide translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In an embodiment, the MMU 490 provides one or more translation lookaside buffers (TLBs) for performing translation of virtual addresses into physical addresses in the memory 304.

FIG. 4B illustrates a memory partition unit 380 of the PPU 300 of FIG. 3, in accordance with an embodiment. As shown in FIG. 4B, the memory partition unit 380 includes a Raster Operations (ROP) unit 450, a level two (L2) cache 460, and a memory interface 470. The memory interface 470 is coupled to the memory 304. Memory interface 470 may implement 32, 64, 128, 1024-bit data buses, or the like, for high-speed data transfer. In an embodiment, the PPU 300 incorporates U memory interfaces 470, one memory interface 470 per pair of memory partition units 380, where each pair of memory partition units 380 is connected to a corresponding memory device 304. For example, PPU 300 may be connected to up to Y memory devices 304, such as high bandwidth memory stacks or graphics double-data-rate, version 5, synchronous dynamic random access memory, or other types of persistent storage.

In an embodiment, the memory interface 470 implements an HBM2 memory interface and Y equals half U. In an embodiment, the HBM2 memory stacks are located on the same physical package as the PPU 300, providing substantial power and area savings compared with conventional GDDR5 SDRAM systems. In an embodiment, each HBM2 stack includes four memory dies and Y equals 4, with HBM2 stack including two 128-bit channels per die for a total of 8 channels and a data bus width of 1024 bits.

In an embodiment, the memory 304 supports Single-Error Correcting Double-Error Detecting (SECDED) Error Correction Code (ECC) to protect data. ECC provides higher reliability for compute applications that are sensitive to data corruption. Reliability is especially important in large-scale cluster computing environments where PPUs 300 process very large datasets and/or run applications for extended periods.

In an embodiment, the PPU 300 implements a multi-level memory hierarchy. In an embodiment, the memory partition unit 380 supports a unified memory to provide a single unified virtual address space for CPU and PPU 300 memory, enabling data sharing between virtual memory systems. In an embodiment the frequency of accesses by a PPU 300 to memory located on other processors is traced to ensure that memory pages are moved to the physical memory of the PPU 300 that is accessing the pages more frequently. In an embodiment, the NVLink 310 supports address translation services allowing the PPU 300 to directly access a CPU's page tables and providing full access to CPU memory by the PPU 300.

In an embodiment, copy engines transfer data between multiple PPUs 300 or between PPUs 300 and CPUs. The copy engines can generate page faults for addresses that are not mapped into the page tables. The memory partition unit 380 can then service the page faults, mapping the addresses into the page table, after which the copy engine can perform the transfer. In a conventional system, memory is pinned (e.g., non-pageable) for multiple copy engine operations between multiple processors, substantially reducing the available memory. With hardware page faulting, addresses can be passed to the copy engines without worrying if the memory pages are resident, and the copy process is transparent.

Data from the memory 304 or other system memory may be fetched by the memory partition unit 380 and stored in the L2 cache 460, which is located on-chip and is shared between the various GPCs 350. As shown, each memory partition unit 380 includes a portion of the L2 cache 460 associated with a corresponding memory device 304. Lower level caches may then be implemented in various units within the GPCs 350. For example, each of the SMs 440 may implement a level one (L1) cache. The L1 cache is private memory that is dedicated to a particular SM 440. Data from the L2 cache 460 may be fetched and stored in each of the L1 caches for processing in the functional units of the SMs 440. The L2 cache 460 is coupled to the memory interface 470 and the XBar 370.

The ROP unit 450 performs graphics raster operations related to pixel color, such as color compression, pixel blending, and the like. The ROP unit 450 also implements depth testing in conjunction with the raster engine 425, receiving a depth for a sample location associated with a pixel fragment from the culling engine of the raster engine 425. The depth is tested against a corresponding depth in a depth buffer for a sample location associated with the fragment. If the fragment passes the depth test for the sample location, then the ROP unit 450 updates the depth buffer and transmits a result of the depth test to the raster engine 425. It will be appreciated that the number of memory partition units 380 may be different than the number of GPCs 350 and, therefore, each ROP unit 450 may be coupled to each of the GPCs 350. The ROP unit 450 tracks packets received from the different GPCs 350 and determines which GPC 350 that a result generated by the ROP unit 450 is routed to through the Xbar 370. Although the ROP unit 450 is included within the memory partition unit 380 in FIG. 4B, in other embodiment, the ROP unit 450 may be outside of the memory partition unit 380. For example, the ROP unit 450 may reside in the GPC 350 or another unit.

FIG. 5A illustrates the streaming multi-processor 440 of FIG. 4A, in accordance with an embodiment. As shown in FIG. 5A, the SM 440 includes an instruction cache 505, one or more scheduler units 510, a register file 520, one or more processing cores 550, one or more special function units (SFUs) 552, one or more load/store units (LSUs) 554, an interconnect network 580, a shared memory/L1 cache 570.

As described above, the work distribution unit 325 dispatches tasks for execution on the GPCs 350 of the PPU 300. The tasks are allocated to a particular DPC 420 within a GPC 350 and, if the task is associated with a shader program, the task may be allocated to an SM 440. The scheduler unit 510 receives the tasks from the work distribution unit 325 and manages instruction scheduling for one or more thread blocks assigned to the SM 440. The scheduler unit 510 schedules thread blocks for execution as warps of parallel threads, where each thread block is allocated at least one warp. In an embodiment, each warp executes 32 threads. The scheduler unit 510 may manage a plurality of different thread blocks, allocating the warps to the different thread blocks and then dispatching instructions from the plurality of different cooperative groups to the various functional units (e.g., cores 550, SFUs 552, and LSUs 554) during each clock cycle.

Cooperative Groups is a programming model for organizing groups of communicating threads that allows developers to express the granularity at which threads are communicating, enabling the expression of richer, more efficient parallel decompositions. Cooperative launch APIs support synchronization amongst thread blocks for the execution of parallel algorithms. Conventional programming models provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., the syncthreads( ) function). However, programmers would often like to define groups of threads at smaller than thread block granularities and synchronize within the defined groups to enable greater performance, design flexibility, and software reuse in the form of collective group-wide function interfaces.

Cooperative Groups enables programmers to define groups of threads explicitly at sub-block (e.g., as small as a single thread) and multi-block granularities, and to perform collective operations such as synchronization on the threads in a cooperative group. The programming model supports clean composition across software boundaries, so that libraries and utility functions can synchronize safely within their local context without having to make assumptions about convergence. Cooperative Groups primitives enable new patterns of cooperative parallelism, including producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

A dispatch unit 515 is configured to transmit instructions to one or more of the functional units. In the embodiment, the scheduler unit 510 includes two dispatch units 515 that enable two different instructions from the same warp to be dispatched during each clock cycle. In alternative embodiments, each scheduler unit 510 may include a single dispatch unit 515 or additional dispatch units 515.

Each SM 440 includes a register file 520 that provides a set of registers for the functional units of the SM 440. In an embodiment, the register file 520 is divided between each of the functional units such that each functional unit is allocated a dedicated portion of the register file 520. In another embodiment, the register file 520 is divided between the different warps being executed by the SM 440. The register file 520 provides temporary storage for operands connected to the data paths of the functional units.

Each SM 440 comprises L processing cores 550. In an embodiment, the SM 440 includes a large number (e.g., 128, etc.) of distinct processing cores 550. Each core 550 may include a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes a floating point arithmetic logic unit and an integer arithmetic logic unit. In an embodiment, the floating point arithmetic logic units implement the IEEE 754-2008 standard for floating point arithmetic. In an embodiment, the cores 550 include 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

Tensor cores configured to perform matrix operations, and, in an embodiment, one or more tensor cores are included in the cores 550. In particular, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In an embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

In an embodiment, the matrix multiply inputs A and B are 16-bit floating point matrices, while the accumulation matrices C and D may be 16-bit floating point or 32-bit floating point matrices. Tensor Cores operate on 16-bit floating point input data with 32-bit floating point accumulation. The 16-bit floating point multiply requires 64 operations and results in a full precision product that is then accumulated using 32-bit floating point addition with the other intermediate products for a 4×4×4 matrix multiply. In practice, Tensor Cores are used to perform much larger two-dimensional or higher dimensional matrix operations, built up from these smaller elements. An API, such as CUDA 9 C++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use Tensor Cores from a CUDA-C++ program. At the CUDA level, the warp-level interface assumes 16×16 size matrices spanning all 32 threads of the warp.

Each SM 440 also comprises M SFUs 552 that perform special functions (e.g., attribute evaluation, reciprocal square root, and the like). In an embodiment, the SFUs 552 may include a tree traversal unit configured to traverse a hierarchical tree data structure. In an embodiment, the SFUs 552 may include texture unit configured to perform texture map filtering operations. In an embodiment, the texture units are configured to load texture maps (e.g., a 2D array of texels) from the memory 304 and sample the texture maps to produce sampled texture values for use in shader programs executed by the SM 440. In an embodiment, the texture maps are stored in the shared memory/L1 cache 470. The texture units implement texture operations such as filtering operations using mip-maps (e.g., texture maps of varying levels of detail). In an embodiment, each SM 340 includes two texture units.

Each SM 440 also comprises NLSUs 554 that implement load and store operations between the shared memory/L1 cache 570 and the register file 520. Each SM 440 includes an interconnect network 580 that connects each of the functional units to the register file 520 and the LSU 554 to the register file 520, shared memory/L1 cache 570. In an embodiment, the interconnect network 580 is a crossbar that can be configured to connect any of the functional units to any of the registers in the register file 520 and connect the LSUs 554 to the register file and memory locations in shared memory/L1 cache 570.

The shared memory/L1 cache 570 is an array of on-chip memory that allows for data storage and communication between the SM 440 and the primitive engine 435 and between threads in the SM 440. In an embodiment, the shared memory/L1 cache 570 comprises 128 KB of storage capacity and is in the path from the SM 440 to the memory partition unit 380. The shared memory/L1 cache 570 can be used to cache reads and writes. One or more of the shared memory/L1 cache 570, L2 cache 460, and memory 304 are backing stores.

Combining data cache and shared memory functionality into a single memory block provides the best overall performance for both types of memory accesses. The capacity is usable as a cache by programs that do not use shared memory. For example, if shared memory is configured to use half of the capacity, texture and load/store operations can use the remaining capacity. Integration within the shared memory/L1 cache 570 enables the shared memory/L1 cache 570 to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data.

When configured for general purpose parallel computation, a simpler configuration can be used compared with graphics processing. Specifically, the fixed function graphics processing units shown in FIG. 3, are bypassed, creating a much simpler programming model. In the general purpose parallel computation configuration, the work distribution unit 325 assigns and distributes blocks of threads directly to the DPCs 420. The threads in a block execute the same program, using a unique thread ID in the calculation to ensure each thread generates unique results, using the SM 440 to execute the program and perform calculations, shared memory/L1 cache 570 to communicate between threads, and the LSU 554 to read and write global memory through the shared memory/L1 cache 570 and the memory partition unit 380. When configured for general purpose parallel computation, the SM 440 can also write commands that the scheduler unit 320 can use to launch new work on the DPCs 420.

The PPU 300 may be included in a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, and the like. In an embodiment, the PPU 300 is embodied on a single semiconductor substrate. In another embodiment, the PPU 300 is included in a system-on-a-chip (SoC) along with one or more other devices such as additional PPUs 300, the memory 204, a reduced instruction set computer (RISC) CPU, a memory management unit (MMU), a digital-to-analog converter (DAC), and the like.

In an embodiment, the PPU 300 may be included on a graphics card that includes one or more memory devices 304. The graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In yet another embodiment, the PPU 300 may be an integrated graphics processing unit (iGPU) or parallel processor included in the chipset of the motherboard.

Exemplary Computing System

Systems with multiple GPUs and CPUs are used in a variety of industries as developers expose and leverage more parallelism in applications such as artificial intelligence computing. High-performance GPU-accelerated systems with tens to many thousands of compute nodes are deployed in data centers, research facilities, and supercomputers to solve ever larger problems. As the number of processing devices within the high-performance systems increases, the communication and data transfer mechanisms need to scale to support the increased bandwidth.

FIG. 5B is a conceptual diagram of a processing system 500 implemented using the PPU 300 of FIG. 3, in accordance with an embodiment. The exemplary system 565 may be configured to implement the method 100 shown in FIG. 1. The processing system 500 includes a CPU 530, switch 510, and multiple PPUs 300 each coupled to respective memories 304. The NVLink 310 provides high-speed communication links between each of the PPUs 300. Although a particular number of NVLink 310 and interconnect 302 connections are illustrated in FIG. 5B, the number of connections to each PPU 300 and the CPU 530 may vary. The switch 510 interfaces between the interconnect 302 and the CPU 530. The PPUs 300, memories 304, and NVLinks 310 may be situated on a single semiconductor platform to form a parallel processing module 525. In an embodiment, the switch 510 supports two or more protocols to interface between various different connections and/or links.

In another embodiment (not shown), the NVLink 310 provides one or more high-speed communication links between each of the PPUs 300 and the CPU 530 and the switch 510 interfaces between the interconnect 302 and each of the PPUs 300. The PPUs 300, memories 304, and interconnect 302 may be situated on a single semiconductor platform to form a parallel processing module 525. In yet another embodiment (not shown), the interconnect 302 provides one or more communication links between each of the PPUs 300 and the CPU 530 and the switch 510 interfaces between each of the PPUs 300 using the NVLink 310 to provide one or more high-speed communication links between the PPUs 300. In another embodiment (not shown), the NVLink 310 provides one or more high-speed communication links between the PPUs 300 and the CPU 530 through the switch 510. In yet another embodiment (not shown), the interconnect 302 provides one or more communication links between each of the PPUs 300 directly. One or more of the NVLink 310 high-speed communication links may be implemented as a physical NVLink interconnect or either an on-chip or on-die interconnect using the same protocol as the NVLink 310.

In the context of the present description, a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit fabricated on a die or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with increased connectivity which simulate on-chip operation and make substantial improvements over utilizing a conventional bus implementation. Of course, the various circuits or devices may also be situated separately or in various combinations of semiconductor platforms per the desires of the user. Alternately, the parallel processing module 525 may be implemented as a circuit board substrate and each of the PPUs 300 and/or memories 304 may be packaged devices. In an embodiment, the CPU 530, switch 510, and the parallel processing module 525 are situated on a single semiconductor platform.

In an embodiment, the signaling rate of each NVLink 310 is 20 to 25 Gigabits/second and each PPU 300 includes six NVLink 310 interfaces (as shown in FIG. 5B, five NVLink 310 interfaces are included for each PPU 300). Each NVLink 310 provides a data transfer rate of 25 Gigabytes/second in each direction, with six links providing 300 Gigabytes/second. The NVLinks 310 can be used exclusively for PPU-to-PPU communication as shown in FIG. 5B, or some combination of PPU-to-PPU and PPU-to-CPU, when the CPU 530 also includes one or more NVLink 310 interfaces.

In an embodiment, the NVLink 310 allows direct load/store/atomic access from the CPU 530 to each PPU's 300 memory 304. In an embodiment, the NVLink 310 supports coherency operations, allowing data read from the memories 304 to be stored in the cache hierarchy of the CPU 530, reducing cache access latency for the CPU 530. In an embodiment, the NVLink 310 includes support for Address Translation Services (ATS), allowing the PPU 300 to directly access page tables within the CPU 530. One or more of the NVLinks 310 may also be configured to operate in a low-power mode.

FIG. 5C illustrates an exemplary system 565 in which the various architecture and/or functionality of the various previous embodiments may be implemented. The exemplary system 565 may be configured to implement the method 100 shown in FIG. 1.

As shown, a system 565 is provided including at least one central processing unit 530 that is connected to a communication bus 575. The communication bus 575 may be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol(s). The system 565 also includes a main memory 540. Control logic (software) and data are stored in the main memory 540 which may take the form of random access memory (RAM).

The system 565 also includes input devices 560, the parallel processing system 525, and display devices 545, e.g. a conventional CRT (cathode ray tube), LCD (liquid crystal display), LED (light emitting diode), plasma display or the like. User input may be received from the input devices 560, e.g., keyboard, mouse, touchpad, microphone, and the like. Each of the foregoing modules and/or devices may even be situated on a single semiconductor platform to form the system 565. Alternately, the various modules may also be situated separately or in various combinations of semiconductor platforms per the desires of the user.

Further, the system 565 may be coupled to a network (e.g., a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, or the like) through a network interface 535 for communication purposes.

The system 565 may also include a secondary storage (not shown). The secondary storage 610 includes, for example, a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, digital versatile disk (DVD) drive, recording device, universal serial bus (USB) flash memory. The removable storage drive reads from and/or writes to a removable storage unit in a well-known manner.

Computer programs, or computer control logic algorithms, may be stored in the main memory 540 and/or the secondary storage. Such computer programs, when executed, enable the system 565 to perform various functions. The memory 540, the storage, and/or any other storage are possible examples of computer-readable media.

The architecture and/or functionality of the various previous figures may be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and/or any other desired system. For example, the system 565 may take the form of a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, a mobile phone device, a television, workstation, game consoles, embedded system, and/or any other type of logic.

While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Machine Learning

Deep neural networks (DNNs) developed on processors, such as the PPU 300 have been used for diverse use cases, from self-driving cars to faster drug development, from automatic image captioning in online image databases to smart real-time language translation in video chat applications. Deep learning is a technique that models the neural learning process of the human brain, continually learning, continually getting smarter, and delivering more accurate results more quickly over time. A child is initially taught by an adult to correctly identify and classify various shapes, eventually being able to identify shapes without any coaching. Similarly, a deep learning or neural learning system needs to be trained in object recognition and classification for it get smarter and more efficient at identifying basic objects, occluded objects, etc., while also assigning context to objects.

At the simplest level, neurons in the human brain look at various inputs that are received, importance levels are assigned to each of these inputs, and output is passed on to other neurons to act upon. An artificial neuron or perceptron is the most basic model of a neural network. In one example, a perceptron may receive one or more inputs that represent various features of an object that the perceptron is being trained to recognize and classify, and each of these features is assigned a certain weight based on the importance of that feature in defining the shape of an object.

A deep neural network (DNN) model includes multiple layers of many connected nodes (e.g., perceptrons, Boltzmann machines, radial basis functions, convolutional layers, etc.) that can be trained with enormous amounts of input data to quickly solve complex problems with high accuracy. In one example, a first layer of the DNN model breaks down an input image of an automobile into various sections and looks for basic patterns such as lines and angles. The second layer assembles the lines to look for higher level patterns such as wheels, windshields, and mirrors. The next layer identifies the type of vehicle, and the final few layers generate a label for the input image, identifying the model of a specific automobile brand.

Once the DNN is trained, the DNN can be deployed and used to identify and classify objects or patterns in a process known as inference. Examples of inference (the process through which a DNN extracts useful information from a given input) include identifying handwritten numbers on checks deposited into ATM machines, identifying images of friends in photos, delivering movie recommendations to over fifty million users, identifying and classifying different types of automobiles, pedestrians, and road hazards in driverless cars, or translating human speech in real-time.

During training, data flows through the DNN in a forward propagation phase until a prediction is produced that indicates a label corresponding to the input. If the neural network does not correctly label the input, then errors between the correct label and the predicted label are analyzed, and the weights are adjusted for each feature during a backward propagation phase until the DNN correctly labels the input and other inputs in a training dataset. Training complex neural networks requires massive amounts of parallel computing performance, including floating-point multiplications and additions that are supported by the PPU 300. Inferencing is less compute-intensive than training, being a latency-sensitive process where a trained neural network is applied to new inputs it has not seen before to classify images, translate speech, and generally infer new information.

Neural networks rely heavily on matrix math operations, and complex multi-layered networks require tremendous amounts of floating-point performance and bandwidth for both efficiency and speed. With thousands of processing cores, optimized for matrix math operations, and delivering tens to hundreds of TFLOPS of performance, the PPU 300 is a computing platform capable of delivering performance required for deep neural network-based artificial intelligence and machine learning applications.

Video Prediction Utilizing Spatially-Displaced Convolutions

Given a sequence of video frames I_1:t(x, y), which is a sample of the immediate past t video frames, a video prediction problem can be defined as the desire to predict the next future video frame I_t+1(x, y) in the sequence of video frames. The video prediction problem can be formulated as:

I_t+1(x,y)=((I_1:t(x,y)),I_1:t(x,y)),  (Eq. 1)

where is a learned function that predicts transformation parameters for the transformation function . In one embodiment, the function is learned by the video prediction system 200 to predict the set of parameters 222.

FIG. 6A illustrates a motion-vector based sampling approach 610 to the video prediction problem, in accordance with the prior art. One solution to the video prediction problem utilizes a bilinear sampling operation guided by a motion vector, which can be formulated as:

I_t+1(x,y)=f(I_t(x+u,y+v)),  (Eq. 2)

where f is a bilinear interpolator and <u, v> is the motion vector predicted by .

As depicted in FIG. 6A, a motion vector (u, v) 612 for a pixel p(x, y) is utilized to sample a pixel value from the previous frame I_t(x+u, y+v). The motion vector 612 can be selected from a backwards optical flow. In the example shown in FIG. 6A, the motion vector for this pixel is: (−3, 2). However, in cases where the pixel p(x, y) was occluded in the previous frame, the motion vector for that pixel in the backwards optical flow can be undefined or have a zero value. Alternatively, the motion vector can be a best match for the pixel, which is likely to sample a pixel value from an unrelated object. Consequently, the motion vector based approach 610 typically leads to poor approximations for the previously occluded pixels.

FIG. 6B illustrates a kernel based sampling approach 620 to pixel synthesis, in accordance with the prior art. Another solution to the video prediction problem combines motion or displacement learning and resampling into a single convolution operation, which can be formulated as:

I_t+1(x,y)=K(x,y)*P_t(x,y),  (Eq. 2)

where P_t(x, y) is a patch of pixels centered at the corresponding pixel p(x, y) in the previous frame and K(x, y) is a convolution kernel predicted by . In other words, rather than learning the displacement associated with the optical flow, as is done for the example shown in FIG. 6A, the convolution kernel coefficients can be learned such that any displacement can be accommodated within the patch overlapped by the convolution kernel.

As depicted in FIG. 6B, a convolution kernel 622 centered at pixel p(x, y) is utilized to sample a pixel value from the previous frame I_t(x, y). The convolution kernel 622 is shown as a 3×3 2D convolution kernel. However, given the same motion vector as the example depicted in FIG. 6A, it is clear that the 3×3 convolution kernel does not overlap with the corresponding pixel p(x−3, y+2) in the previous frame. Consequently, the sampled pixel value is likely to be incorrect for any pixels having a motion vector with magnitude larger than √{square root over (2)}=√{square root over ((Δx)²+(Δy)²)}. In order to overcome the problems with large displacements associated with large motion vectors, the size of the convolution kernel can be increased. For example, the size of the corresponding convolution kernel that would be required to include all relevant pixels surrounding the corresponding pixel p(x−3, y+2) to calculate the equivalent of a 3×3 convolution kernel displaced according to the motion vector (−3, 2) would necessitate a minimum convolution kernel size of 9×9. Furthermore, an accurate prediction of the convolution kernel coefficients for this 9×9 convolution kernel would require a small number of coefficients corresponding to the relevant pixels (e.g., 9 out of 81 non-zero coefficients). It will be appreciated that for any motion vectors of even modest size, an extremely large convolution kernel size is required to capture the relevant pixel data, and this large size quickly breaks the ability of the neural network utilized to predict the convolution kernels to be accurately trained or make accurate predictions.

FIG. 6C illustrates an SDC-based sampling approach 630 to pixel synthesis, in accordance with some embodiments. A novel approach to the video prediction problem combines the best aspects of the motion vector based sampling approach 610 and the kernel based sampling approach 620, which can be defined as:

I_t+1(x,y)=K(x,y)*P_t(x+u,y+v)  (Eq. 3)

Instead of increasing the size of the convolution kernel to cover a larger patch of pixels centered on the pixel p(x, y), the SDC-based sampling approach 630 uses smaller convolution operations that are displaced from the corresponding pixel p(x, y) based on a predicted displacement vector (u, v) 632 that centers the new convolution operation on pixel p(x+u, y+v) in the previous frame. The displacement vector 632 is not equivalent to the motion vector 612 predicted from the pure backwards optical flow because the pure backwards optical flow cannot accurately account for dis-occlusions. Instead, the displacement vector 632 corresponds to a prediction near the edge of objects proximate the occluded pixel in the previous video frame, estimated from the pure backwards optical flow as well as the sequence of image frames.

Using the predicted displacement vector 632, a much smaller convolution kernel 634 can be used to sample a pixel value from the previous frame than compared with the kernel based sampling approach 620 of FIG. 6B. For example, the predicted convolution kernel 634 can filter the pixels from the occluded object that are visible near the edge specified by the displacement vector using, e.g., a 3×3 convolution kernel having 9 learned coefficients compared to the required 9×9 convolution kernel of the kernel based sampling approach 620, a nine-fold decrease in learned coefficients. This approach can significantly speed up the video prediction algorithms that implement SDC-based sampling techniques.

It will be appreciated that the number of predicted coefficients in the convolution kernel 634 can be kept rather small. Even though the convolution kernel itself is small, as long as the predicted displacement vector 632 is accurate, then the predicted pixel value is likely to approximate the occluded pixel value where the pixel values in the neighborhood overlapped by the displaced convolution operation include pixels from the same object or objects. In real-world scenarios, this is typically true as long as the motion between frames is moderate and, where the motion is extreme, a viewer is not as likely to notice any artifacts caused by inaccurate predictions.

FIG. 7 illustrates an SDC-based sampling approach to pixel synthesis using one-dimensional (1D) convolution kernels, in accordance with some embodiments. The general SDC-based sampling approach 630 illustrated in FIG. 6C can accommodate error in the predicted displacement vector 632 by increasing the size of the 2D convolution kernels 634. However, by increasing the size of the convolution kernels, the same issues are encountered that exist with the simple kernel-based approach of FIG. 6B. More specifically, the complexity of the deep learning neural networks increases when predicting more coefficient values and the accuracy of those predictions decreases. Even with modest sized 2D convolution kernels, training can become difficult and the results produced by the neural network can be disappointing.

However, 2D convolution kernels can be approximated, in many instances, with two 1D convolution operations performed separately, where the results of the convolution operations are summed. For example, a 2D convolution kernel 634 can instead be separated into a 1×N 1D horizontal convolution kernel 710 and an N×1 1D vertical convolution kernel 720. Again, both the 1D convolution kernels are applied to a number of pixels centered at the pixel p(x+u, y+v) specified by the predicted displacement vector 702.

It will be appreciated that by reducing the 2D convolution operation to a pair of orthogonal 1D convolution operations centered on displaced pixel p(x+u, y+v), the number of parameters predicted by the deep learning neural network model can be reduced or, alternatively, the width and height of the patch of pixels around the displaced pixel can be dramatically increased. For example, in the case of a 2D convolution operation utilizing a 7×7 2D convolution kernel, the deep learning neural network model would need to predict 49 convolution coefficients. However, in the case of a pair of orthogonal 1D convolution operations, the width and height of the convolution operation can be approximately doubled (e.g., 1×13 and 13×1, respectively) while reducing the number of predicted convolution coefficients by nearly half (e.g., 26 vs. 49). This approach can allow for the use of extremely large 1D convolutions e.g., 1×31 and 31×1) where a similarly sized 2D convolution kernel (e.g., 31×31) would be impossible to predict by any deep learning neural network that could be implemented in a reasonable number of compute and memory resources.

In yet another embodiment, the two 1D predicted convolution kernels can be utilized to generate a separable 2D convolution kernel, which is an outer product of the two 1D convolution kernels. The SDC module 230 can be configured to receive the two 1D convolution kernels from the second neural network 220 and compute the coefficients for the separable 2D convolution kernel prior to sampling the pixel value from the previous video frame using the separable 2D convolution kernel. Alternately, the SDC module 230 can be configured to apply one of the 1D convolution kernels to each row or column of the patch of pixels and then multiply the intermediate result of said convolution operation by a corresponding coefficient of the other 1D convolution kernel. This type of operation is equivalent to calculating the separable 2D convolution coefficients prior to applying the 2D convolution operation but requires a fewer number of operations.

In one embodiment, the SDC module 230 can be optimized to speed up the processing of the convolution operations. It will be appreciated that, for most pixel positions, many of the predicted coefficients in the convolution kernel(s) will be zero or close to zero while a few coefficients in the kernel may be relatively large. This characteristic of the convolution kernels can be exploited to improve the execution speed by omitting the computations for zero-valued or small coefficients where the relative contribution for that coefficient would be lost in a limited precision result. In one embodiment, the SDC module 230 is configured to skip a calculation in the convolution operation for any coefficients below a threshold value. For example, where coefficients are in the range of [0,1], the SDC module 230 can be configured to skip a calculation if the coefficient of the convolution kernel is below 0.05. It will be appreciated that the threshold value can be adapted for different applications and that 0.05 is only provided as one example of a threshold value. In some embodiments, the threshold value can be calculated based on the predicted coefficients produced by the second neural network 220. For example, the SDC module 230 can sum the coefficients in the convolution kernels predicted for a frame and then calculate the threshold value based on the sum. However, it will be appreciated that the amount of time taken to calculate the threshold value, and the complexity of the function implemented for that purpose, can reduce the effectiveness of the optimization. Therefore, a pre-defined threshold value may be preferred to a threshold value adapted based on the output of the second neural network 220.

FIG. 8 illustrates a deep learning neural network architecture of the second neural network 220 of FIG. 2, in accordance with some embodiments. The second neural network 220 is a modified type of convolutional neural network (CNN), which can be referred to generally as a U-Net or a V-Net because of the structure and connections between each stage of the network. Like a conventional CNN, the second neural network 220 includes an encoder that applies a number of convolution operations to an input 802 to extract feature information. Each stage of the second neural network 220 includes one or more 3D convolution layers followed by an activation function and a down-sampling operation to reduce the spatial resolution of the input. In an embodiment, the down-sampling operation replaces a pooling layer in the conventional CNN. In one embodiment, the down-sampling operation comprises a convolution operation with a stride equal to 1×2×2 (e.g., the 3D convolution kernel is applied every other pixel rather than every pixel).

Once the encoder has extracted feature information from the input 802, a decoder up-samples the feature information and combines the feature information with spatial information forwarded to each stage via skip connections from a corresponding stage of the encoder. The output generally encodes the feature information with the same spatial resolution as the input 802.

In one embodiment, as depicted in FIG. 8, the second neural network 220 includes a first stage 810 that receives the input 802, which includes an image frame I_t and a backwards optical flow F_t, for two or more image frames in a sequence of image frames (e.g., I_1:t and F_2:t). In one embodiment, the input 802 comprises five channels per image frame: (1) a red channel; (2) a green channel; (3) a blue channel; (4) a u-component of the motion vector from the optical flow; and (5) a v-component of the motion vector. The input 802 for each frame is provided in 3 dimensions: x-coordinate and y-coordinate in pixel space and a t-coordinate to identify different frames in the sequence.

In one embodiment, the first stage 810 includes one or more convolution layers 812 that apply 3D convolution operations to the input 802. The result of the convolution operations is a number of feature maps that provide activations in the 3D space associated with the input 802. For example, where the input 802 comprises a sequence of image frames and corresponding backwards optical flows in 1080×1920 resolution (e.g., full high-definition video), then the convolution operations can generate a number of feature maps at the 1080×1920 resolution. The convolution layers 812 are followed by an activation function, not explicitly shown, such as a rectified linear unit (ReLU). In one embodiment, the convolution layer 812 in the encoder stage is followed by a Leaky ReLU. It will be appreciated that, in some embodiments, the activation function can be moved in front of each convolution operation or moved after each down-sampling operation.

The first stage 810 then includes a down-sampling layer 814 that applies a convolution operation with a stride to the output activations of the feature maps to down-sample the feature maps in the 3D space. In one embodiment, each convolution operation uses a stride of 1×2×2 such that the feature maps are reduced in spatial resolution by half in the x-dimension and the y-dimension in the pixel space of the image frame, while keeping the resolution of time fixed. The down-sampled output of the first stage 810 is then passed to the next stage, the second stage 820.

The second stage 820 is similar to the first stage 810 in that the input to the second stage 820 is processed by one or more convolution layers 822 followed by a down-sampling layer 824. Again, in one embodiment, the spatial resolution of the feature maps generated by the second stage 820 is halved in the horizontal and vertical pixel space. The encoder comprises a number of additional stages that continue to down-sample the feature maps at each successive stage until reaching a final stage 830 of the encoder, which includes one or more convolution layers 832 followed by a down-sampling layer 834 that generates feature maps at the lowest spatial resolution.

In one embodiment, the encoder section of the second neural network 220 includes at least six stages. For example, the first stage 810 receives an input 802 having three dimensions (x, y, t) in five channels (R, G, B, U, V), as described above. The convolution layers 812 generate a feature map comprising 32 channels in the three dimensions and the down-sampling layer 814 reduces the resolution of the feature maps to half the resolution in each dimension of the pixel space (e.g., 540×960 resolution by the number of frames in time t). The second stage 820 doubles the number of channels of the feature maps (e.g., 32 to 64) and halves the resolution in each dimension of the pixel space (e.g., 270×480). The third stage doubles the number of channels of the feature maps (e.g., 64 to 128) and halves the resolution in each dimension of the pixel space (e.g., 135×240). The fourth stage doubles the number of channels of the feature maps (e.g., 128 to 256) and halves the resolution in each dimension of the pixel space (e.g., 68×120). Note, zero padding can be utilized when the down-sampling operation would result in a loss of information due to an odd number of pixels in the input to the stage. The fifth stage maintains the number of channels of the feature maps (e.g., 256 to 256) and halves the resolution in each dimension of the pixel space (e.g., 34×60). Finally, the sixth stage 830 doubles the number of channels of the feature maps (e.g., 256 to 512) and halves the resolution in each dimension of the pixel space (e.g., 17×30).

It will be appreciated that each convolution layer in the encoder section of the second neural network 220 can implement a convolution operation using a convolution kernel of a different size. For example, in one embodiment, the convolution layer 812 of the first stage 810 implements convolution operations based on a 3×7×7 convolution kernel; the convolution layer 822 of the second stage 820 implements convolution operations based on a 3×5×5 convolution kernel; and the convolution layers of the other stages of the encoder implement convolution operations based on 3×3×3 convolution kernels. However, in other embodiments, different sized convolution kernels can be implemented at each stage of the encoder section of the second neural network 220. Furthermore, it will be appreciated that each of the 3D convolution operations of the encoder section generates activations based on information spanning multiple image frames and optical flows. In other words, the feature information generated by the encoder section incorporates the time dimension rather than extracting features from a single image frame/optical flow pair.

The encoder section of the second neural network 220 extracts the feature information from the spatial resolution of the input image frames and optical flows and encodes that information at low spatial resolution over a large number of channels. In one embodiment, the output of the encoder section is processed by a decoder section of the second neural network 220. Each stage of the decoder section includes a convolution layer and a deconvolution layer. Both the convolution layer and the deconvolution layer receive the output of the previous stage of the decoder section and concatenate that output with the output of a corresponding stage of the encoder section. The output of the convolution layer is followed by an up-sampling layer that preforms a transposed convolution operation on the feature map generated by the convolution layer.

In one embodiment, as depicted in FIG. 8, the first stage 840 of the decoder section includes a convolution layer 842 and a deconvolution layer 846. Because there is no previous stage of the decoder section at the first stage 840, the input of the convolution layer 842 and the deconvolution layer 846 merely comprises the feature map generated by the last stage 830 of the encoder section of the second neural network 220.

In one embodiment, the convolution layer 842 applies 3×3×3 convolution kernels using a 1×1×1 stride to the 512 channel feature map received from the encoder section. The convolution layer 842 compresses the number of channels in the input feature map (e.g., reducing the channels from 512 to 2). The feature map also matches the spatial resolution of the input (e.g., 17×30).

Following the convolution layer 842, an up-sampling layer 844 increases the spatial resolution of the feature map by performing a transposed convolution operation. In one embodiment, the up-sampling layer 844 applies a 1×4×4 transposed convolution kernel using a 1×2×2 stride to double the spatial resolution of the feature map in each dimension of the pixel space while keeping the number of channels fixed (e.g., 2 channels). For example, the spatial resolution is doubled (e.g., 34×60) and the number of channels remains at 2.

In parallel with the convolution layer 842 and the up-sampling layer 844, a deconvolution layer 846 increases the spatial resolution of the input feature map received by the stage by performing a transposed convolution operation. In one embodiment, the deconvolution layer 846 applies a 1×4×4 transposed convolution kernel using a 1×2×2 stride to double the spatial resolution of the feature map while reducing the number of channels in the feature map.

The output of the up-sampling layer 844 is concatenated to the output of the deconvolution layer 846 and transmitted to the next stage of the decoder section of the second neural network 220. Each stage of the decoder section receives the concatenated output of the previous stage of the decoder section, which is also concatenated with the output forwarded to the decoder stage from a corresponding stage of the encoder section. Each stage of the decoder section doubles the spatial resolution of the feature maps to match the spatial resolution of the feature maps processed by the next decoder stage. It will be appreciate that the number of channels in the feature map from the previous stage in the decoder section does not have to match the number of channels in the feature map from the corresponding stage of the encoder section.

In one embodiment, the second neural network includes six stages in the decoder section, doubling the spatial resolution of the feature map at each stage in the decoder section. For example, the first stage 840 of the decoder section increases the spatial resolution from 17×30 to 34×60; the second stage of the decoder section increases the spatial resolution from 34×60 to 68×120; the third stage of the decoder section increases the spatial resolution from 68×120 to 135×240; the fourth stage of the decoder section increases the spatial resolution from 135×240 to 270×480; the fifth stage 850 of the decoder section increases the spatial resolution from 270×480 to 540×960; and the sixth stage 860 of the decoder section increases the spatial resolution from 540×960 to the full high-definition resolution of 1080×1920.

The operation of the convolution layer 852, the up-sampling layer 854, and the deconvolution layer 856 as well as the convolution layer 862, the up-sampling layer 864, and the deconvolution layer 866 of stage 850 and stage 860, respectively, operate similarly to the like layers of the first stage 840 of the decoder section with the exception that the input to the stage includes both the forwarded output of the corresponding stage of the encoder section and the output of the previous stage of the decoder section.

It will be appreciated that each stage of the decoder section effectively extracts features from the input to the stage, up-samples the features and then mixes the features with the spatial information forwarded from the encoder stage to match the features more closely with the spatial information.

Although not shown explicitly in FIG. 8, in one embodiment, the output 804 of the last stage of the decoder section is processed by a post-processing stage to generate the per-pixel parameters 222 that define the displacement vectors for the pixels of the predicted frame 232. In one embodiment, the post-processing stage includes a first convolution layer that applies a 3×3×3 convolution kernel using a 1×1×1 stride to the 13 channel input. The output of the first convolution layer is provided as the input to a second convolution layer that applies a 2×3×3 convolution kernel using a 2×1×1 stride (e.g., compressing the time domain from 5 frames to 3 frames, for example), which is provided as an input to a third convolution layer that applies a 2×3×3 convolution kernel using a 2×1×1 stride. The result provides two channels of the output, given the u-coordinate and the v-coordinate for the displacement vector corresponding to each pixel of the predicted image frame I_t+1(x, y).

In addition, in one embodiment, the input of the last stage 860 of the decoder section is processed by a pair of additional post-processing stages to generate the per-pixel parameters for the 1D convolution kernels, K_u(x, y) and K_v(x, y). In one embodiment, each of the additional post processing stages include: a first convolution layer that applies a 3×3×3 convolution kernel using a 1×1×1 stride to the input; a second deconvolution layer that applies a 1×4×4 transposed convolution kernel using a 1×2×2 stride to the output of the first convolution layer; a third convolution layer that applies a 2×3×3 convolution kernel using a 1×1×1 stride to the output of the second transposed convolution layer, thereby reducing the number of channels to equal the size of the 1D convolution filters; a fourth convolution layer that applies a 1×3×3 convolution kernel using a 1×1×1 stride to the output of the third convolution layer; and a fifth convolution layer that applies a 1×3×3 convolution kernel using a 1×1×1 stride to the output of the fourth convolution layer.

The output of the pair of additional post-processing stages is a multi-channel feature map, where each channel encodes a particular coefficient of the 1D convolution filter for each pixel of the predicted image frame I_t+1(x, y).

It will be appreciated that the exact structure, such as the size of the convolution kernels, the stride, the number of stages in each of the encoder and decoder sections, and the like are provided for illustration of one exemplary embodiment of the second neural network 220. In other embodiments, the second neural network 220 can depart from the exemplary structure described above, such as by implementing a different number of stages, making the down-sampling and up-sampling more aggressive, increasing or decreasing the size of the 1D convolution filters, generating a 2D convolution filter instead of two separable 1D convolution filters, and so forth.

FIG. 9 illustrates a flowchart of a method for training the second neural network 220 of FIG. 2, in accordance with some embodiments. The results that are achieved by the second neural network 220 are dependent, to a certain extent, on the ability to effectively train the model to produce the correct set of parameters 222 for the SDC-based sampling approach 630. In one embodiment, the training primary relies on the computation of the L1 loss over the predicted image given by:

₁=∥I_t+1−I_t+1^g∥,  (Eq. 4)

where I_i^g is the ground-truth target and I_i is the predicted frame generated by the SDC module 230. Training based on ₁ has been found to typically be better at capturing small changes than training based on ₂, and will generally produce sharper images. However, it will be appreciated that the effectiveness of the training can require a good set of training data, such as 100s of thousands of ground-truth video frames and corresponding preceding sequences of video frames. In one embodiment, the training data set can be collected from, e.g., computer-generated (synthetic) sequences captured during video game play. Alternatively, the training data set can include sequences of video frames captured from live video feeds such as cable networks.

In one embodiment, the loss function in Equation 4 can be fine-tuned for the various feature representations of the second neural network. More specifically, a fine-tuned loss function can be defined as a weighted sum of an ₁ loss component, a perceptual loss component, and a style loss component. The perceptual loss component can be given by:

_perceptual=Σ_l=1^Lκ_l∥ψ_l(I_t+1)−ψ_l((I_t+1^g)∥,  (Eq. 5)

where ψ_l(I_i) is the feature map from the l^th selected layer of the pre-trained second neural network 220, L is the number of layers, and κ_l is a normalization factor of 1/C_lH_lW_l (channel, height, width) for the l^th selected layer. The style loss component can be given by:

_styleΣ_l=1^Lκ_l∥ψ_l(I_t+1)^Tψ_l(I_t+1)−ψ_l(I_t+1^g)^T)ψ_l(I_t+1^g)∥   (Eq. 6)

The fine-tuned loss function comprising a weighted sum of the three components set forth above is given by:

_fine=ω₁₁+ω_sstyle+ω_pperceptual  (Eq. 7)

In one embodiment, training the second neural network 220 can include an initialization step. During initialization, the parameters of the second neural network 220 can be adjusted based on an initialization loss function _kernel given by:

$\begin{array}{cc}{ℒ}_{\mathrm{kernel}}={\sum }_{x=1}^W{\sum }_{y=1}^H\left({K_u\left(x,y\right)-1^{〈\frac{N}{2}〉}}^2+{K_v\left(x,y\right)-1^{〈\frac{N}{2}〉}}^2\right),& \left(\mathrm{Eq}.8\right)\end{array}$

The initialization loss function _kernel is based on the ₂ norm difference between the adaptive 1D convolution kernels K_u(x, y) and K_v(x, y) and a one-hot kernel

$1^{〈\frac{N}{2}〉}$

of similar size where most of the coefficients of the one-hot kernel are zero or close to zero and the middle coefficient is set to one or close to one. The one-hot kernel, as applied by the SDC-based sampling approach 630, would very closely approximate the motion vector based sampling approach 610. After a small subset of training data set is used to initialize the attributes (e.g., weights and/or biases) of the second neural network 220 based on the initialization loss function _kernel of Equation 8, the remainder of the training data set is used to fine tune the attributes based on the fine-tuned loss function of Equation 7. Using this type of initialization step to initialize the attributes of the second neural network 220 can significantly speed up the training time.

Returning to the method 900 of FIG. 9, at step 902, a set of training data is received. In one embodiment, the training data includes a large number of 1080p video frames collected from computer-generated video games. Each training sample in the training set includes 5 consecutive video frames in a sequence I_1:5 and a corresponding 6^th video frame as the ground-truth video frame I₆^g. In one embodiment, the sequence of frames and the ground-truth frame are randomly cropped to 256×256 resolution. At step 904, the attributes for the second neural network 220 are randomly initialized.

At step 906, the second neural network 220 is trained, during a coarse training period, to learn the displacement vectors <u, v> based on an ₁ loss function. Optimizing for the displacement vectors alone during the coarse training period helps to allow the second neural network 220 to capture large and coarse motions. Using a batch size of 128 training samples and implemented using batch training techniques on a small number of PPUs 300 (e.g., 8 PPUs), step 906 can take a few hundred epochs to converge.

At step 908, the second neural network 220 is trained, during an initialization period, to learn the adaptive 1D convolution kernels based on the initialization loss function _kernel. In one embodiment, all of the attributes of the second neural network 220 are fixed during this initialization period except for the attributes for the pair of additional post-processing stages that generate the per-pixel parameters for the 1D convolution kernels, K_u(x, y) and K_v(x, y). Because the initialization loss function during this step is based on an ₂ loss function, only a small number of epochs is required in the initialization period.

At step 910, the second neural network 220 is trained, during a joint training period, to jointly tune the displacement vectors <u, v> and the adaptive 1D convolution kernels K_u(x, y) and K_v(x, y) based on an ₁ loss function. Using a batch size of 128 training samples and implemented using batch training techniques on a small number of PPUs 300 (e.g., 8 PPUs), step 910 can take a few hundred epochs to converge.

Finally, at step 912, the second neural network 220 is trained, during a fine-tuning training period, to jointly tune the displacement vectors <u, v> and the adaptive 1D convolution kernels K_u(x, y) and K_v(x, y) based on an _fine loss function. The fine-tuning training period utilizes perceptual loss and stylized loss components to adjust the attributes of the second neural network 220.

It is noted that the techniques described herein may be embodied in executable instructions stored in a computer readable medium for use by or in connection with a processor-based instruction execution machine, system, apparatus, or device. It will be appreciated by those skilled in the art that, for some embodiments, various types of computer-readable media can be included for storing data. As used herein, a “computer-readable medium” includes one or more of any suitable media for storing the executable instructions of a computer program such that the instruction execution machine, system, apparatus, or device may read (or fetch) the instructions from the computer-readable medium and execute the instructions for carrying out the described embodiments. Suitable storage formats include one or more of an electronic, magnetic, optical, and electromagnetic format. A non-exhaustive list of conventional exemplary computer-readable medium includes: a portable computer diskette; a random-access memory (RAM); a read-only memory (ROM); an erasable programmable read only memory (EPROM); a flash memory device; and optical storage devices, including a portable compact disc (CD), a portable digital video disc (DVD), and the like.

It should be understood that the arrangement of components illustrated in the attached Figures are for illustrative purposes and that other arrangements are possible. For example, one or more of the elements described herein may be realized, in whole or in part, as an electronic hardware component. Other elements may be implemented in software, hardware, or a combination of software and hardware. Moreover, some or all of these other elements may be combined, some may be omitted altogether, and additional components may be added while still achieving the functionality described herein. Thus, the subject matter described herein may be embodied in many different variations, and all such variations are contemplated to be within the scope of the claims.

To facilitate an understanding of the subject matter described herein, many aspects are described in terms of sequences of actions. It will be recognized by those skilled in the art that the various actions may be performed by specialized circuits or circuitry, by program instructions being executed by one or more processors, or by a combination of both. The description herein of any sequence of actions is not intended to imply that the specific order described for performing that sequence must be followed. All methods described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context.

The use of the terms “a” and “an” and “the” and similar references in the context of describing the subject matter (particularly in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The use of the term “at least one” followed by a list of one or more items (for example, “at least one of A and B”) is to be construed to mean one item selected from the listed items (A or B) or any combination of two or more of the listed items (A and B), unless otherwise indicated herein or clearly contradicted by context. Furthermore, the foregoing description is for the purpose of illustration only, and not for the purpose of limitation, as the scope of protection sought is defined by the claims as set forth hereinafter together with any equivalents thereof. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illustrate the subject matter and does not pose a limitation on the scope of the subject matter unless otherwise claimed. The use of the term “based on” and other like phrases indicating a condition for bringing about a result, both in the claims and in the written description, is not intended to foreclose any other conditions that bring about that result. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention as claimed.

Claims

1. A computer-implemented method for generating a predicted video frame in a sequence of video frames, the method comprising:

receiving an input that includes the sequence of video frames and at least one optical flow, wherein each optical flow maps pixels from a particular video frame to motion vectors that identify corresponding pixels in a corresponding video frame in the sequence of video frames;

processing the input by layers of a first neural network to generate a set of parameters that include a displacement vector and at least one convolution kernel for each pixel of a plurality of pixels in the predicted video frame; and

generating the predicted video frame based on the set of parameters.

2. The method of claim 1, wherein generating the predicted video frame comprises, for each pixel of the plurality of pixels in the predicted video frame:

identifying a patch of pixels in a previous video frame in the sequence of video frames based on the displacement vector for the pixel; and

applying a convolution operation to the patch of pixels utilizing the at least one convolution kernel.

3. The method of claim 2, wherein the at least one convolution kernel includes a two-dimensional convolution kernel.

4. The method of claim 2, wherein the at least one convolution kernel includes a first one-dimensional convolution kernel associated with a horizontal dimension and a second one-dimensional convolution kernel associated with a vertical dimension.

5. The method of claim 4, wherein the convolution operation includes generating a two-dimensional convolution kernel based on the first one-dimensional convolution kernel and the second one-dimensional convolution kernel.

6. The method of claim 1, further comprising:

receiving the sequence of video frames; and

processing the sequence of video frames by layers of a second neural network to generate the at least one optical flow.

7. The method of claim 1, wherein the first neural network includes an encoder section that includes a plurality of stages and a decoder section that includes a plurality of stages, and wherein each stage in the plurality of stages of the encoder section includes one or more convolution layers and a down-sampling layer and each stage in the plurality of stages of the decoder section includes a convolution layer and an up-sampling layer.

8. The method of claim 7, wherein each stage in the plurality of stages of the decoder section also includes a deconvolution layer, and wherein an output of each stage in the plurality of stages of the decoder section concatenates a feature map generated by the up-sampling layer to a feature map generated by the deconvolution layer.

9. The method of claim 8, wherein an input of each stage in the plurality of stages of the decoder section concatenates a feature map generated by the down-sampling layer of a corresponding stage of the encoder section to the output of a previous stage of the decoder section.

10. The method of claim 1, wherein the first neural network is trained, at least in part, based on a loss function that includes a perceptual loss component and a style loss component.

11. A system, comprising:

a memory storing a sequence of video frames and at least one optical flow, each optical flow in the at least one optical flow corresponding to a pair of video frames in the sequence of video frames;

at least one parallel processing unit coupled to the memory and configured to implement, at least in part: a first neural network configured to process the sequence of video frames and the at least one optical flow to generate a set of parameters that include a displacement vector and at least one convolution kernel for each pixel of a plurality of pixels in a predicted video frame, and a spatially-displaced convolution (SDC) module configured to generate the predicted video frame based on the set of parameters.

12. The system of claim 11, wherein the SDC module is configured to, for each pixel of the plurality of pixels in the predicted video frame:

identify a patch of pixels in a previous video frame in the sequence of video frames based on the displacement vector for the pixel; and

apply a convolution operation to the patch of pixels utilizing the at least one convolution kernel.

13. The system of claim 12, wherein the at least one convolution kernel includes a two-dimensional convolution kernel.

14. The system of claim 12, wherein the at least one convolution kernel includes a first one-dimensional convolution kernel associated with a horizontal dimension and a second one-dimensional convolution kernel associated with a vertical dimension.

15. The system of claim 11, wherein the at least one parallel processing unit is further configured to implement, at least in part:

a second neural network configured to process the sequence of video frames to generate the at least one optical flow.

16. The system of claim 15, wherein the at least one parallel processing unit includes a first parallel processing unit configured to implement the first neural network and a second parallel processing unit configured to implement the second neural network.

17. The system of claim 11, wherein the at least one parallel processing unit includes a first parallel processing unit coupled to a second parallel processing unit via a high-speed interconnect.

18. The system of claim 11, wherein the first neural network includes an encoder section that includes a plurality of stages and a decoder section that includes a plurality of stages, and wherein each stage in the plurality of stages of the encoder section includes one or more convolution layers and a down-sampling layer and each stage in the plurality of stages of the decoder section includes a convolution layer and an up-sampling layer.

19. A non-transitory computer-readable media storing computer instructions for performing video prediction that, when executed by one or more processors, cause the one or more processors to perform the steps of:

receiving an input that includes the sequence of video frames and at least one optical flow, wherein each optical flow maps pixels from a particular video frame to motion vectors that identify corresponding pixels in a corresponding video frame in the sequence of video frames;

processing the input by layers of a first neural network to generate a set of parameters that include a displacement vector and at least one convolution kernel for each pixel of a plurality of pixels in the predicted video frame; and

generating the predicted video frame based on the set of parameters.

20. The computer-readable media of claim 19, wherein generating the predicted video frame comprises, for each pixel of the plurality of pixels in the predicted video frame:

identifying a patch of pixels in a previous video frame in the sequence of video frames based on the displacement vector for the pixel; and

applying a convolution operation to the patch of pixels utilizing the at least one convolution kernel.