VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES WITH REDUCED TOP SOURCE/DRAIN VARIABILITY AND LOWER RESISTANCE
A method of forming a fin field effect device is provided. The method includes forming one or more vertical fins on a substrate and a fin template on each of the vertical fins. The method further includes forming a gate structure on at least one of the vertical fins, and a top spacer layer on the at least one gate structure, wherein at least an upper portion of the at least one of the one or more vertical fins is exposed above the top spacer layer. The method further includes forming a top source/drain layer on the top spacer layer and the exposed upper portion of the at least one vertical fin. The method further includes forming a sacrificial spacer on opposite sides of the fin templates and the top spacer layer, and removing a portion of the top source/drain layer not covered by the sacrificial spacer to form a top source/drain electrically connected to the vertical fins.
The present invention generally relates to vertical fin field effect devices, and more particularly to vertical fin field effect device fabrication.
Description of the Related ArtA Field Effect Transistor (FET) typically has a source, a channel, and a drain, where current flows from the source to the drain, and a gate that controls the flow of current through the device channel. Field Effect Transistors (FETs) can have a variety of different structures, for example, FETs have been fabricated with the source, channel, and drain formed in the substrate material itself, where the current flows horizontally (i.e., in the plane of the substrate), and FinFETs have been formed with the channel extending outward from the substrate, but where the current also flows horizontally from a source to a drain. The channel for the FinFET can be an upright slab of thin rectangular silicon (Si), commonly referred to as the fin with a gate on the fin, as compared to a MOSFET with a single gate parallel with the plane of the substrate. Depending on the doping of the source and drain, an n-FET or a p-FET can be formed. Two FETs also can be coupled to form a complementary metal oxide semiconductor (CMOS) device, where a p-channel MOSFET and n-channel MOSFET are electrically coupled together.
SUMMARYIn accordance with an embodiment of the present invention, a method of forming a fin field effect device is provided. The method includes forming one or more vertical fins on a substrate and a fin template on each of the one or more vertical fins. The method further includes forming a gate structure on at least one of the one or more vertical fins. The method further includes forming a top spacer layer on the at least one gate structure, wherein at least an upper portion of the at least one of the one or more vertical fins is exposed above the top spacer layer. The method further includes forming a top source/drain layer on the top spacer layer and the exposed upper portion of the at least one of the one or more vertical fins. The method further includes forming a sacrificial spacer on opposite sides of the at least one of the one or more fin templates and the top spacer layer, and removing a portion of the top source/drain layer not covered by the sacrificial spacer to form a top source/drain electrically connected to the at least one of the one or more vertical fins.
In accordance with another embodiment of the present invention, a method of forming a fin field effect device is provided. The method includes forming a bottom source/drain layer on a substrate, and forming one or more vertical fins on the bottom source/drain layer and a fin template on each of the one or more vertical fins. The method further includes forming a bottom spacer layer on the bottom source/drain layer. The method further includes forming a gate structure on the bottom spacer layer and at least one of the one or more vertical fins. The method further includes forming a top spacer layer on the at least one gate structure, wherein at least an upper portion of the at least one of the one or more vertical fins is exposed above the top spacer layer. The method further includes forming a top source/drain layer on the top spacer layer and the exposed upper portion of the at least one of the one or more vertical fins. The method further includes forming a sacrificial spacer on opposite sides of the at least one of the one or more fin templates and the top spacer layer, and removing a portion of the top source/drain layer not covered by the sacrificial spacer to form a top source/drain electrically connected to the at least one of the one or more vertical fins.
In accordance with yet another embodiment of the present invention, a vertical fin field effect transistor device is provided. The vertical fin field effect transistor device includes one or more vertical fins on a substrate. The vertical fin field effect transistor device further includes a top source/drain electrically connected to at least one of the one or more vertical fins, and a conductive fill that wraps around the sidewalls of the top source/drain.
These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The following description will provide details of preferred embodiments with reference to the following figures wherein:
Embodiments of the present invention provide uniform top source/drains on vertical fins that can have non-uniform top portions. Epitaxial growth of top source/drains on non-uniform top portions of a vertical fin can be difficult due to different growth planes being simultaneously exposed at the top of the vertical fin. The top portion of a vertical fin may not have well defined and consistent surface planes, but a narrow, convex surface on which epitaxial or heteroepitaxial growth can be difficult and inconsistent over multiple fins. The curved surfaces can have numerous exposed crystal planes without a dominant growth plane.
Embodiments of the present invention provide a fabrication process that avoids inconsistent fabrication results by forming top source/drains on one or more sidewalls of the vertical fins, where the sidewalls have more consistent sizes and predetermined exposed crystal planes. Lateral epitaxial growth on the sidewalls of the vertical fins can allow controlled formation of the top source/drain with intended sizes and crystal alignment from a dominant crystal plane. The epitaxial growth on the dominant crystal planes of the exposed sidewalls can provide consistent symmetrical top source/drain formation. The fabrication process from the sidewalls of the vertical fins can avoid poorly formed and asymmetrical top source/drains that would otherwise be formed from the narrow and curved top surfaces of the vertical fins.
Embodiments of the present invention provide multiple vertical fin devices with uniform top source/drains that can provide more consistent device properties and performance. Use of self-aligned spacers with controlled thicknesses can provide uniform and symmetrical top source/drains for vertical fin field effect transistor (VFinFET) devices.
Exemplary applications/uses to which the present invention can be applied include, but are not limited to: logic devices (e.g., NAND gate circuits, NOR gate circuits, inverters, etc.) and memory devices (e.g., static random access memory (SRAM), dynamic access memory (DRAM).
It is to be understood that aspects of the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps can be varied within the scope of aspects of the present invention.
Referring now to the drawings in which like numerals represent the same or similar elements and initially to
In one or more embodiments, one or more vertical fins 130 can be formed on a substrate 110. The vertical fins 130 can be formed by a multiple patterning fabrication process, for example, a sidewall image transfer (SIT) process, a self-aligned double patterning (SADP) process, self-aligned triple patterning (SATP) process, or a self-aligned quadruple patterning (SAQP). The vertical fins 130 may be formed by a direct write process or double patterning process using, for example, immersion lithography, extreme ultraviolet lithography, or x-ray lithography.
In one or more embodiments, a bottom source/drain layer 120 can be formed on the substrate 110, where the bottom source/drain layer 120 can be formed by an epitaxial or heteroepitaxial growth process. The bottom source/drain layer 120 can be doped to be an n-type bottom source/drain layer or a p-type bottom source/drain layer. In various embodiments, the bottom source/drain layer 120 can be a semiconductor material, including, but not limited to n-type (e.g., P or As) doped silicon (Si) or p-type (e.g., B) doped silicon-germanium (SiGe). The bottom source/drain layer 120 can be the same semiconductor material as the substrate 110. The vertical fins 130 can be formed from a semiconductor layer formed on the bottom source/drain layer 120, for example, by an epitaxial or heteroepitaxial growth process.
In various embodiments, a fin template 140 can be formed on each of the vertical fins 130 as part of the patterning process, where the fin templates 140 can be a hardmask material, including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon borocarbide (SiBC), silicon boro carbonitride (SiBCN), or combinations thereof. In various embodiments, a fin cap 150 can be formed on each of the fin templates 140, where the fin caps 150 can also be formed as part of the patterning process. The fin cap(s) 150 can be a hardmask material, including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon borocarbide (SiBC), silicon boro carbonitride (SiBCN), or combinations thereof, that is different from the material of the fin template(s) 140.
The fin templates 140 can be formed from a fin template layer formed on the semiconductor layer, and the fin caps 150 can be formed from a fin cap layer formed on the fin template layer, where the fin templates and fin caps can be formed by the patterning process.
In one or more embodiments, vertical fins 130 can be laterally adjacent to each other (i.e., in a row). The facing sidewalls of adjacent vertical fins 130 can be separated by a distance in a range of about 10 nm to about 50 nm, or in a range of about 20 nm to about 40 nm, although other distances are also contemplated. In various embodiments, the exposed sidewalls of the vertical fins can be {100} crystal planes.
In various embodiments, the widths of the semiconductor vertical fin(s) 130 can be in a range of about 5 nanometers (nm) to about 15 nm, or about 6 nm to about 10 nm, or about 6 nm to about 8 nm, although other widths are also contemplated.
In various embodiments, the height of the semiconductor vertical fin(s) 130 can be in a range of about 20 nanometers (nm) to about 100 nm, or about 30 nm to about 50 nm, although other heights are also contemplated. Although the vertical fins 111 are depicted in the figures perpendicular to the substrate 110 (i.e., having a 90 degree angle), the fins can have a tapered sidewall that does not meet the substrate at a right angle (i.e., not exactly 90 degree). The top surface of the vertical fins 130 may not be perfectly flat or rectangular, but may have a convex curved surface. The substrate surface can have a curved (recessed) profile between the vertical fins 130.
In one or more embodiments, a substrate 110 can be, for example, a single crystal semiconductor material wafer or a semiconductor-on-insulator stacked wafer. The substrate can include a support layer that provides structural support, and an active semiconductor layer that can form devices. An insulating layer (e.g., a buried oxide (BOX) layer) may be between the active semiconductor layer and the support layer to form a semiconductor-on-insulator substrate (SeOI) (e.g., a silicon-on-insulator substrate (SOI)).
In one or more embodiments, the substrate 110 or an active semiconductor layer can be a crystalline semiconductor, for example, a IV or IV-IV semiconductor (e.g., silicon (Si), silicon carbide (SiC), silicon-germanium (SiGe), germanium (Ge)) or a III-V semiconductor (e.g., gallium-arsenide (GaAs), indium-phosphide (InP), indium-antimonide (InSb)).
In one or more embodiments, a bottom spacer layer 160 can be formed on the bottom source/drain layer 120, where the bottom spacer layer can be formed by a directional deposition, for example, a high density plasma (HDP) or gas cluster ion beam (GCIB), or by a blanker deposition, for example, chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD) and etched back to an intended thickness.
In various embodiments, the bottom spacer layer 160 can have a thickness in a range of about 3 nm to about 10 nm, or about 5 nm to about 7 nm, although other thicknesses are also contemplated.
In various embodiments, the bottom spacer layer 160 can be a dielectric material, including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon borocarbide (SiBC), silicon boro carbonitride (SiBCN), or combinations thereof. The bottom spacer layer 160 can be a material different from the in templates 140 and/or the fin caps 150 to allow selective removal.
In one or more embodiments, a gate structure can be formed on the bottom spacer layer 160, where the gate structure can include a gate dielectric layer 170 and a gate electrode 180, the gate electrode can include a work function layer on the gate dielectric layer 180 and a conductive gate fill on the work function layer. The work function layer can be formed by a conformal deposition, for example, atomic layer deposition (ALD) or plasma enhanced ALD (PEALD), on the gate dielectric layer 170. The work function layer can be a conducting metallic nitride or carbide compound material, for example, tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), and combinations thereof.
The conductive gate fill can be formed by a blanket deposition. In various embodiments, the conductive gate fill can be a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au), a conducting metallic compound material (e.g., tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide (CoSi), nickel silicide (NiSi)), transition metal aluminides (e.g. Ti3Al, ZrAl), TaC, TaMgC, or any suitable combination of these materials.
In one or more embodiments, a top spacer layer 190 can be formed on the gate dielectric layer 170 and a gate electrode 180, where the top spacer layer 190 can be formed by a directional deposition, (e.g., HDP or GCIB), or a conformal deposition (e.g., ALD, PEALD). An etch-back can be used to remove excess deposited materials on the sidewalls of the vertical fins 130. In various embodiments, an upper portion of the vertical fin(s) 130 can extend above the top surface of the top spacer layer 190 by a predetermined height. In various embodiments, the upper portion of the vertical fin(s) 130 can extend above the top surface of the top spacer layer 190 by a height in the range of about 10 nm to about 50 nm, or about 20 nm to about 30 nm, although other heights are also contemplated. The fin template 140 and fin cap 150 can be exposed above the top spacer layer 190. The height of the upper portion of the vertical fin(s) 130 exposed above the top spacer layer can be sufficient to provide a uniform crystal face for the epitaxial growth of a top source/drain layer.
In various embodiments, the top spacer layer 190 can have a thickness in a range of about 3 nm to about 10 nm, or about 5 nm to about 7 nm, although other thicknesses are also contemplated.
In one or more embodiments, a top source/drain layer 200 can be formed on the top spacer layer 190, where the top source/drain layer 200 can be formed by an epitaxial or heteroepitaxial growth process. The top source/drain layer 200 can be formed by a lateral epitaxial or heteroepitaxial growth process from the exposed sidewalls of the vertical fin(s) 130. In various embodiments, the vertical fins 130 can have sidewalls with an exposed {100} crystal plane for lateral growth of the top source/drain layer 200.
In one or more embodiments, the top source/drain layer 200 can have a thickness in a range of about 10 nm to about 60 nm, or about 20 nm to about 40 nm, although other thicknesses are also contemplated. The thickness of the top source/drain layer 200 can be greater than the height of the exposed sidewalls of the vertical fin(s) 130, such that the top source/drain layer 200 can cover a lower portion of a fin template 140 on the underlying vertical fin.
In various embodiments, the top source/drain layer 200 can be doped in situ (i.e., during epitaxial growth) or ex situ (i.e., after formation of the top source/drain layer) or both. The top source/drain layer 200 can be doped using, for example, ion implantation, plasma doping, gas phase doping, solid phase doping, and/or liquid phase doping.
In various embodiments, the bottom source/drain layer 120 can have a dopant concentration in the range of about 1×1020/cm3 to about 3×1021/cm3, or about 5×1020/cm3 to about 1×1021/cm3, although other concentrations are contemplated.
In one or more embodiments, the top source/drain layer 200, bottom source/drain layer 120, and vertical fin(s) 130 can be heat treated to diffuse dopants from the top source/drain layer 200 and bottom source/drain layer 120 into the adjacent regions of the vertical fin(s) to form a top extension region 137 and a bottom extension region 133. In various embodiments, the top extension region 137 and a bottom extension region 133 can have a dopant concentration in a range of about 1×1019/cm3 to about 3×1021/cm3, or about 5×1020/cm3 to about 3×1021/cm3, where the extension regions can be about 1×1019/cm3 at the device channel and about 5×1020/cm3 to about 3×1021/cm3 at the interface with the top source/drain layer 200 and bottom source/drain layer 120.
In various embodiments, the heat treatment can be conducted at a temperature in the range of about 800° C. to about 1300° C., or about 950° C. to about 1050° C. The heat treatment can be conducted for a duration in a range of about 30 milliseconds (msec) to about 30 seconds (sec). The heat treatment can be laser annealing, flash annealing, rapid thermal annealing (RTA), furnace annealing, or any suitable combination thereof. The thickness of the top spacer layer 190 and bottom spacer layer 160 can be the same, so dopants would diffuse the same distances to control the lengths of the top and bottom extension regions. The top extension region 137 can extend below the bottom surface of the top spacer layer 190 and the bottom extension region 133 can extend above the top surface of the bottom spacer layer 160, such that the top and bottom extension regions overlap with the gate structure.
In one or more embodiments, a sacrificial layer 210 can be formed on exposed surfaces of the top source/drain layer 200, fin templates 140, and fin caps 150, where the sacrificial layer 210 can be formed by a conformal deposition (e.g., ALD, PEALD, low pressure chemical vapor deposition (LPCVD), or a combination thereof).
In one or more embodiments, the sacrificial layer 210 can have a thickness in a range of about 3 nm to about 12 nm, or about 5 nm to about 10 nm, although other thicknesses are also contemplated. The thickness of the sacrificial layer 210 on the sidewalls of the fin templates 140 can determine the width of sacrificial spacers subsequently formed on the top source/drain layer 200.
In one or more embodiments, the sacrificial layer 210 can be made of a dielectric material, including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon borocarbide (SiBC), silicon boro carbonitride (SiBCN), or combinations thereof. In a non-limiting exemplary embodiment, the sacrificial layer 210 can be silicon boro carbonitride (SiBCN) or stoichiometric silicon nitride (Si3N4), where the sacrificial layer 210 can be the same material as the fin templates 140 to allow the fin templates 140 and subsequently formed sacrificial spacers to be removed at the same time.
In one or more embodiments, a portion of the sacrificial layer 210 can be removed to form sacrificial spacers 215 on the top source/drain layer 200, where the portion of the sacrificial layer 210 can be removed using a directional etch, for example, a reactive ion etch (RIE). The portion of the sacrificial layer 210 on the top source/drain layer 200 can be etched back to leave sacrificial spacers 215 on the sidewalls of the fin templates 140. The fin caps 150 can also be removed as part of the etch-back process to expose the top surface of the fin templates 140. In various embodiments, the sacrificial spacers 215 can have the same width as the thickness of the sacrificial layer 210. The width of the sacrificial spacers 215 can be about the same as the width of the vertical fins and fin templates 140.
In one or more embodiments, a portion of the top source/drain layer 200 exposed by forming the sacrificial spacers 215 can be removed to expose the underlying top spacer layer 190. The portion of the top source/drain layer 200 can be removed using a directional etch (e.g., RIE), where the sacrificial spacers 215 can mask the underlying portion of the top source/drain layer 200. Removal of the exposed portion of the top source/drain layer 200 can form top source/drains 205 on upper portions of the vertical fin(s) 130 and lower portions of the fin templates 140. The top source/drains 205 can be adjoining and in electrical contact with the top extension region 137 of the vertical fin, where the top source/drains 205 can be a doped, crystalline semiconductor.
In various embodiments, removal of portions of the top source/drain layer 200 forms gaps between the top source/drains 205 that can physically and electrically separate the top source/drains 205 and vertical fins 130, for example, to form separate FinFET devices. In various embodiments, top source/drains 205 can be electrically connected together with a conductive material to create merged top source/drains 205 that electrically connect two or more vertical fins to form merged devices. The resulting top source/drains 205 can have consistent sizes and crystal alignment.
In one or more embodiment, an insertion layer 220 can be formed on the top spacer layer 190, top source/drains 205, sacrificial spacers 215, and fin templates 140, where the insertion layer 220 can be formed by a conformal deposition (e.g., ALD, PEALD, LPCVD). The insertion layer 220 can be formed to a predetermined thickness, where the thickness can determine the size of a hollow space adjacent to the top source/drains 205.
In one or more embodiments, the insertion layer 220 can have a thickness in a range of about 5 nm to about 15 nm, or about 5 nm to about 10 nm, although other thicknesses are also contemplated. The thickness of the insertion layer 220 on the sidewalls of the top source/drains 205 can determine the width of sidewall spacers subsequently formed on the top spacer layer 190.
In various embodiments, the insertion layer 220 can be a dielectric material, including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon borocarbide (SiBC), silicon boro carbonitride (SiBCN), or combinations thereof. In a non-limiting exemplary embodiment, the insertion layer 220 can be the same material as sacrificial spacers 215.
In one or more embodiments, a portion of the insertion layer 220 can be removed to form sidewall spacers 225 on the top spacer layer 190, and on the sidewalls of the top source/drains 205 and sacrificial spacers 215. The portion of the insertion layer 220 can be removed using a directional etch (e.g., RIE) to expose portions of the underlying top spacer layer 190 and the tops surfaces of the sacrificial spacers 215 and fin templates 140.
In one or more embodiments, an interlayer dielectric (ILD) layer 230 can be formed on the sidewall spacers 225, sacrificial spacers 215, and fin templates 140, where the interlayer dielectric (ILD) layer 230 can be formed by a blanket deposition (e.g., CVD, PECVD). The ILD layer can cover and extend above the top spacer layer 230, sidewall spacers 225, sacrificial spacers 215, and fin templates 140.
In various embodiments the ILD layer 230 can be a dielectric material, including, but not limited to, silicon oxide (SiO) or a low-k material. A low-k dielectric can include, but not be limited to, carbon doped silicon oxide (SiO:C), fluorine doped silicon oxide (SiO:F), polymeric material, for example, tetraethyl orthosilicate (TEOS), hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ), and combinations thereof.
In one or more embodiments, one or more openings 240 can be formed in the ILD layer 230, where a separate opening 240 can be formed above each of one or more of the vertical fins 130, fin templates 140, and sacrificial spacers 215. The openings 240 can expose the top surfaces of the fin templates 140 and sacrificial spacers 215. The openings 240 can be formed in the ILD layer 230 by lithographic masking and etching processes, where a mask layer can be formed on the ILD layer.
In one or more embodiments, the exposed fin templates 140 and sacrificial spacers 215 can be removed by a selective isotropic etch, for example, a wet chemical etch or dry plasma etch, where removal of the sacrificial spacers 215 can expose an upper portion of the sidewall spacers 225. The sidewall spacers 225 can be removed using a selective etch, where removal of the fin template 140, sacrificial spacers 215, and sidewall spacers 225 above a vertical fin 130 and top source/drains 205 can form a hollow space 228 around the top source/drains 205 and a trough 229 over the vertical fin and between the inner sidewalls of the top source/drain. The hollow space 228 can expose the sidewalls of the top source/drains 205 and a portion of the top spacer layer 190.
In one or more embodiments, a barrier layer 250 can be formed on the sidewalls of the openings 240 and hollow spaces 228 formed in the ILD layer 230, where the barrier layer 250 can be formed by a conformal deposition (e.g., ALD, PEALD). The barrier layer 250 can also form on the exposed surfaces of the top source/drains 205 and the top extension region 137 of the vertical fins 130, where the barrier layer 250 can cover the surfaces of the trough 229. The barrier layer 250 can act as a seed layer for depositing a conductive material in the openings 240 and hollow spaces 228, and to prevent diffusion of the conductive material into the ILD layer 230 and top source/drains 205. The barrier layer 250 can be a conductive material. In various embodiments, the barrier layer 250 can be titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), niobium nitride (NbN), tungsten nitride (WN), tungsten carbon nitride (WCN), or combinations thereof, where the barrier layer can prevent diffusion and/or alloying of the metal contact fill material with the top source drain material, and/or anode/cathode material. In various embodiments, the barrier layer can be deposited in the trench(es) by ALD, CVD, MOCVD, PECVD, or any suitable combination thereof.
In various embodiment, the barrier layer 250 can have a thickness in a range of about 0.5 nm to about 3 nm, or about 1 nm to about 2 nm, although other thicknesses are also contemplated.
In one or more embodiments, a contact fill 260 can be formed on the barrier layer 250 in the openings 240, hollow spaces 228, and troughs 229, where the contact fill 260 can be formed by, for example, metal-organic chemical vapor deposition (MOCVD), ALD, CVD, PVD, plating, electroplating, or any suitable combination thereof, onto the barrier layer 250.
In various embodiment, the contact fill 260 can be a conductive material, for example, a metal including, but not limited to, tungsten (W), aluminum (Al), or copper (Cu), cobalt (Co), nickel (Ni), titanium (Ti), ruthenium (Ru).
In various embodiments, the contact fill 260 can fill in the hollow spaces 228 and wrap around the top source/drains 205 and top extension regions 137, where the contact fill 260 can be on portions of the sidewalls and top surfaces of the top source/drains 205.
In various embodiments, the formation of the contact fill 260 around the top source/drains 205 can increase the contact area of the contact fill 260 to the top source/drains 205 by at least two times (2×) or at least three time (3×), or at least four times (4×), where the increased electrical contact area can reduce the electrical resistance experienced by charge flowing through the vertical FinFET device. In a non-limiting exemplary embodiment, the interfacial surface area between a top source/drain 205 and a surrounding contact fill 260 can increase from about 20 nm2 to about 65 nm2, where the increase can depend on the height of the sidewalls of the top source/drains 205.
In one or more embodiments, a single opening 240 that exposes multiple fin templates 140, sidewall spacers 225, and sacrificial spacers 215 can be formed in the ILD layer 230. Segments of the ILD layer can remain between the sidewall spacers 225 on adjacent top source/drains forming intervening ILD blocks 245.
In one or more embodiments, the exposed fin templates 140, sacrificial spacers 215, and sidewall spacers 225 can be removed by a selective isotropic etch, for example, a wet chemical etch or dry plasma etch. The removal of the fin template 140, sacrificial spacers 215, and sidewall spacers 225 above a plurality of vertical fins 130 and top source/drains 205 can form an extended hollow space 228 around each of the top source/drains 205 and a trough 229 over each of the vertical fins and between the inner sidewalls of the top source/drains. Outer sidewalls of the top source/drains 205 can be facing an intervening ILD block 245.
In one or more embodiments, a barrier layer 250 can be formed on the sidewalls of the opening 240 and hollow spaces 228 formed in the ILD layer 230, and on the exposed surfaces of the top source/drains 205, top extension regions 137, and ILD blocks 245. A continuous barrier layer 250 can span multiple top source/drains 205 and vertical fins 130, where the continuous barrier layer 250 can form an electrical connection between each of the multiple top source/drains 205.
In one or more embodiments, a contact fill 260 can be formed on the barrier layer 250 in the opening 240, hollow spaces 228, and troughs 229, where the contact fill 260 can be a conductive metal. The contact fill 260 can form merged top source/drains 205 that electrically connect two or more vertical fins to form merged devices. The top source/drains 205 can be electrically connected together by the electrically conductive contact fill 260 and electrically conductive barrier layer 250.
The present embodiments can include a design for an integrated circuit chip, which can be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer can transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
Methods as described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
It should also be understood that material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes SixGe1-x where x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.
Reference in the specification to “one embodiment” or “an embodiment”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. For example, if the device in the FIGS. is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers e intervening layers can also be present.
It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.
It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Having described preferred embodiments of a system and method (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.
Claims
1. A method of forming a fin field effect device, comprising:
- forming one or more vertical fins on a substrate and a fin template on each of the one or more vertical fins;
- forming a gate structure on at least one of the one or more vertical fins;
- forming a top spacer layer on the at least one gate structure, wherein at least an upper portion of the at least one of the one or more vertical fins is exposed above the top spacer layer;
- forming a top source/drain layer on the top spacer layer and the exposed upper portion of the at least one of the one or more vertical fins;
- forming a sacrificial spacer on opposite sides of the at least one of the one or more fin templates and the top spacer layer; and
- removing a portion of the top source/drain layer not covered by the sacrificial spacer to form a top source/drain electrically connected to the at least one of the one or more vertical fins.
2. The method of claim 1, further comprising forming an insertion layer on the exposed portions of the top spacer layer, top source/drain, sacrificial spacer, and fin template.
3. The method of claim 2, further comprising heat treating the at least one of the one or more vertical fins and the top source/drain to form a top extension region in the upper portion of the at least one of the one or more vertical fins.
4. The method of claim 2, further comprising removing a portion of the insertion layer to form a sidewall spacer on the top source/drain and sacrificial spacer.
5. The method of claim 4, further comprising forming an interlayer dielectric (ILD) layer on the sidewall spacer, sacrificial spacer, and fin template.
6. The method of claim 5, further comprising forming openings in the ILD layer above the sacrificial spacer and fin template, and removing the sidewall spacer, sacrificial spacer, and fin template to form a hollow space adjacent to the top source/drain.
7. The method of claim 6, further comprising forming a conductive fill on the top source/drain, wherein the conductive fill fills in the hollow space to wrap around the top source/drain.
8. The method of claim 7, further comprising forming a barrier layer on the exposed surfaces of the hollow space, opening, and top source/drain, wherein the barrier layer is between the conductive fill and the surfaces of the hollow space, opening, and top source/drain.
9. The method of claim 8, further comprising forming a bottom source/drain layer between the substrate and the one or more vertical fins on the substrate.
10. A method of forming a fin field effect device, comprising:
- forming a bottom source/drain layer on a substrate;
- forming one or more vertical fins on the bottom source/drain layer and a fin template on each of the one or more vertical fins;
- forming a bottom spacer layer on the bottom source/drain layer;
- forming a gate structure on the bottom spacer layer and at least one of the one or more vertical fins;
- forming a top spacer layer on the at least one gate structure, wherein at least an upper portion of the at least one of the one or more vertical fins is exposed above the top spacer layer;
- forming a top source/drain layer on the top spacer layer and the exposed upper portion of the at least one of the one or more vertical fins;
- forming a sacrificial spacer on opposite sides of the at least one of the one or more fin templates and the top spacer layer; and
- removing a portion of the top source/drain layer not covered by the sacrificial spacer to form a top source/drain electrically connected to the at least one of the one or more vertical fins.
11. The method of claim 10, further comprising heat treating the at least one of the one or more vertical fins, the bottom source/drain layer and the top source/drain to form a top extension region in the upper portion of the at least one of the one or more vertical fins and a bottom extension region in the lower portion of the at least one of the one or more vertical fins.
12. The method of claim 10, wherein the one or more vertical fins has a width in the range of about 5 nanometers (nm) to about 15 nm.
13. The method of claim 10, wherein the sacrificial spacer on opposite sides of the at least one of the one or more fin templates has a width in a range of about 5 nm to about 10 nm.
14. The method of claim 10, wherein the top source/drain layer is formed by a lateral epitaxial or heteroepitaxial growth from an exposed sidewall of the at least one of the one or more vertical fins.
15. A vertical fin field effect transistor device, comprising:
- one or more vertical fins on a substrate;
- a top source/drain electrically connected to at least one of the one or more vertical fins; and
- a conductive fill that wraps around the sidewalls of the top source/drain.
16. The vertical fin field effect transistor device of claim 15, wherein the top source/drain and top surface of the at least one of the one or more vertical fins forms a trough, and the conductive fill fills in the trough.
17. The vertical fin field effect transistor device of claim 16, further comprising a barrier layer on the exposed surfaces of the hollow space, opening, at least one of the one or more vertical fins, and top source/drain, wherein the barrier layer is between the conductive fill and the surfaces of the hollow space, opening, at least one of the one or more vertical fins, and top source/drain.
18. The vertical fin field effect transistor device of claim 15, further comprising a top extension region in an upper portion of the at least one of the one or more vertical fins, and a bottom extension region in the lower portion of the at least one of the one or more vertical fins.
19. The vertical fin field effect transistor device of claim 18, further comprising a bottom source/drain layer between the substrate and the one or more vertical fins, and a gate structure on the bottom source/drain layer and at least one of the one or more vertical fins.
20. The vertical fin field effect transistor device of claim 19, further comprising a top spacer layer on the at least one gate structure, and a top spacer layer on the at least one gate structure, wherein the top extension region extends below the top spacer layer.
Type: Application
Filed: Sep 18, 2018
Publication Date: Mar 19, 2020
Patent Grant number: 10916638
Inventors: Kangguo Cheng (Schenectady, NY), Shogo Mochizuki (Clifton Park, NY), Choonghyun Lee (Rensselaer, NY), Juntao Li (Cohoes, NY)
Application Number: 16/134,526
