Patents by Inventor Kangguo Cheng

Kangguo Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220013986
    Abstract: A device and a method to produce an augmented-laser (ATLAS) comprising a bi-stable resistive system (BRS) integrated in series with a semiconductor laser. The laser exhibits reduction/inhibition of the Spontaneous Emission (SE) below lasing threshold by leveraging the abrupt resistance switch of the BRS. The laser system comprises a semiconductor laser and a BRS operating as a reversible switch. The BRS operates in a high resistive state in which a semiconductor laser is below a lasing threshold and emitting in a reduced spontaneous emission regime, and a low resistive state in which a semiconductor laser is above or equal to a lasing threshold and emitting in a stimulated emission regime. The BRS operating as a reversible switch is electrically connected in series across two independent chips or on a single wafer. The BRS is formed using insulator-to-metal transition (IMT) materials or is formed using threshold-switching selectors (TSS).
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Inventors: Julien FROUGIER, Kangguo CHENG, Ruilong Xie, Chanro PARK
  • Publication number: 20220013413
    Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.
    Type: Application
    Filed: September 23, 2021
    Publication date: January 13, 2022
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Publication number: 20220013521
    Abstract: An embodiment of the invention may include a semiconductor structure and method of manufacturing. The semiconductor structure may include a top channel and a bottom channel, wherein the top channel includes a plurality of vertically oriented channels. The bottom channel includes a plurality of horizontally oriented channels. The semiconductor structure may include a gate surrounding the top channel and the bottom channel. The semiconductor structure may include spacers located on each side of the gate. A first spacer includes a dielectric material located between the plurality of vertically oriented channels. A second spacer includes a dielectric material located between the plurality of horizontally oriented channels. This may enable spacer formation between the vertical spacers.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 13, 2022
    Inventors: Chen Zhang, Dechao Guo, Junli Wang, Ruilong Xie, Kangguo Cheng, Juntao Li, Chanro Park, Ruqiang Bao, Sung Dae Suk, Lan Yu, Heng Wu
  • Publication number: 20220013366
    Abstract: A first mask layer is formed on top of a semiconductor substrate. A mandrel material is formed perpendicular to the first mask layer. A second mask layer is formed on one or more exposed surfaces of the mandrel material. The mandrel material is removed. A pattern of the first mask layer and the second mask layer is transferred into the semiconductor substrate.
    Type: Application
    Filed: July 8, 2020
    Publication date: January 13, 2022
    Inventors: Kangguo Cheng, Chanro PARK, Ruilong Xie, Juntao LI
  • Patent number: 11221359
    Abstract: Techniques regarding determining device operability via a metal-induced layer exchange are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a dielectric membrane positioned between an amorphous semiconductor resistor layer and an electrically conductive metal layer. The dielectric membrane can facilitate a metal induced layer exchange that can experiences catalyzation by heat generated from operation of a semiconductor device positioned adjacent to the apparatus.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 11, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dexin Kong, Kangguo Cheng
  • Publication number: 20220005735
    Abstract: Embodiments of the invention include semiconductor devices having a first n-type S/D region, a second n-type S/D region, and a first layer of protective material over the second n-type S/D region, wherein the first layer of protective material includes a first type of material and a second type of material. A second layer of protective material is formed over the first layer of protective material, wherein the second layer of protective material includes an oxide of the second type of material. The devices further include a first p-type S/D region, a second p-type S/D region, and the second layer of protective material over the second p-type S/D region, wherein the second p-type S/D region second layer of protective material includes the first type of material and the second type of material, and wherein the second layer of protective material includes the oxide of the second type of material.
    Type: Application
    Filed: September 15, 2021
    Publication date: January 6, 2022
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Peng Xu
  • Publication number: 20220005934
    Abstract: Self-aligned semiconductor FET device source and drain contacts and techniques for formation thereof are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate; source and drains on opposite sides of the at least one gate; gate spacers offsetting the at least one gate from the source and drains; lower source and drain contacts disposed on the source and drains; upper source and drain contacts disposed on the lower source and drain contacts; and a silicide present between the lower source and drain contacts and the upper source and drain contacts.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 6, 2022
    Inventors: Chanro Park, Kangguo Cheng, Ruilong Xie, Juntao Li
  • Patent number: 11217680
    Abstract: A method of forming a semiconductor structure includes forming a fin over a substrate, forming a bottom source/drain over the substrate surrounding a first portion of sidewalls of the fin, and forming a bottom spacer over the bottom source/drain and surrounding a second portion of the sidewalls of the fin. The method also includes forming a T-shaped gate stack over the bottom spacer and surrounding a third portion of the sidewalls of the fin, forming a top spacer over the T-shaped gate stack and surrounding a fourth portion of the sidewalls of the fin, and forming a top source/drain over the top spacer and surrounding a fifth portion of the sidewalls and a top surface of the fin. The T-shaped gate stack includes a gate dielectric, a gate conductor, and a gate metal extending outward from a portion of sidewalls of the gate conductor between the bottom and top spacers.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: January 4, 2022
    Assignee: International Business Machines Corporation
    Inventors: Yi Song, Juntao Li, Huimei Zhou, Kangguo Cheng, Ardasheir Rahman
  • Publication number: 20210408233
    Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor, wherein the fabrication operations include forming a source or drain (S/D) region having stacked, spaced-apart, and doped S/D layers. The fabrication operations further include forming a multi-region S/D contact structure configured to contact a top surface, a bottom surface, and sidewalls of each of the stacked, spaced-apart, and doped S/D layers.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Inventors: Ruilong Xie, Reinaldo Vega, Kangguo Cheng, Chanro Park, Juntao Li
  • Publication number: 20210408016
    Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.
    Type: Application
    Filed: September 9, 2021
    Publication date: December 30, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kangguo CHENG, Juntao LI, Geng WANG, Qintao ZHANG
  • Patent number: 11211462
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of gate structures on a semiconductor fin, and forming a plurality of source/drain regions adjacent the plurality of gate structures. In the method, a germanium oxide layer is formed on the plurality of gate structures and on the plurality of source/drain regions, and portions of the germanium oxide layer on the plurality of source/drain regions are converted into a plurality of dielectric layers. The method also includes removing unconverted portions of the germanium oxide layer from the plurality of gate structures, and depositing a plurality of cap layers in place of the removed unconverted portions of the germanium oxide layer. The plurality of dielectric layers are removed, and a plurality of source/drain contacts are formed on the plurality of source/drain regions. The plurality of source/drain contacts are adjacent the plurality of cap layers.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: December 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chanro Park, ChoongHyun Lee, Kangguo Cheng, Ruilong Xie
  • Patent number: 11211291
    Abstract: A semiconductor device includes a base structure including a first interlayer dielectric (ILD) layer and a contact including a conductive liner disposed along a conductive core, a conductive plug disposed on the conductive liner between the conductive core and the first ILD layer to a height of the base structure, and a metallization level including a conductive line and a self-aligned via underneath the conductive line disposed on the contact and the conductive plug. The conductive plug protects underlying material and increases connectivity between the self-aligned via and the contact that was reduced due to misalignment.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: December 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Christopher J. Waskiewicz, Kangguo Cheng, Chih-Chao Yang
  • Patent number: 11211452
    Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor, wherein the fabrication operations include forming a source or drain (S/D) region having stacked, spaced-apart, and doped S/D layers. The fabrication operations further include forming a multi-region S/D contact structure configured to contact a top surface, a bottom surface, and sidewalls of each of the stacked, spaced-apart, and doped S/D layers.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: December 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Reinaldo Vega, Kangguo Cheng, Chanro Park, Juntao Li
  • Publication number: 20210399114
    Abstract: Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.
    Type: Application
    Filed: September 2, 2021
    Publication date: December 23, 2021
    Inventors: Kangguo Cheng, Julien Frougier, Nicolas Loubet
  • Patent number: 11205590
    Abstract: MOL non-SAC structures and techniques for formation thereof are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming gates over the fins and source/drains offset by gate spacers; lining upper sidewalls of the gates with a first dielectric liner; depositing a source/drain metal; lining upper sidewalls of the source/drain metal with a second dielectric liner; depositing a dielectric over the gates and source/drains; forming a first via in the dielectric which exposes the second dielectric liner over a select source/drain; removing the second dielectric liner from the select source/drain; forming a second via in the dielectric which exposes the first dielectric liner over a select gate; removing the first dielectric liner from the select gate; forming a source/drain contact in the first via; and forming a gate contact in the second via. A semiconductor device is also provided.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: December 21, 2021
    Assignee: International Business Machines Corporation
    Inventors: Su Chen Fan, Adra Carr, Ruilong Xie, Kangguo Cheng
  • Publication number: 20210391223
    Abstract: Nanopore structures are provided. In one aspect, a nanopore structure includes: an oxide shell surrounding a nanopore, wherein openings on both ends of the nanopore have a diameter D1, and a center of the nanopore has a diameter D2, wherein D1>D2. In another aspect, the nanopore structure includes: a first film disposed on a substrate; a second film disposed on the first film; at least one pore extending through the first film and the second film; a dielectric material disposed in the at least one pore; and a nanopore at a center of the dielectric material in the at least one pore, wherein a top opening to the nanopore has a first diameter d1, and a bottom opening to the nanopore has a second diameter d2, wherein d2>d1. Methods of forming the nanopore structures are also provided.
    Type: Application
    Filed: June 13, 2020
    Publication date: December 16, 2021
    Inventor: Kangguo Cheng
  • Patent number: 11201231
    Abstract: A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide upper portion has a greater germanium content than the narrower lower portion. In other embodiments, the silicon germanium alloy fin has a narrow upper portion and a wider lower portion. In this embodiment, the narrow upper portion of the silicon germanium alloy fin has a greater germanium content than the wider lower portion of the silicon germanium alloy fin.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: December 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Hong He, Juntao Li
  • Patent number: 11201089
    Abstract: Embodiments of the present invention are directed to techniques for forming a robust low-k bottom spacer for a vertical field effect transistor (VFET) using a spacer first, shallow trench isolation last process integration. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A first dielectric liner is formed on a sidewall of the semiconductor fin. A bottom spacer is formed over the substrate and on a sidewall of the first dielectric liner. The first dielectric liner is positioned between the semiconductor fin and the bottom spacer. Portions of the bottom spacer are removed to define a shallow trench isolation region.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: December 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hiroaki Niimi, Pietro Montanini, Kangguo Cheng
  • Publication number: 20210384320
    Abstract: A method of forming a comb-shaped transistor device is provided. The method includes forming a stack of alternating sacrificial spacer segments and channel segments on a substrate. The method further includes forming channel sidewalls on opposite sides of the stack of alternating sacrificial spacer segments and channel segments, and dividing the stack of alternating sacrificial spacer segments and channel segments into alternating sacrificial spacer slabs and channel slabs, wherein the channel slabs and channel sidewalls form a pair of comb-like structures. The method further includes trimming the sacrificial spacer slabs and channel slabs to form a nanosheet column of sacrificial plates and channel plates, and forming source/drains on opposite sides of the sacrificial plates and channel plates.
    Type: Application
    Filed: August 25, 2021
    Publication date: December 9, 2021
    Inventor: Kangguo Cheng
  • Patent number: 11195755
    Abstract: A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: December 7, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Zhenxing Bi, Dexin Kong