Abstract: Disclosed are a gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes stacked nanosheets having end portions adjacent to source/drain regions and a center portion between the end portions. The thickness of each nanosheet is tapered from a maximum thickness near the source/drain regions to a minimum thickness near and across the center portion. A gate wraps around each center portion. Inner spacers are aligned below the end portions between the gate and source/drain regions. The thickness of each inner spacer is tapered from a maximum thickness at the gate to a minimum thickness near the adjacent source/drain region. Each inner spacer includes a first spacer layer immediately adjacent to the gate, a second spacer layer immediately adjacent to the gate at least above the first spacer layer and further extending laterally beyond the first spacer layer toward or to the adjacent source/drain region, and, optionally, an air-gap.

Abstract: An approach for minimizing stack height and reducing resistance of an MRAM (Magnetoresistive random-access memory) is disclosed. The approach leverages an MRAM device with a T shape magnetic bottom electrode. The T shape magnetic bottom electrode can be made from a lower resistance metal such as cobalt. Furthermore, the method of creating the MRAM can include, depositing a low-k dielectric layer, forming bottom electrode via within the low-k dielectric layer, depositing bottom electrode metal liner on the bottom electrode via, depositing bottom electrode magnetic metal on the bottom electrode metal liner, planarizing the bottom electrode magnetic metal, depositing coupling layer and an MRAM stack on the bottom electrode magnetic metal, patterning and etching anisotropically the MRAM stack and depositing in-situ conformal dielectric layer and forming a top contact via on the MRAM stack.

Abstract: An approach provides a semiconductor structure for a first device with a first plurality of channels with a larger horizontal dimension than a vertical dimension of the first plurality of channels a second device comprising a second plurality of channels with a smaller horizontal dimension than the vertical dimension of the second plurality of channels. The first plurality of channels and the second plurality of channels have a same channel width in embodiments of the present invention. The first device is an n-type horizontal gate-all-around device and the second device is a p-type horizontal gate-all-around device.

Abstract: Embodiments disclosed herein include a semiconductor structure for reducing contact to contact shorting. The semiconductor structure may include a gate cut region with a liner and a dielectric core confined within a first lateral side of the liner and a second lateral side of the liner. The semiconductor structure may also include a first source/drain (S/D) contact overlapping the first lateral side and the dielectric core. The first S/D may include a line-end that contacts the second lateral side of the liner.

Abstract: Semiconductor devices and methods of forming the same include forming dummy gate spacers in a trench in a semiconductor substrate. A dummy gate is formed in the trench. An exposed dummy gate spacer is replaced with a sacrificial spacer. A cap layer is formed over the dummy gate. The cap layer is etched to expose the dummy gate. The sacrificial spacer is replaced with an isolation dielectric spacer. The dummy gate is replaced with a conductor.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a first recess partially through a substrate from a first side of the substrate, forming a dielectric layer in the first recess, forming a second recess partially through the dielectric layer from the first side of the substrate, and forming a buried power rail (BPR) in the second recess of the dielectric layer. The method also includes thinning the substrate from a second side of the substrate to a level of the dielectric layer, the second side of the substrate being opposite to the first side of the substrate.

Abstract: Semiconductor devices and methods of forming the same include a first device region, a second device region, and an inter-device dielectric spacer between the first device region and the second device region. The first device region includes a first device channel, a first-polarity work function metal layer on the first device channel, and a second-polarity work function metal layer on the first device channel. The second device region include a second device channel, and a second-polarity work function metal layer on the second device channel.

Abstract: The density of deuterium or hydrogen within phase change material (PCM) of a PCM memory cell reduces the active defects in the amorphous phase of the PCM by passivating dangling bonds, which results in the PCM becoming easier to nucleate during the SET process of the PCM memory cell. Resultingly, the addition of deuterium or hydrogen within the PCM relatively increases the SET programming voltage window of the PCM memory cell compared with a similar PCM cell without.

Abstract: A three-dimensional semiconductor structure with a bottom electrode in an interlayer dielectric material. The bottom electrode material with a rectangular shape has a first notch is in a top portion of a portion of the bottom electrode material. The first notch occurs in an intersection of the bottom electrode material with a top electrode material. A dielectric material contacts the bottom electrode material and a top surface of the interlayer dielectric material. The dielectric material is between five sides of the bottom electrode material and the top electrode material in the intersection of the bottom electrode material with the top electrode material and has a large contact area with of the bottom electrode material and the top electrode. When the bottom electrode material is a word line and the top electrode material is a bit line, the three-dimensional structure is a ReRAM cross point cell.

Abstract: Embodiments of the invention include a semiconductor device having a fin-shaped channel with a bottom surface, sidewalls and a top surface. A first source or drain (S/D) region is communicatively coupled to the fin-shaped channel, and a sub-channel region is between the bottom surface of the fin-shaped channel and a substrate. A U-shaped dielectric region within a first portion of the sub-channel region, wherein the U-shaped dielectric region includes a bottom isolation layer and a first inner spacer region. A wrap-around gate structure extends around the bottom surface, the sidewalls and the top surface of the fin-shaped channel, wherein a bottom region of the wrap-around gate structure is within a second portion of the sub-channel region.

Abstract: Disclosed are a gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes stacked nanosheets having end portions adjacent to source/drain regions and a center portion between the end portions. The thickness of each nanosheet is tapered from a maximum thickness near the source/drain regions to a minimum thickness near and across the center portion. A gate wraps around each center portion. Inner spacers are aligned below the end portions between the gate and source/drain regions. The thickness of each inner spacer is tapered from a maximum thickness at the gate to a minimum thickness near the adjacent source/drain region. Each inner spacer includes a first spacer layer immediately adjacent to the gate, a second spacer layer immediately adjacent to the gate at least above the first spacer layer and further extending laterally beyond the first spacer layer toward or to the adjacent source/drain region, and, optionally, an air-gap.

Abstract: A complementary metal-oxide semiconductor device formed by fabricating CMOS nanosheet stacks, forming a dielectric pillar dividing the CMOS nanosheet stacks, forming CMOS FET pairs on either side of the dielectric pillar, and forming a gate contact for at least one of the FETs.

Abstract: A semiconductor structure comprises a substrate having a first side and a second side opposite the first side, and a gate for at least one transistor device disposed above the first side of the substrate. The structure may further include a buried power rail at least partially disposed in the substrate and a gate tie-down contact connecting the gate to the buried power rail from the second side of the substrate. The structure may further or alternatively include one or more source/drain regions disposed over the first side of the substrate, and a gate contact connecting to a portion of the gate from the second side of the substrate, the portion of the gate being adjacent to at least one of the one or more source/drain regions.

Abstract: An integrated circuit component includes a first layer including first and second areas of epitaxy material. The first layer has a first polarity. The component further includes a second layer including third and fourth areas of epitaxy material. The second layer has a second polarity that is different than the first polarity. The third area is arranged at least partially above the first area, and the fourth area is arranged at least partially above the second area. The integrated circuit component further includes an interconnect in direct contact with one of the first area and the third area and in direct contact with one of the second area and the fourth area. The interconnect has a top surface that does not extend substantially above an uppermost surface of the second layer.

Abstract: Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region.

Abstract: A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

Abstract: Semiconductor structures are disclosed which comprise semiconductor devices having buried power rails. In one example, a semiconductor structure comprises a plurality of semiconductor devices. Each of the semiconductor devices is isolated from an adjacent semiconductor device by a dielectric layer. The semiconductor structure further comprises a first diffusion break extending across the plurality of semiconductor devices, a second diffusion break extending across the plurality of semiconductor devices and a plurality of gates extending across the plurality of semiconductor devices. The gates are disposed between the first diffusion break and the second diffusion break. Each semiconductor device comprises a power rail extending between the first diffusion break and the second diffusion break under the plurality of gates.

Abstract: An integrated circuit has a frontside and a backside and includes a first CMOS cell of complementary metal oxide semiconductor (CMOS) devices. A first row of gate cuts and a second row of gate cuts bound the first CMOS cell. A gate is associated with at least one of the devices in the first CMOS cell. A first signal line is at the frontside of the integrated circuit. A signal connection is provided from the first signal line to the backside of the integrated circuit. A local interconnect is provided at the backside of the integrated circuit from the signal connection to the gate.

Abstract: A method of manufacturing a resistive random access memory (RRAM) cell includes forming an electrode, and forming an insulator on the electrode, the insulator having a pore and an insulator surface. The method also includes forming a dielectric material on the insulator and the electrode using an atomic layer deposition (ALD) process such that a seam exists in the dielectric material, and forming another electrode on the dielectric material.

Abstract: Embodiments disclosed herein include a semiconductor device. The semiconductor device may include a magnetoresistive random access memory (MRAM) array. The MRAM array may include defective MRAM cells, redundancy MRAM cells, and operational MRAM cells. The semiconductor device may also include an address input electrically connected to the MRAM array and a selector circuit wired to the address input and an output of the MRAM array. The selector circuit may be configured to read the defective MRAM cells to identify the MRAM array.