Abstract: Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.

Abstract: Embodiments of present invention provide a ferroelectric random-access memory (FeRAM) cell. The FeRAM cell includes a vertical channel between a bottom source/drain region and a top source/drain region; a gate oxide surrounding the vertical channel; and a ferroelectric layer surrounding the gate oxide, wherein the ferroelectric layer has two or more sections of different horizontal thicknesses between the bottom source/drain region and the top source/drain region. A method of manufacturing the FeRAM cell is also provided.

Abstract: Tiered-profile contacts for semiconductor devices and techniques for formation thereof are provided In one aspect, a method for forming tiered-profile contacts to a semiconductor device includes: depositing a first oxide layer over the semiconductor device; depositing a second oxide layer on the first oxide layer; patterning contact trenches through the first/second oxide layer down to the semiconductor device; isotropically etching a top portion of the contact trenches selective to a bottom portion of the contact trenches based on the second oxide layer having a greater etch rate than the first oxide layer to make the top portion of the contact trenches wider than the bottom portion; and filling the contact trenches with a contact metal(s) to form the tiered-profile contacts. Other methods to form tiered-profile contacts using sacrificial spacers as well as structures including the present tiered-profile contacts are also provided.

Abstract: A semiconductor device includes a dielectric isolation layer, a plurality of gates formed above the dielectric isolation layer, a plurality of source/drain regions above the dielectric isolation layer between the plurality of gates, and at least one contact placeholder for a backside contact. The at least one contact placeholder contacts a bottom surface of a first source/drain region of the plurality of source/drain regions. The semiconductor device further includes at least one backside contact contacting a bottom surface of a second source/drain region of the plurality of source/drain regions, and a buried power rail arranged beneath, and contacting the at least one backside contact.

Abstract: A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

Abstract: Semiconductor structures are disclosed which comprise semiconductor devices having thin multi-layer channel stacks. In one example, a semiconductor structure comprises a gate structure comprising a multi-layer channel stack. The multi-layer channel stack comprises a first dielectric layer, a second dielectric layer, and a channel layer disposed between the first and second dielectric layers. The semiconductor structure further comprises a first source/drain region disposed on a first side of the gate structure and in electrical contact with a first end portion of the multi-layer channel stack and a second source/drain region disposed on a second side of the gate structure and in electrical contact with a second end portion of the multi-layer channel stack.

Abstract: A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.

Abstract: A method of forming a semiconductor structure includes patterning a hard mask layer over a top surface of a substrate. The method also includes forming a first portion of one or more vertical fins below the patterned hard mask layer. The method further includes forming a top spacer on sidewalls of the hard mask layer and the first portion of the one or more vertical fins. The method further includes forming a second portion of the one or more vertical fins in the substrate below the top spacer and trimming sidewalls of the second portion of the one or more vertical fins. The method further includes forming an interfacial layer on the trimmed sidewalls of the second portion of the one or more vertical fins. The one or more vertical fins provide one or more vertical transport channels for one or more vertical transport field-effect transistors.

Abstract: A vertical field-effect transistor device includes a substrate comprising a semiconductor material, and a set of fins formed from the semiconductor material and extending vertically with respect to the substrate. The vertical field-effect transistor device further includes gate structures disposed on the substrate and on a portion of sidewalls of the set of fins, spacers disposed on the gate structures and on a remaining portion of the sidewalls of the set of fins, source/drain regions disposed over top portions of the set of fins, and a metal liner disposed adjacent and over the source/drain regions such that a wrap-around contact is defined to cover an upper area of the source/drain regions. A portion of the source/drain regions is configured to have a lateral width less than a width between adjacent gate structures on the respective fin.

Abstract: Disclosed are a gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes stacked nanosheets having end portions adjacent to source/drain regions and a center portion between the end portions. The thickness of each nanosheet is tapered from a maximum thickness near the source/drain regions to a minimum thickness near and across the center portion. A gate wraps around each center portion. Inner spacers are aligned below the end portions between the gate and source/drain regions. The thickness of each inner spacer is tapered from a maximum thickness at the gate to a minimum thickness near the adjacent source/drain region. Each inner spacer includes a first spacer layer immediately adjacent to the gate, a second spacer layer immediately adjacent to the gate at least above the first spacer layer and further extending laterally beyond the first spacer layer toward or to the adjacent source/drain region, and, optionally, an air-gap.

Abstract: An approach for minimizing stack height and reducing resistance of an MRAM (Magnetoresistive random-access memory) is disclosed. The approach leverages an MRAM device with a T shape magnetic bottom electrode. The T shape magnetic bottom electrode can be made from a lower resistance metal such as cobalt. Furthermore, the method of creating the MRAM can include, depositing a low-k dielectric layer, forming bottom electrode via within the low-k dielectric layer, depositing bottom electrode metal liner on the bottom electrode via, depositing bottom electrode magnetic metal on the bottom electrode metal liner, planarizing the bottom electrode magnetic metal, depositing coupling layer and an MRAM stack on the bottom electrode magnetic metal, patterning and etching anisotropically the MRAM stack and depositing in-situ conformal dielectric layer and forming a top contact via on the MRAM stack.

Abstract: An approach provides a semiconductor structure for a first device with a first plurality of channels with a larger horizontal dimension than a vertical dimension of the first plurality of channels a second device comprising a second plurality of channels with a smaller horizontal dimension than the vertical dimension of the second plurality of channels. The first plurality of channels and the second plurality of channels have a same channel width in embodiments of the present invention. The first device is an n-type horizontal gate-all-around device and the second device is a p-type horizontal gate-all-around device.

Abstract: Embodiments disclosed herein include a semiconductor structure for reducing contact to contact shorting. The semiconductor structure may include a gate cut region with a liner and a dielectric core confined within a first lateral side of the liner and a second lateral side of the liner. The semiconductor structure may also include a first source/drain (S/D) contact overlapping the first lateral side and the dielectric core. The first S/D may include a line-end that contacts the second lateral side of the liner.

Abstract: Semiconductor devices and methods of forming the same include a first device region, a second device region, and an inter-device dielectric spacer between the first device region and the second device region. The first device region includes a first device channel, a first-polarity work function metal layer on the first device channel, and a second-polarity work function metal layer on the first device channel. The second device region include a second device channel, and a second-polarity work function metal layer on the second device channel.

Abstract: Semiconductor devices and methods of forming the same include forming dummy gate spacers in a trench in a semiconductor substrate. A dummy gate is formed in the trench. An exposed dummy gate spacer is replaced with a sacrificial spacer. A cap layer is formed over the dummy gate. The cap layer is etched to expose the dummy gate. The sacrificial spacer is replaced with an isolation dielectric spacer. The dummy gate is replaced with a conductor.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a first recess partially through a substrate from a first side of the substrate, forming a dielectric layer in the first recess, forming a second recess partially through the dielectric layer from the first side of the substrate, and forming a buried power rail (BPR) in the second recess of the dielectric layer. The method also includes thinning the substrate from a second side of the substrate to a level of the dielectric layer, the second side of the substrate being opposite to the first side of the substrate.

Abstract: A three-dimensional semiconductor structure with a bottom electrode in an interlayer dielectric material. The bottom electrode material with a rectangular shape has a first notch is in a top portion of a portion of the bottom electrode material. The first notch occurs in an intersection of the bottom electrode material with a top electrode material. A dielectric material contacts the bottom electrode material and a top surface of the interlayer dielectric material. The dielectric material is between five sides of the bottom electrode material and the top electrode material in the intersection of the bottom electrode material with the top electrode material and has a large contact area with of the bottom electrode material and the top electrode. When the bottom electrode material is a word line and the top electrode material is a bit line, the three-dimensional structure is a ReRAM cross point cell.

Abstract: The density of deuterium or hydrogen within phase change material (PCM) of a PCM memory cell reduces the active defects in the amorphous phase of the PCM by passivating dangling bonds, which results in the PCM becoming easier to nucleate during the SET process of the PCM memory cell. Resultingly, the addition of deuterium or hydrogen within the PCM relatively increases the SET programming voltage window of the PCM memory cell compared with a similar PCM cell without.

Abstract: Embodiments of the invention include a semiconductor device having a fin-shaped channel with a bottom surface, sidewalls and a top surface. A first source or drain (S/D) region is communicatively coupled to the fin-shaped channel, and a sub-channel region is between the bottom surface of the fin-shaped channel and a substrate. A U-shaped dielectric region within a first portion of the sub-channel region, wherein the U-shaped dielectric region includes a bottom isolation layer and a first inner spacer region. A wrap-around gate structure extends around the bottom surface, the sidewalls and the top surface of the fin-shaped channel, wherein a bottom region of the wrap-around gate structure is within a second portion of the sub-channel region.

Abstract: Disclosed are a gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes stacked nanosheets having end portions adjacent to source/drain regions and a center portion between the end portions. The thickness of each nanosheet is tapered from a maximum thickness near the source/drain regions to a minimum thickness near and across the center portion. A gate wraps around each center portion. Inner spacers are aligned below the end portions between the gate and source/drain regions. The thickness of each inner spacer is tapered from a maximum thickness at the gate to a minimum thickness near the adjacent source/drain region. Each inner spacer includes a first spacer layer immediately adjacent to the gate, a second spacer layer immediately adjacent to the gate at least above the first spacer layer and further extending laterally beyond the first spacer layer toward or to the adjacent source/drain region, and, optionally, an air-gap.