Patents by Inventor Kangguo Cheng

Kangguo Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10790379
    Abstract: A method for fabricating a semiconductor structure is provided. The method includes forming one or more vertical fins on a semiconductor substrate with a hardmask on a top surface of the one or more vertical fins. The method includes forming an opening in the hardmask and the one or more vertical fins and in a portion of the semiconductor substrate to form a plurality of vertical fins. The method includes depositing an anchor layer in the opening. The method includes depositing a liner layer on sidewalls of each of the vertical fins and above a top surface of the semiconductor substrate. The method includes forming an angled recessed region in the exposed portion of each of the vertical fins below the liner layer and in the semiconductor substrate. The method includes forming a bottom source/drain region in the angled recessed region.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Ruilong Xie, Kangguo Cheng
  • Patent number: 10790825
    Abstract: A method, system, and apparatus for setting an on-chip password is provided. In an embodiment, a method for programming an on-chip password includes determining a desired logic state for a field-effect transistor according to the on-chip password. The desired logic state is one of a first logic state and a second logic state. The method also includes subjecting one of a source and a drain of the field-effect transistor to hot-carrier stress according to the desired logic state to produce one of a symmetric state of the field-effect transistor and an asymmetric state of the field-effect transistor. The symmetric state corresponds to one of the first and second logic states. The asymmetric state corresponds to the other one of the first and second logic states.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 10788446
    Abstract: A semiconductor device includes a first passivation layer disposed on a semiconductor base. The semiconductor device further includes a dielectric layer disposed on the first passivation layer. The semiconductor device further includes a plurality of pillars disposed in an opening in the dielectric layer and the first passivation layer and from a top surface of the semiconductor base. The semiconductor device further includes a metal layer disposed on the exterior surfaces of the plurality of pillars and sidewalls of the dielectric layer and the first passivation layer and on the exposed top surface of the semiconductor base. The semiconductor device further includes a second passivation layer disposed on the metal layer and a top surface of the semiconductor device; wherein the second passivation layer has an electrical charge.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, Ruilong Xie, Chanro Park
  • Patent number: 10790376
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers; contacts connecting to at least one gate structure of the plurality of gate structures; and at least one metallization feature connecting to the source and drain regions and extending over the sidewall spacers.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Chanro Park, Julien Frougier, Kangguo Cheng, Andre P. Labonte
  • Publication number: 20200303244
    Abstract: A semiconductor wafer includes a substrate. The substrate includes a first substrate region doped with a first dopant and a second substrate region doped with a second dopant. The semiconductor wafer further includes a buried oxide (BOX) layer formed on the substrate and a channel layer formed above the BOX layer. A first transistor is operably disposed on the substrate in the first substrate region and a second transistor is operably disposed on the substrate in the second substrate region. First doped source and drain structures electrically connected to the substrate in the first substrate region and separated by portions of the channel layer and the BOX layer. Second doped source and drain structures electrically connected to the substrate in the second substrate region and separated by portions of the channel layer and the BOX layer.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Inventors: Chen Zhang, Xin Miao, Wenyu XU, Kangguo Cheng
  • Publication number: 20200303263
    Abstract: A method of forming a semiconductor structure includes forming a stacked vertical transport field-effect transistor (VTFET) structure and a sacrificial layer in contact with a source/drain region of the stacked vertical transport field-effect transistor structure. A masking layer is formed over the sacrificial layer. The masking layer defines a pattern to be patterned into the sacrificial layer. The sacrificial layer is patterned based on the masking layer to form a patterned sacrificial layer and the masking layer is removed. A portion of the stacked VTFET structure is etched down to a surface of the patterned sacrificial layer and the patterned sacrificial layer is removed to form a channel exposing the source/drain region. A contact material is formed in the etched portion of the stacked vertical transport field-effect transistor structure and in the channel. The contact material is formed in contact with the exposed source/drain region.
    Type: Application
    Filed: March 21, 2019
    Publication date: September 24, 2020
    Inventors: Chen Zhang, Tenko Yamashita, Kangguo Cheng, Oleg Gluschenkov
  • Publication number: 20200303543
    Abstract: Embodiments of the present invention are directed to forming a wrap-around contact (WAC) for a vertical field effect transistor (VFET). In a non-limiting embodiment of the invention, a top spacer is formed on a surface of a gate. A sacrificial spacer is formed on the top spacer. A source/drain region is formed over the top spacer and between sidewalls of the sacrificial spacer. The sacrificial spacer can be replaced with a wrap-around contact. The source/drain region can include a first material, the sacrificial spacer can include a second material, and the second material can be selected such that the second material can be etched selective to the first material.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Inventors: Kangguo Cheng, Chanro Park, Julien Frougier, RUILONG XIE
  • Publication number: 20200303264
    Abstract: A method of forming a semiconductor structure includes forming a first portion of a source/drain contact over a source/drain region of a fin-type field-effect transistor (FinFET), the source/drain region being formed over a fin providing a channel region of the FinFET and being adjacent a gate spacer surrounding a gate region of the FinFET. The method also includes forming a first interlayer dielectric (ILD) layer over the first portion of the source/drain contact, the gate spacer and the gate region, and forming a second ILD layer over the first ILD layer. The method further includes forming a second portion of the source/drain contact over the first portion of the source/drain contact in a first opening in the first ILD layer, and forming a third portion of the source/drain contact over the second portion of the source/drain contact in a second opening in the second ILD layer. The second opening is larger than the first opening.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Inventors: Chanro Park, Kangguo Cheng, Ruilong Xie, Hari Prasad Amanapu
  • Patent number: 10784363
    Abstract: Various methods and structures for fabricating a contact for a semiconductor FET or FinFET device. A semiconductor FET structure includes a substrate, a source/drain region layer and source/drain contact. First and second gate spacers are adjacent respective first and second opposing sides of the source/drain contact. The source/drain contact is disposed directly on and contacting the entire source/drain region layer, and at a vertical level thereabove, the source/drain contact being recessed to a limited horizontal area continuing vertically upwards from the vertical level. The limited horizontal area horizontally extending along less than a full horizontal length of a vertical sidewall of the first and second gate spacers, and less than fully covering the source/drain region layer. A method uses a reverse contact mask to form a shape of the source/drain contact into an inverted “T” shape.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10784333
    Abstract: Techniques for generating enhanced inductors and other electronic devices are presented. A device generator component (DGC) performs directed-self assembly (DSA) co-polymer deposition on a circular guide pattern formed in low-k dielectric film, and DSA annealing to form two polymers in the form of alternating concentric rings; performs a loop cut in the concentric rings to form concentric segments; fills the cut portion with insulator material; selectively removes first polymer, fills the space with low-k dielectric, and planarizes the surface; selectively removes the second polymer, fills the space with conductive material, and planarizes the surface; deposits low-k film on top of the concentric segments and insulator material that filled the loop cut portion; forms vias in the low-k film, wherein each via spans from an end of one segment to an end of another segment; and fills vias with conductive material to form conductive connectors to form substantially spiral conductive structure.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Xu, Kangguo Cheng, Xuefeng Liu, Chi-Chun Liu, Yongan Xu
  • Patent number: 10784357
    Abstract: A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10784370
    Abstract: Method and structures for forming vertical transistors with uniform fin thickness. A structure includes: a substrate, a plurality of fins over the substrate, a top and a bottom source/drain region in contact with the plurality of fins, respectively, where the bottom source/drain region has an alternating topography, and a bottom spacer in contact with the bottom source/drain region, where the bottom spacer conforms to the alternating topography of the bottom-source drain region.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 10784364
    Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer, patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other, and etching exposed sides of the plurality of silicon germanium layers to remove portions of the silicon germanium layers from lateral sides of each of the plurality of silicon germanium layers, wherein a concentration of germanium is varied between each of the plurality of silicon germanium layers to compensate for variations in etching rates between the plurality of silicon germanium layers to result in remaining portions of each of the plurality of silicon germanium layers having the same or substantially the same width as each other.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10784148
    Abstract: Techniques for forming uniform fin height on oxide substrates for finFET devices is provided. In one aspect, a method for forming a finFET device includes: patterning fins in a wafer; burying the fins in an oxide material; recessing the oxide material to form a recessed oxide material in between the fins; selectively forming sidewall spacers, above the recessed oxide material, alongside top portions of one or more of the fins that serve as active fins of the finFET device; converting bottom portions of the one or more fins beneath the sidewall spacers to an oxide, such that the active fins are present on the oxide; and forming gates over the active fins. A finFET device is also provided.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peng Xu, Kangguo Cheng
  • Publication number: 20200294997
    Abstract: Methods and system of generating a code are described. A device can receive a request to generate a code. The device can select a set of cells among a plurality of cells. The device can determine current through the selected cells in a forward mode. The device can determine current through the selected cells in a reverse mode. The device can determine a set of differences between the currents of the forward mode and the reverse mode. The set of differences corresponds to the set of selected cells. The device can transform the set of differences into the code. The device can output the code to respond to the request.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 17, 2020
    Inventor: Kangguo Cheng
  • Publication number: 20200294866
    Abstract: A method for forming a semiconductor device includes forming a structure having at least a first nanosheet stack for a first device, a second nanosheet stack for a second device and disposed over the first nanosheet stack, a disposable gate structure, and a gate spacer. The disposable gate structure and sacrificial layers of the first and second nanosheet stacks are removed thereby forming a plurality of cavities. A conformal gate dielectric layer is formed in the plurality cavities and surrounding at least portions of the first and second nanosheet stacks. A first conformal work function layer is formed in contact with the gate dielectric layer. Portions of the first conformal work function layer are removed without using a mask from at least the second nanosheet stack. A second conformal work function layer is formed on exposed portions of the gate dielectric layer.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Inventors: Kangguo CHENG, Juntao LI, Ruilong Xie, Chanro PARK
  • Publication number: 20200292490
    Abstract: A method for fabricating a semiconductor device including an ion-sensitive field-effect transistor (ISFET) with enhanced sensitivity includes forming a microwell within a stack including alternating dielectric layers formed on a semiconductor chip corresponding to an ISFET. Forming the stack includes forming a first dielectric layer including a first material and a second dielectric layer including a second material. The method further includes etching the second dielectric layer selective to at least the first dielectric layer using a wet etch process, and forming a macrowell from the microwell having a shape defined by the etching.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 17, 2020
    Inventors: Kangguo Cheng, Chanro Park, Juntao Li, Ruilong Xie
  • Publication number: 20200295151
    Abstract: Techniques regarding non-SAC semiconductor devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can further comprise a gate positioned adjacent a channel region of a semiconductor body for a field effect transistor. The gate can comprise a metal liner, and wherein the metal liner is an interface between a first metal layer of the gate and a second metal layer of the gate.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 17, 2020
    Inventors: Ruilong Xie, Hari Prasad Amanapu, Kangguo Cheng, Chanro Park
  • Publication number: 20200292611
    Abstract: Techniques regarding determining device operability via a metal-induced layer exchange are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a dielectric membrane positioned between an amorphous semiconductor resistor layer and an electrically conductive metal layer. The dielectric membrane can facilitate a metal induced layer exchange that can experiences catalyzation by heat generated from operation of a semiconductor device positioned adjacent to the apparatus.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Inventors: Dexin Kong, Kangguo Cheng
  • Publication number: 20200295198
    Abstract: Semiconductor devices and methods for forming the semiconductor devices include forming a sacrificial layer on a substrate on each side of a stack of nanosheets, the stack of nanosheets including first nanosheets and second nanosheets stacked in alternating fashion with a dummy gate structure formed thereon. Source and drain regions are grown on from the sacrificial layer and from ends of the second nanosheets to form source and drain regions in contact with each side of the stack of nanosheets. The sacrificial layer is removed. An interlevel dielectric is deposited around the source and drain regions to fill between the source and drain regions and the substrate.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 17, 2020
    Inventors: Kangguo Cheng, Juntao Li, Peng Xu, Zhenxing Bi