Patents by Inventor Kangguo Cheng
Kangguo Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12262549Abstract: A method of forming a comb-shaped transistor device is provided. The method includes forming a stack of alternating sacrificial spacer segments and channel segments on a substrate. The method further includes forming channel sidewalls on opposite sides of the stack of alternating sacrificial spacer segments and channel segments, and dividing the stack of alternating sacrificial spacer segments and channel segments into alternating sacrificial spacer slabs and channel slabs, wherein the channel slabs and channel sidewalls form a pair of comb-like structures. The method further includes trimming the sacrificial spacer slabs and channel slabs to form a nanosheet column of sacrificial plates and channel plates, and forming source/drains on opposite sides of the sacrificial plates and channel plates.Type: GrantFiled: August 25, 2021Date of Patent: March 25, 2025Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Kangguo Cheng
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Patent number: 12255651Abstract: Provided is a reconfigurable Ring Oscillator (RO) Physical Unclonable Function (PUF), which comprises a NAND gate with a first input line and a second input line and a series of inverters with at least one memory cell placed between two inverters of the series of inverters, where an output of a last inverter provides input to the second input line, and where the memory cell comprises a Field Effect Transistor (FET). In addition, the reconfigurable RO PUF comprises a frequency counter, where the output of the last inverter provides input to the frequency counter. In normal operation mode, the first input line is on to enable ring oscillation and the FET is off. In reconfiguration mode, the first input line is off and the FET is on to enable reconfiguration.Type: GrantFiled: October 25, 2023Date of Patent: March 18, 2025Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Julien Frougier, Carl Radens, Ruilong Xie
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Patent number: 12256554Abstract: A device includes a plurality of magnetic random-access memory (MRAM) cells in a first region of the device; and a dummy MRAM pillar disposed in a second region of the device, wherein the dummy MRAM pillar is not connected to an active metal feature.Type: GrantFiled: September 27, 2021Date of Patent: March 18, 2025Assignee: International Business Machines CorporationInventors: Ruilong Xie, Kangguo Cheng, Dimitri Houssameddine, Julien Frougier
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Patent number: 12256653Abstract: A phase change memory (PCM) device is provided. The PCM device includes a bottom electrode formed on a substrate, a heater electrode formed on the bottom electrode, the heater electrode having a tapered portion that becomes narrower in a direction away from the substrate. The PCM device also includes an interlayer dielectric (ILD) layer formed on the tapered portion of the heater electrode, the interlayer layer dielectric including an airgap that at least partially surrounds the tapered portion of the heater electrode. The PCM device also includes a phase change layer formed on the heater electrode, and a top electrode formed on the phase change layer.Type: GrantFiled: December 9, 2021Date of Patent: March 18, 2025Assignee: International Business Machines CorporationInventors: Juntao Li, Kangguo Cheng, Dexin Kong, Ruilong Xie
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Patent number: 12245517Abstract: A memory device that includes an magnetoresistive random-access memory (MRAM) stack positioned on an electrode, a metal line in contact with the electrode, and a sidewall spacer abutting the MRAM stack. The memory device also includes a stepped reach through conductor having a first height portion of the stepped reach through conductor in an undercut region positioned between the sidewall spacer and the metal line, and a second height portion having a greater height dimensions than the first height portion abutting an outer sidewall of the sidewall spacer.Type: GrantFiled: September 1, 2021Date of Patent: March 4, 2025Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruilong Xie, Dimitri Houssameddine, Kangguo Cheng, Julien Frougier, Bruce B. Doris
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Patent number: 12245530Abstract: A ring-shaped heater, system, and method to gradually change the conductance of the phase change memory through a concentric ring-shaped heater. The system may include a phase change memory. The phase change memory may include a bottom electrode. The phase change memory may also include a ring-shaped heater patterned on top of the bottom electrode, the ring-shaped heater including: a plurality of concentric conductive heating layers, and a plurality of insulator spacers, where each insulator spacer separates each conductive heating layer. The phase change memory may also include a phase change material proximately connected to the ring-shaped heater. The phase change memory may also include a top electrode proximately connected to the phase change material.Type: GrantFiled: June 25, 2021Date of Patent: March 4, 2025Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Carl Radens, Juntao Li, Ruilong Xie, Praneet Adusumilli, Oscar van der Straten, Alexander Reznicek
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Patent number: 12237328Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.Type: GrantFiled: April 19, 2023Date of Patent: February 25, 2025Assignee: Adeia Semiconductor Solutions LLCInventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
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Patent number: 12230544Abstract: A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.Type: GrantFiled: November 2, 2022Date of Patent: February 18, 2025Assignee: Adeia Semiconductor Solutions LLCInventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthiharan, John Zhang
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Patent number: 12224203Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.Type: GrantFiled: April 7, 2023Date of Patent: February 11, 2025Assignee: Adeia Semiconductor Solutions LLCInventors: Kangguo Cheng, Thomas J. Haigh, Juntao Li, Eric G. Liniger, Sanjay C. Mehta, Son V. Nguyen, Chanro Park, Tenko Yamashita
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Patent number: 12219885Abstract: A phase change memory includes a substrate, a plurality of first phase change elements on the substrate, a plurality of electrodes on the plurality of first phase change elements, and a second phase change element connecting the plurality of electrodes and disposed between the plurality of first phase change elements.Type: GrantFiled: November 19, 2021Date of Patent: February 4, 2025Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Juntao Li, Zuoguang Liu, Arthur Gasasira
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Patent number: 12219884Abstract: A phase change memory, system, and method for gradually changing the conductance and resistance of the phase change memory while preventing resistance drift. The phase change memory may include a phase change material. The phase change memory may also include a bottom electrode. The phase change memory may also include a heater core proximately connected to the bottom electrode. The phase change memory may also include a set of conductive rings surrounding the heater core, where the set of conductive rings comprises one or more conductive rings, and where the set of conductive rings are proximately connected to the phase change material. The phase change memory may also include a set of spacers, where a spacer, from the set of spacers, separates a portion of a conductive ring, from the set of conductive rings, from the heater core.Type: GrantFiled: September 30, 2021Date of Patent: February 4, 2025Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Carl Radens, Juntao Li, Ruilong Xie, Praneet Adusumilli, Oscar van der Straten, Alexander Reznicek, Zuoguang Liu, Arthur Gasasira
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Patent number: 12208386Abstract: 3D nanochannel interleaved devices for molecular manipulation are provided. In one aspect, a method of forming a device includes: forming a pattern on a substrate of alternating mandrels and spacers alongside the mandrels; selectively removing the mandrels from a front portion of the pattern forming gaps between the spacers; selectively removing the spacers from a back portion of the pattern forming gaps between the mandrels; filling i) the gaps between the spacers with a conductor to form first electrodes and ii) the gaps between the mandrels with the conductor to form second electrodes; and etching the mandrels and the spacers in a central portion of the pattern to form a channel (e.g., a nanochannel) between the first electrodes and the second electrodes, wherein the first electrodes and the second electrodes are offset from one another across the channel, i.e., interleaved. A device formed by the method is also provided.Type: GrantFiled: August 15, 2023Date of Patent: January 28, 2025Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Kangguo Cheng, Donald Canaperi, Shawn Peter Fetterolf
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Patent number: 12211848Abstract: Provided is a semiconductor structure with shared gated devices. The semiconductor structure comprises a substrate and a bottom dielectric isolation (BDI) layer on top of the substrate. The structure further comprises a pFET region that includes a p-doped Source-Drain epitaxy material and a first nanowire matrix above the BDI layer. The structure further comprises an nFET region that includes a n-doped Source-Drain epitaxy material and a second nanowire matrix above the BDI layer. The structure further comprises a conductive gate material on top of a portion of the first nanowire matrix and the second nanowire matrix. The structure further comprises a vertical dielectric pillar separating the pFET region and the nFET region. The vertical dielectric pillar extends downward through the BDI layer into the substrate. The vertical dielectric pillar further extends upward through the conductive gate material to a dielectric located above the gate region.Type: GrantFiled: July 23, 2021Date of Patent: January 28, 2025Assignee: International Business Machines CorporationInventors: Julien Frougier, Ruilong Xie, Kangguo Cheng, Chanro Park
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Patent number: 12210011Abstract: Nanopore structures are provided. In one aspect, a nanopore structure includes: an oxide shell surrounding a nanopore, wherein openings on both ends of the nanopore have a diameter D1, and a center of the nanopore has a diameter D2, wherein D1>D2. In another aspect, the nanopore structure includes: a first film disposed on a substrate; a second film disposed on the first film; at least one pore extending through the first film and the second film; a dielectric material disposed in the at least one pore; and a nanopore at a center of the dielectric material in the at least one pore, wherein a top opening to the nanopore has a first diameter d1, and a bottom opening to the nanopore has a second diameter d2, wherein d2>d1. Methods of forming the nanopore structures are also provided.Type: GrantFiled: April 25, 2023Date of Patent: January 28, 2025Assignee: International Business Machines CorporationInventor: Kangguo Cheng
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Patent number: 12207570Abstract: A phase change memory (PCM) semiconductor device is provided. The PCM semiconductor device includes: a phase change material stack on a substrate, the phase change material stack including at least two phase change material layers each separated by an insulating layer; a first electrode on a first side of the phase change material stack; and a second electrode on a second side of the phase change material stack, wherein a first one of the phase change material layers has a length that is different from a length of a second one of the phase change material layers.Type: GrantFiled: March 16, 2022Date of Patent: January 21, 2025Assignee: International Business Machines CorporationInventors: Ching-Tzu Chen, Juntao Li, Kangguo Cheng, Carl Radens
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Patent number: 12191208Abstract: A dielectric layer is on top of a first semiconductor stack. The first semiconductor stack is compressively strained. A second semiconductor stack is on top of the dielectric layer. The second semiconductor stack is tensely strained.Type: GrantFiled: September 23, 2021Date of Patent: January 7, 2025Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Shogo Mochizuki, Juntao Li
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Patent number: 12183740Abstract: Provided is a stacked field-effect transistor (FET). The stacked FET comprises a top device, a bottom device, and a transition region between the top device and the bottom device. The transition region includes a plurality of inner spacers and a first inter-layer dielectric (ILD). The ILD is formed between each of the plurality of inner spacers. The top and bottom devices have a first channel sheet thickness in a gate region and a second channel sheet thickness between inner spacers. The second channel sheet thickness is larger than both the first channel sheet thickness and the first distance.Type: GrantFiled: June 6, 2022Date of Patent: December 31, 2024Assignee: International Business Machines CorporationInventors: Ruilong Xie, Kangguo Cheng, Curtis S. Durfee, Jay William Strane, Min Gyu Sung, Julien Frougier, Chanro Park
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Patent number: 12176345Abstract: Stacked FET devices having independent and shared gate contacts are provided. In one aspect of the invention, a stacked FET device includes: a bottom-level FET(s) having a bottom-level FET gate; a top-level FET(s) having a top-level FET gate, wherein an upper portion of the bottom-level FET gate is adjacent to the top-level FET gate; a dielectric sidewall spacer in between the upper portion of the bottom-level FET gate and the top-level FET gate; and a dielectric gate cap disposed over the bottom and top-level FET gates that includes a different dielectric material from the dielectric sidewall spacer. A device having at least one first stacked FET device and at least one second stacked FET device, and a method of forming a stacked FET device are also provided.Type: GrantFiled: September 23, 2021Date of Patent: December 24, 2024Assignee: International Business Machines CorporationInventors: Ruilong Xie, Julien Frougier, Kangguo Cheng, Juntao Li, Chanro Park
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Patent number: 12176416Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.Type: GrantFiled: May 26, 2023Date of Patent: December 24, 2024Assignee: International Business Machines CorporationInventors: Lan Yu, Kangguo Cheng, Heng Wu, Chen Zhang
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Publication number: 20240415032Abstract: A phase change memory cell includes a portion of a phase change material over a bi-layer heater where the bi-layer heater has a wider bottom portion on a bottom electrode and a narrower top portion of the bi-layer heater under the phase change material. A first dielectric material is inside and directly contacting the bi-layer heater. The first dielectric material surrounds an air gap in the bottom portion of the first dielectric material. The air gap is adjacent to the wider bottom portion of the bi-layer heater. The narrower top portion of the bi-layer heater is between a sidewall of the first dielectric material and a fourth dielectric material. The fourth dielectric material is above a surface of the bottom portion of the bi-layer heater and contacts a sidewall of a third dielectric material. The phase change memory cell includes a top electrode contacting the phase change material.Type: ApplicationFiled: June 12, 2023Publication date: December 12, 2024Inventors: Kangguo Cheng, Juntao Li, Ruilong Xie, Julien Frougier