# SOFT DECODING FOR FLASH MEMORY

A method of soft decoding received signals. The method comprises defining quantisation intervals for a signal value range, determining a number of bits detected in each quantisation interval, a number of bits in each quantisation interval that are connected to unsatisfied constraints and a probability that the error correction code is unsatisfied, determining an overall bit error rate based on the probability that the error correction code is unsatisfied, determining a log likelihood ratio for each quantisation interval based on the overall bit error rate, the number of bits detected in each quantisation interval and the number of bits in each quantisation interval that are connected to unsatisfied constraints and performing soft decoding using the log likelihood ratios.

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**Description**

**FIELD**

Embodiments described herein relate generally to reading received signal values and in particular to a method of soft decoding received signal values.

**BACKGROUND**

Error-correcting codes (ECC) are often used in communications and storage applications to protect the data against detection/reading errors. Although there are many types of ECC, most of them work better if, as part of their decoding an indication of the level of reliability of the decoding is provided instead of simply a binary decoding decision. In some case, it is possible to compute an indication of decoding reliability based on the system model. However in other cases, the system model is too complicated to allow such computation being performed at all or at least in an efficient manner.

In the following, embodiments will be described with reference to the drawings in which:

**DETAILED DESCRIPTION**

According to an embodiment there is provided a method of soft decoding received signals. The method comprises defining quantisation intervals for a signal value range, determining a number of bits detected in each quantisation interval, a number of bits in each quantisation interval that are connected to unsatisfied constraints and a probability that the error correction code is unsatisfied, determining an overall bit error rate based on the probability that the error correction code is unsatisfied, determining a log likelihood ratio for each quantisation interval based on the overall bit error rate, the number of bits detected in each quantisation interval and the number of bits in each quantisation interval that are connected to unsatisfied constraints and performing soft decoding using the log likelihood ratios.

The signal value range may be a threshold voltage range if the received signals are data read from a memory, for example from flash memory. If the signal is received via a transmission channel the signal value range is the range of signal values that can be received using the modulation scheme of the wireless transmission.

The method may further comprise determining an error in each quantisation interval based on the overall bit error rate and the number of bits in each quantisation interval that are connected to unsatisfied constraints and thereafter determining said log likelihood ratio further using said overall bit error rate.

The method further comprises determining one or more or all of a probability that a constraint is unsatisfied when an associated bit is correct based on said overall bit error rate and a constraint degree of the error correction code, a probability that a constraint is unsatisfied when an associated bit is incorrect based on said overall bit error rate and a constraint degree of the error correction code, a probability that a correct bit is connected to a predetermined number of unsatisfied constraints based on a variable degree of the error correction code, the number of unsatisfied constraints and a probability that a constraint is unsatisfied when an associated bit is correct and a probability that an incorrect bit is connected to a number of unsatisfied constraints based on a variable degree of the error correction code, the number of unsatisfied constraints and a probability that a constraint is unsatisfied when an associated bit is incorrect.

The method further comprises setting said log likelihood ratio to a predetermined value for a or any quantisation interval in which one or more of the number of bits detected is zero or in which an error is determined to be lower or equal to zero.

Said data may be stored using a multicell write once storage technique, wherein said log likelihood ratios are determined for an array, wherein the quantisation intervals for the individual cells used in combination in the multicell write once storage technique individually define dimensions of the array.

The method may further comprise a step of attempting to hard decode said data by repeatedly reading memory cells storing said data with a changing read threshold parameter, said quantisation intervals being defined by said change in the read threshold parameter.

The method may further comprise outputting the soft decoded data from a controller that has performed said soft decoding to an output port or to a connected device.

According to an embodiment there is provided a non-transitory storage medium storing computer program instructions for execution by a processor and that, when executed by a processor, cause the processor to perform any of the above discussed methods.

According to another embodiment there is provided a device for soft decoding received signals comprising a processor and memory storing instructions for execution by the processor. The instruction causing the processor, when executing the instruction to define quantisation intervals for a signal value range, determine a number of bits detected in each quantisation interval, a number of bits in each quantisation interval that are connected to unsatisfied constraints and a probability that the error correction code is unsatisfied, determine an overall bit error rate based on the probability that the error correction code is unsatisfied, determine a log likelihood ratio for each quantisation interval based on the overall bit error rate, the number of bits detected in each quantisation interval and the number of bits in each quantisation interval that are connected to unsatisfied constraints and perform soft decoding using the log likelihood ratios.

The device may be is a flash memory storage device comprising a flash memory controller and a flash memory array. The device may comprise an input/output port for receiving data to be stored in the flash array and/or for outputting decoded data.

The device may be a wireless communications device and may comprise an antenna for receiving the signals and/or an output port for outputting the soft decoded signals to other devices, for example through a wired connection.

The disclosed method provides a way of computing the reliability (also referred to as soft values) of estimated bits in a low-complexity manner. In embodiments the number of unsatisfied constraints of an LDPC code are counted. It is further determined how many bits fall within which quantisation interval. Based on this information the number of bit errors in each quantisation interval are estimated and, on the basis of this estimation, conclusions are drawn on the reliability of an estimated bit.

The method of the embodiment is general and can be used in any application in which the distributions of received signal values overlap so that reliable discrimination between signals is no longer possible. Embodiments presented herein refer to the decoding of information stored in flash memory. In other embodiments information stored in other memory types may be decoded. Embodiments also relate to decoding of signals received in wireless communication systems, as is described with reference to

**100** and non-volatile flash storage memory **110**. The computing device may be a mobile computing device, such as a mobile phone, tablet computer, laptop, camera or any other type of mobile computing device. Alternatively the computing device **100** may be stationary, such as a desktop computer or indeed part of a stationary server or part of a storage bank, such as part of a RAID solution.

The non-volatile flash storage memory **110** may take any form of non-volatile storage device comprising flash memory. The non-volatile flash storage memory **110** may, for example, be a “thumb drive”, a solid-state drive (SSD), a memory card, etc.

The computing device **100** and the non-volatile flash storage memory **110** are in communicative connection with each other in a manner that allows the computing device **100** to transmit data and commands indicating the processing the data is to be subjected to by the non-volatile flash storage memory **110** to the non-volatile flash storage memory **110** and that allows the non-volatile flash storage memory **110** return data retrieved from memory to the computing device **100**. The computing device **100** may also provide power to the non-volatile flash storage memory **110**. A number of interfaces that allow communication between a computing device **100** and a non-volatile flash storage memory **110** are known. The exact nature of the interface is not important. Exemplary interfaces include the USB interface, SD, microSD, xD, Compactflash, MMC, to name but a few.

The non-volatile flash storage memory **110** comprises a memory controller **120** and non-volatile flash memory **130**. The memory controller **120** interfaces with the computing device **100** as well as with the flash memory **130**. The memory controller **120** provides power to the flash memory **130** and is moreover connected to the flash memory **130** via command, control, address and data lines. The memory controller **120** may control all of the operations flash memory **130**.

As shown in **32**-**64** word lines per block; in _{k+1 }and WL_{k }are shown) that connect the gates of horizontally adjacent FETs, and vertically along (often thousands of) bit-lines (BL_{1 }to BL_{n }in

To determine the storage state of a memory cell a bias voltage is applied to the word line connected to the memory cell in question and a separate bias voltage is applied across the memory cell's channel. The gate voltage applied to all other memory cells that are connected to the memory cells that is to be read is such that the other memory cells are fully conducting so that the bias voltage applied along the bitline is applied, to the largest extent possible, across the channel of the memory cell to be read.

**2**^{n }storage distributions (with n being the number of bits stored). The two distributions shown in

The conductivity of the channel of the memory cell to be read is intended to be influenced solely by the amount of charge stored on the memory cell's floating gate and by the bias voltage (indicated as V_{Read }in

To store charges in the floating gate of a memory cell charges are progressively injected into the floating gate using incremental step pulse program (ISPP). The amount of charge stored on the floating gate is monitored (for example using the above discussed sensing technique) to keep track of programming progress. Once it is determined that a charge that is sufficient to render the memory cell conductive for a given threshold voltage has been stored in a floating gate of the memory cell programming is completed.

It is worth noting that programming is a one-way process in a sense that the amount of charge stored on the floating gate cannot selectively be reduced. Instead, once the amount of charge stored in a memory cell exceeds a desired amount all of the charges on the memory cell need to be removed from the floating gate and programming re-started. Such erasure takes place simultaneously for all memory cells in a block of flash memory.

NAND flash memory cells are subject to various types of impairments that affect its performance, such as inaccurate programming, retention noise, random telegraph noise and more importantly inter-cell interference (ICI). It will be appreciated that charges stored on the floating gate generate electric fields that can influence the conductivity of the channel of an adjacent memory cell, thereby interfering with and potentially falsifying perceived memory cell storage state. This is illustrated in _{Read }is chosen it is still possible for programmed memory cells that happen to fall within the leftmost part of the “0” charge distribution to not be able to cause the memory cell to conduct. These memory cells are then incorrectly interpreted as relating to storage state “1”. Conversely it is also possible for an erased memory cells that happen to fall within the rightmost part of the “1” charge distribution to cause the memory cell to conduct during a read operation so that these memory cells are being incorrectly interpreted as relating to storage state “0”. As flash memory architectures continue to be miniaturised the effect electric fields have on adjacent cells becomes more pronounced, thereby increasing ICI.

One way of mitigating the increasing ICI effect is to employ soft-decision error correction codes (ECCs). Towards this purpose, a flash memory controller may start by comparing the threshold voltage against the hard decision boundaries. If sensing of the storage states of memory cells using hard decision boundaries soft decoding may instead be used. Error correction codes to which soft decoding can be applied include a LDPC (low-density parity check) code, aBCH code, a turbo code, an RS (Reed-Solomon code), a convolution code, an RSC (Recursive Systematic Code), or coded modulation such as TCM (Trellis-Coded Modulation), BCM (Block Coded Modulation), and so on. Soft deciding algorithms that can be used include, amongst others, mini-sum algorithms and Viterbi decoding. For soft decoders to work in the best possible way they require knowledge of the reliability of (e.g., log-likelihood ratios (LLRs)) of the read information to be fed to the iterative decoder. As the channel model is not precisely known, it is desirable to have a simple and dynamic LLR estimation algorithm instead of relying on precomputed lookup table that may undermine the performance the soft detection method.

Some flash memory arrays may be configured to perform an initial ‘hard detection’ routine in an attempt to determine the storage states of a group of memory cell by simply distinguishing between the stored states using the above described reading process. Any errors encountered are corrected using error correction codes that have originally been stored with the data that is to be read. In such a hard detection routine the threshold voltage used for distinguishing between two storage states may be changed in subsequent read attempts until a threshold voltage that minimises the total number of errors in the read group of cells is minimised. _{Read }shown in _{Read}. Such alternative threshold voltages are shown as V_{S1}, V_{S2}, V_{S3 }and V_{S4 }in

It will be appreciated that moving the threshold voltage between reads, for example from V_{Read }to V_{S2}, the number of memory cells that have been detected as having one of the storage states, say the number of memory cells detected to be in the left-most storage state (mapped to a binary “1” in _{Read }is used, is higher than the number of memory cells detected to be in this storage state when threshold voltage V_{S2 }s used. Equally, the number of memory cells that have been detected as having the other one of the storage states, in the example the number of memory cells detected to be in the right-most storage state (mapped to a binary “0” in _{Read }is used, is lower than the number of memory cells detected to be in this storage state when threshold voltage V_{S2 }is used. In the following the intervals defined by respective adjacent threshold voltages are referred to as quantisation intervals r. The total number of quantisation intervals will be referred to as L in the following and has to be larger than 2^{n}. Further quantisation intervals are below threshold voltage V_{S1 }and above V_{S4}, so that L=6 in the embodiment illustrated in

ECC decoder soft input information can be provided in the form of log likelihood ratio (LLR) information. The LLR is defined as

where b is the data bit and y is the received (read) value, so, for a given quantisation interval r, that Pr(b =1|y) is the probability of a data bit that has been stored as b=1 being read as a value y=1 and Pr(b=0|y) is the probability of a data bit that has been stored as b=0 being read as a value y=0. If these conditional probabilities can't be explicitly calculated, a measurement-based technique can be used. As disclosed in, for example, Eran Sharon and Alex Bazarsky (Eran Sharon and Alex Bazarsky, “Dynamic memory error model estimation for real and ECC adaptations”, Non-Volatile Memory Workshop, March 2017) it can be shown that the magnitude of the LLR is related to the bit-error rate (BER). In particular for a received value in quantisation interval r, the LLR magnitude is

where P_{r }is the BER for that particular interval. It is therefore desirable to estimate the interval-dependent P_{r}.

Consider a subsection of a regular LDPC code shown in _{r,q }and the number of bits received in quantisation interval r by C_{r}. The expected value of the former can be expressed as:

*E{C*_{r,q}}=(*P*_{q|e}*P*_{r}*+P*_{q|c}(1−*P*_{r}))*C*_{r}=(*P*_{q|e}*−P*_{q|c})*E*_{r}*+P*_{q|c}*C*_{r } (1)

where E_{r }is the number of bit errors in interval r, P_{q|e }and P_{q|c }are the probabilities that a bit is connected to q unsatisfied constraints given that it is wrong and correct, respectively. Assuming independence of bits connected to the same constraint (which roughly holds for high-girth LDPC codes), these probabilities can be expressed as:

where p_{u|e }and p_{u|c }are the probabilities that a constraint is unsatisfied given that a certain bit is wrong and correct, respectively, and d_{v }is the variable degree of the LDPC code. These probabilities are founds as:

where p is the overall (interval-independent) BER and is the constraint degree of the LDPC code. The overall BER is related to the interval-dependent errors by a simple summation:

where N is the total number of bits and L is the number of quantisation intervals. Through the observations Ĉ_{r,q}, Ĉ_{r }and the variable dependencies, we have:

*Ĉ*_{r,q}=(*P*_{q|e}(*E*_{r})−*P*_{q|c}(*E*_{r}))*E*_{r}*+P*_{q|c}(*E*_{r})*Ĉ*_{r } (7)

Determining the errors E_{r}, and hence

is a very complex optimisation task since E_{r }affects the probabilities P^{q|e}. P_{q|c }in a highly non-linear fashion.

In the above calculations, we assumed a regular LDPC code (all variable and constraint nodes have the same degree). If an irregular code is used, the same procedure applies but will then have to be repeated for every type of node degree.

Instead of performing a complicated minimisation, it was found that the errors E_{r }can be found in a much less computationally complex way. The probability that a constraint is unsatisfied can be computed as:

where p is the overall bit error probability. Hence the overall BER can be found directly and the intermediate probabilities p_{u|e}, p_{u|c}, P_{q|e}, P_{q|c }can be computed. The errors E_{r }are then computed using:

*Ĉ*_{r,q}=(*P*_{q|e}*−P*_{q|c})*E*_{r}*+P*_{q|c}*Ĉ*_{r } (9)

A weighted least-squares (WLS) metric is, in one embodiment, used to reflect the fact that there can be significant differences in the number of bits and unsatisfied constraints, Ĉ_{r, q}, which means that errors should have different importance. The WLS problem:

is solved as:

This does not involve any numerical optimisations or complex minimisations.

The complete algorithm is shown in the flow chart in _{r }(the number of bits in quantisation interval r), C_{r,q }(the number of bits received in quantisation interval r that are connected to q unsatisfied constraints) and p_{c }(the probability that a constraint of the LDPC code is unsatisfied, as indicated by the read values and the parity check matrix).

In the subsequent step the probability p that any of the constraints of the LDPC is unsatisfied is calculated using equation (8) above. On the basis of this calculation p_{u|e}, p_{u|c }(the probabilities that a constraint is unsatisfied given that a certain bit is wrong and correct, respectively), P_{q|e }and P_{q|c }(the probabilities that a bit is connected to q unsatisfied constraint given that it is wrong and correct, respectively) are calculated using equations (2) to (5) above.

After initialising index r to a starting value of 1 a processing loop is entered in which the errors E_{r }are calculated in consecutive iterations of the loop using equation (11) above until the quantisation index r (which is incremented in each iteration of the loop) would exceed the total number of quantisation intervals to be considered (r>L?) if the iterations were continued. In each iteration of the loop the LLR magnitude for the currently considered quantisation interval is also calculated using:

This equation includes two fail-safe provisions in that a predetermined value L_{max }is chosen if the results for the calculation of E_{r }erroneously suggests that he error is equal to or smaller than zero (E_{r}≤0) or if C_{r}=0 (no bits were recorded in an interval). The choice of L_{max }may be based on simulations or experience values.

The final LLR for the quantisation interval r is then calculated as L_{r}=(2{circumflex over (b)}−1)|L_{r}| where {circumflex over (b)} is the hard decision on the bit.

The advantage of the embodiment compared to existing methods is that the complexity is significantly reduced. Instead of solving a complex optimisation problem, the embodiment determines intermediate variables directly, thereby avoid costly minimisation steps.

In the following the above discussed LLR technique is extended to multicell write-once memory (WOM) codes that are used in flash memory.

The level of charges stored in flash memory cells can be increased in well-defined ways but a corresponding partial decrease of the stored charges is not possible. Instead during operation the charges in the memory cells are gradually increased until a desired charge amount is reached. If a smaller charge amount is to be stored then all of the charges stored in the cells need to be removed from the cell and the charge amount be increased thereafter until the desired charging state is reached. Charge storage and erasure cycles reduce the lifetime of the memory. To counteract this cell deterioration WOM codes have been designed that allows for multiple writes before the cells need to be erased. One such code for cells configured to store up to data in two memory cells in two write operations is shown in **0** to **3**. To the left of the left-hand column the three bit information stored in the two memory cells in the first write operation is shown.

The lines connecting the storage states illustrated in the left-hand column of

Since this WOM covers two cells, a two-dimensional LLR look-up table is used in the embodiment. Instead of determining L_{r}, as described above, the embodiment determines L_{r}_{1}_{,r}_{2 }where r_{1 }and r_{2 }indicate the quantisation intervals for the two cells. Apart for this, the algorithm is the same as before.

To illustrate the performance of the LLR generation, a flash memory with multilevel cells (MLC) with four storage states (i.e. two bits per cell) and impaired by intercell interference, random telegraph noise (modelled as Laplacian noise, with the variance being a function of the number of P/E cycles) and retention impairment (modelled as Gaussian noise, with the variance also being a function of the number of P/E cycles) was simulated. As each memory cell stores two bits of information the method illustrated in _{v}=3 and constraint degree d_{c}=15 was used. As a comparison, the LLRs generated by Eran Sharon, Alex Bazarsky, “Dynamic memory error model estimation for real and ECC adaptations”, Non-Volatile Memory Workshop, March 2017 with the MSE metric and optimal LLRs, based on offline simulations were used. As can be seen from

_{S1 }to V_{S4 }shown in

The commonly used QAM (Quadrature Amplitude Modulation) uses to separate pulse amplitude modulated symbols that can be decoded independently from each other in the above described manner.

Whilst certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices, and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices, methods and products described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

## Claims

1. A method of soft decoding received signals, the method comprising:

- defining quantisation intervals for a signal value range;

- determining a number of bits detected in each quantisation interval, a number of bits in each quantisation interval that are connected to unsatisfied constraints and a probability that the error correction code is unsatisfied;

- determining an overall bit error rate based on the probability that the error correction code is unsatisfied;

- determining a log likelihood ratio for each quantisation interval based on the overall bit error rate, the number of bits detected in each quantisation interval and the number of bits in each quantisation interval that are connected to unsatisfied constraints; and

- performing soft decoding using the log likelihood ratios.

2. The method of claim 1, further comprising:

- determining an error in each quantisation interval based on the overall bit error rate and the number of bits in each quantisation interval that are connected to unsatisfied constraints; and

- thereafter determining said log likelihood ratio further using said overall bit error rate.

3. The method of claim 1, further comprising:

- determining one or more or all of: a probability that a constraint is unsatisfied when an associated bit is correct based on said overall bit error rate and a constraint degree of the error correction code; a probability that a constraint is unsatisfied when an associated bit is incorrect based on said overall bit error rate and a constraint degree of the error correction code; a probability that a correct bit is connected to a predetermined number of unsatisfied constraints based on a variable degree of the error correction code, the number of unsatisfied constraints and a probability that a constraint is unsatisfied when an associated bit is correct; and a probability that an incorrect bit is connected to a number of unsatisfied constraints based on a variable degree of the error correction code, the number of unsatisfied constraints and a probability that a constraint is unsatisfied when an associated bit is incorrect.

4. The method of claim 1, further comprising setting said log likelihood ratio to a predetermined value for a or any quantisation interval in which one or more of the number of bits detected is zero or in which an error is determined to be lower or equal to zero.

5. The method of claim 1, wherein said data is stored using a multicell write once storage technique, wherein said log likelihood ratios are determined for an array, wherein the quantisation intervals for the individual cells used in combination in the multicell write once storage technique individually define dimensions of the array.

6. The method of claim 1, further comprising a step of attempting to hard decode said data by repeatedly reading memory cells storing said data with a changing read threshold parameter, said quantisation intervals being defined by said change in the read threshold parameter.

7. The method of claim 1, further comprising outputting the soft decoded data from a controller that has performed said soft decoding to an output port or to a connected device.

8. A non-transitory storage medium storing computer program instructions for execution by a processor and that, when executed by a processor, cause the processor to perform the method of claim 1.

9. A device for soft decoding received signals comprising a processor and memory storing instructions for execution by the processor, the instruction causing the processor when executing the instruction to:

- define quantisation intervals for a signal value range;

- determine a number of bits detected in each quantisation interval, a number of bits in each quantisation interval that are connected to unsatisfied constraints and a probability that the error correction code is unsatisfied;

- determine an overall bit error rate based on the probability that the error correction code is unsatisfied;

- determine a log likelihood ratio for each quantisation interval based on the overall bit error rate, the number of bits detected in each quantisation interval and the number of bits in each quantisation interval that are connected to unsatisfied constraints; and

- perform soft decoding using the log likelihood ratios.

10. The device of claim 9, the instruction causing the processor when executing the instruction to:

- determine an error in each quantisation interval based on the overall bit error rate and the number of bits in each quantisation interval that are connected to unsatisfied constraints; and

- thereafter determine said log likelihood ratio further using said overall bit error rate.

11. The device of claim 9, the instruction causing the processor when executing the instruction to:

- determine one or more or all of: a probability that a constraint is unsatisfied when an associated bit is correct based on said overall bit error rate and a constraint degree of the error correction code; a probability that a constraint is unsatisfied when an associated bit is incorrect based on said overall bit error rate and a constraint degree of the error correction code; a probability that a correct bit is connected to a predetermined number of unsatisfied constraints based on a variable degree of the error correction code, the number of unsatisfied constraints and a probability that a constraint is unsatisfied when an associated bit is correct; and a probability that an incorrect bit is connected to a number of unsatisfied constraints based on a variable degree of the error correction code, the number of unsatisfied constraints and a probability that a constraint is unsatisfied when an associated bit is incorrect.

12. The device of claim 9, the instruction causing the processor when executing the instruction to set said log likelihood ratio to a predetermined value for a or any quantisation interval in which one or more of the number of bits detected is zero or in which an error is determined to be lower or equal to zero.

13. The device of claim 9, wherein said data is stored using a multicell write once storage technique, wherein said log likelihood ratios are determined for an array, wherein the quantisation intervals for the individual cells used in combination in the multicell write once storage technique individually define dimensions of the array.

14. The device of claim 9, the instruction causing the processor when executing the instruction to perform a step of attempting to hard decode said data by repeatedly reading memory cells storing said data with a changing read threshold parameter, said quantisation intervals being defined by said change in the read threshold parameter.

15. The device of claim 9, the instruction causing the processor when executing the instruction to output the soft decoded data from a controller that has performed said soft decoding to an output port or to a connected device.

16. The device of claim 9, wherein the device is a flash memory storage device.

17. The device of claim 9, wherein the device is a wireless communications device.

**Patent History**

**Publication number**: 20200177210

**Type:**Application

**Filed**: Nov 30, 2018

**Publication Date**: Jun 4, 2020

**Applicants**: Kabushiki Kaisha Toshiba (Minato-ku), Toshiba Memory Corporation (Minato-ku)

**Inventors**: Magnus Stig Torsten SANDELL (Bristol), Amr Ismail (Bristol)

**Application Number**: 16/205,924

**Classifications**

**International Classification**: H03M 13/45 (20060101); G06F 11/10 (20060101);