Patents Assigned to TOSHIBA MEMORY CORPORATION
  • Publication number: 20220139471
    Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining l0 the first memory cells in the bit line direction.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Tomoharu TANAKA
  • Publication number: 20220130456
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Application
    Filed: January 4, 2022
    Publication date: April 28, 2022
    Applicant: Toshiba Memory Corporation
    Inventors: Tokumasa HARA, Noboru SHIBATA
  • Publication number: 20220130469
    Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.
    Type: Application
    Filed: January 7, 2022
    Publication date: April 28, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Akio SUGAHARA, Takaya HANDA, Ryosuke ISOMURA, Kazuto UEHARA, Junichi SATO, Norichika ASAOKA, Masashi YAMAOKA, Bushnaq SANAD, Yuzuru SHIBAZAKI, Noriyasu KUMAZAKI, Yuri TERADA
  • Publication number: 20220115064
    Abstract: A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 14, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Tokumasa HARA
  • Publication number: 20220115403
    Abstract: A semiconductor memory device includes a plurality of electrode layers stacked above a first semiconductor layer, a second semiconductor layer and a first film. The second semiconductor layer extends through the plurality of electrode layers in a stacking direction of the plurality of electrode layers. The second semiconductor layer includes an end portion inside the first semiconductor layer. The first film is positioned inside the first semiconductor layer and contacts the first semiconductor layer. The first semiconductor layer includes a first portion, a second portion, and a third portion. The first film is positioned between the first portion and the second portion. The third portion links the first portion and the second portion. The third portion is positioned between the first film and the second semiconductor layer. The second semiconductor layer includes a contact portion contacting the third portion of the first semiconductor layer.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki MARUYAMA, Yoshiaki FUKUZUMI, Yuki SUGIURA, Shinya ARAI, Fumie KIKUSHIMA, Keisuke SUDA, Takashi ISHIDA
  • Publication number: 20220108754
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.
    Type: Application
    Filed: December 17, 2021
    Publication date: April 7, 2022
    Applicant: Toshiba Memory Corporation
    Inventor: Masanobu SHIRAKAWA
  • Publication number: 20220107761
    Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks. The controller is electrically coupled to the nonvolatile memory. The controller controls the nonvolatile memory. When receiving, from the host, a first command for changing a state of an allocated block to a reallocatable state in a case where a second command that is yet to be executed or being executed involving read of data from the allocated block has been received from the host, the controller changes the state of the allocated block to the reallocatable state after the second command is finished.
    Type: Application
    Filed: December 17, 2021
    Publication date: April 7, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi KANNO
  • Publication number: 20220101924
    Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.
    Type: Application
    Filed: December 13, 2021
    Publication date: March 31, 2022
    Applicant: Toshiba Memory Corporation
    Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA
  • Publication number: 20220100377
    Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
    Type: Application
    Filed: December 7, 2021
    Publication date: March 31, 2022
    Applicant: Toshiba Memory Corporation
    Inventors: Hiroshi YAO, Shinichi KANNO, Kazuhiro FUKUTOMI
  • Publication number: 20220102262
    Abstract: A semiconductor device includes an insulating layer, a conductive member provided inside the insulating layer, a chip disposed on a first surface of the insulating layer and connected to the conductive member, and an electrode connected to the conductive member via a barrier layer. A resistivity of the barrier layer is higher than a resistivity of the conductive member. At least a portion of the electrode protrudes from a second surface of the insulating layer.
    Type: Application
    Filed: December 8, 2021
    Publication date: March 31, 2022
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki TAJIMA, Kazuo SHIMOKAWA
  • Publication number: 20220093643
    Abstract: A semiconductor memory device according to an embodiment includes a substrate, first and second conductive layers, first and second pillars, and a first member. The first conductive layer includes a first portion, a second portion, and a third portion above the second portion. The second conductive layers are stacked above the first conductive layer. The first pillar includes a first semiconductor layer in contact with the first portion in a direction crossing the stacked direction. The second pillar is provided to penetrate the second conductive layers and the third portion in the stacked direction. The first member is provided between the first and second pillars and between the second and third portions.
    Type: Application
    Filed: December 3, 2021
    Publication date: March 24, 2022
    Applicant: Toshiba Memory Corporation
    Inventors: Manabu SAKAMOTO, Kenji TASHIRO, Takamasa ITO
  • Publication number: 20220083278
    Abstract: According to one embodiment, a storage system performs a first allocation operation of allocating, for a first namespace, a plurality of first blocks included in the blocks of a nonvolatile memory. The storage system performs a read operation, a write operation or an erase operation on one of the first blocks in response to a command received from a host to read, write or erase the one first block, counts the total number of erase operations performed on the first blocks, and notifies the host of the counted number of erase operations in response to a command received from the host to obtain an erase count associated with the first namespace.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 17, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi KANNO
  • Publication number: 20220083442
    Abstract: Example implementations include a method of receiving a host command identifier associated with a host command, determining a device command associated with the host command and a memory controller device, receiving a device command timestamp corresponding to a time of the determining the device command, and determining a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp.
    Type: Application
    Filed: September 16, 2020
    Publication date: March 17, 2022
    Applicant: Toshiba Memory Corporation
    Inventors: Paul Edward HANHAM, Shigehiro ASANO, Julien MARGETTS
  • Publication number: 20220083497
    Abstract: A system for reading stored data may include one or more Ethernet drives and a controller, both configured to communicatively connect to a host device. The controller may receive a first read command from the host device, determine a first drive among the one or more Ethernet drives using the first read command and a mapping table, translate the first read command into a second read command, and send the second read command to the first drive. Responsive to receiving the second read command, the first drive may send a first remote data transfer instruction to the host device independent of the controller. The first remote data transfer instruction may include stored data read from the first drive to cause the host device to write the stored data read from the first drive to one or more memory buffers in the host device indicated by the second read command.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 17, 2022
    Applicant: Toshiba Memory Corporation
    Inventor: Yaron KLEIN
  • Publication number: 20220084846
    Abstract: A semiconductor manufacturing apparatus includes a mounting unit arranged to mount an annular member, having an annular shape, to a work substrate including a first substrate and a second substrate bonded to each other so that the annular member surrounds the first substrate. The apparatus further includes a holding unit arranged to hold the work substrate having the annular member mounted thereto. The apparatus further includes a first fluid supply unit arranged to supply a first fluid to the second substrate of the work substrate held by the holding unit.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 17, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Hidekazu HAYASHI
  • Publication number: 20220077175
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second memory cells; a first and second word lines; and a first bit line. The device is configured to execute first to sixth operations. In the first operation, a first voltage is applied to the first word line and a second voltage is applied to a semiconductor layer. In the second operation, the first voltage is applied to the second word line. In the third operation, a third voltage is applied to the first word line. In the fourth operation, the third voltage is applied to the second word line. In the fifth operation, a fourth voltage is applied to the first word line. In the sixth operation, the fourth voltage is applied to the second word line.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Takuya FUTATSUYAMA
  • Publication number: 20220075548
    Abstract: Various implementations described herein relate to systems and methods for managing selective erasure in a Solid-State Drive (SSD) including receiving a selective erase command corresponding to erasing valid and invalid data mapped to a logical address and in response to receiving the selective erase command, erasing blocks in which one or more pages mapped to the logical address are located based on a mapping table that maps the logical address to the one or more pages. Both valid data and invalid data may be physically stored in one or more pages.
    Type: Application
    Filed: November 15, 2021
    Publication date: March 10, 2022
    Applicant: Toshiba Memory Corporation
    Inventor: Yaron Klein
  • Publication number: 20220075686
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yuta KUMANO, Hironori UCHIKAWA, Kosuke MORINAGA, Naoaki KOKUBUN, Masahiro KIYOOKA, Yoshiki NOTANI, Kenji SAKURADA, Daiki WATANABE
  • Patent number: 11270765
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: March 8, 2022
    Assignee: Toshiba Memory Corporation
    Inventors: Tokumasa Hara, Noboru Shibata
  • Patent number: RE48983
    Abstract: A memory device includes a memory which has memory areas, and a controller has a first mode and a second mode. Upon receipt of write data, the controller writes data in the memory areas while managing correspondence between logical addresses of write data and memory areas which store corresponding write data. A plurality of the memory areas constitutes a management unit. The controller in the first mode is able to write pieces of data in respective memory areas and configured to maintain data in memory areas in one management unit which contains data to be updated. The controller in the second mode writes pieces of data in respective memory areas in the ascending order of logical addresses of the pieces of data and invalidates data in memory areas in one management unit which contains updated data.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: March 22, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akihisa Fujimoto