Abstract: According to one embodiment, a semiconductor memory device includes a memory, a controller, and a sense amplifier. The memory includes a plurality of memory cells, wherein each of the memory cells can store a multi level indicating one data. The controller writes the multi level to one cell of the memory. The sense amplifier performs unary read of data from the multi level written in the one cell. The data is data in which an error of a predetermined lower significant bit is allowed. The controller reads data indicated by the multi level stored in the one cell of the memory from the sense amplifier.

Abstract: A semiconductor memory device includes a substrate, a controller, a semiconductor memory component, first and second capacitors, and a jumper element. The substrate has a conductor pattern. The conductor pattern includes a first conductor portion and a second conductor portion. The first conductor portion overlaps at least a part of the first capacitor in a thickness direction of the substrate and is electrically connected to the first capacitor. The second conductor portion overlaps at least a part of the second capacitor in the thickness direction of the substrate and is electrically connected to the second capacitor. The first conductor portion and the second conductor portion are separated from each other, and are electrically connected to each other by the jumper element.

Abstract: A resistance-change type memory device includes a substrate, a plurality of electrodes arranged in a first direction parallel to an upper surface of the substrate and extending in a second direction intersecting the upper surface, a resistance-change film provided in a third direction that is parallel to the upper surface and intersects the first direction as viewed from the plurality of electrodes, a semiconductor film provided between the plurality of electrodes and the resistance-change film, and an insulating film provided between the plurality of electrodes and the semiconductor film. The resistance-change film has a resistance value that changes when a current flows therein.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.

Abstract: According to one embodiment, a storage system includes a controller. The controller receives, from a host, a write command including a block address indicating a first block in a plurality of blocks, and a page address indicating a first page of the first block. The controller writes data designated by the write command to the first page of the first block. The controller notifies the host 2 of a page address indicating a latest readable page which is included in pages of the first block, the pages containing data which was written by the host before the designated data was written to the first page, the latest readable page having become readable by writing the designated data to the first page.

Abstract: A semiconductor storage device includes a substrate, a plurality of first gate electrodes on the substrate and arranged in a thickness direction of the substrate, and a first semiconductor pillar extending in the thickness direction of the substrate through the plurality of first gate electrodes, the first semiconductor pillar including a first portion facing the plurality of first gate electrodes and a second portion farther from the substrate than the first portion. The semiconductor storage device also includes a second gate electrode on the substrate farther from the substrate than the plurality of first gate electrodes, and a second semiconductor pillar extending in the thickness direction of the substrate through the second gate electrode, and connected to the first semiconductor pillar at the second portion of the first semiconductor pillar. The second portion of the first semiconductor pillar contains carbon (C).

Abstract: According to one embodiment, a communication control device includes processing circuitry. The processing circuitry acquires at least either; wired communication characteristic information or wireless communication characteristic information from relaying devices or, storage characteristic information indicating usage of a plurality of storage devices storing data units that are transferred via the relaying devices and sent or received by a terminal in the wireless network or, data characteristic information indicating states of a plurality of data units stored in each of the storage devices. The processing circuitry is configured to receive a data acquisition request or a data saving request sent from the terminal and specify a relaying device or a storage device that processes the data acquisition request or the data saving request, and sends an instruction to the terminal, instructing to transmit the data acquisition request or the data saving request to the specified relaying device or the storage device.

Abstract: A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.

Abstract: A magnetoresistive element according to an embodiment includes: a first layer; a first magnetic layer; a second magnetic layer disposed between the first layer and the first magnetic layer; a nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; and an insulating layer disposed at least on side surfaces of the nonmagnetic layer, the first layer including: at least one element selected from a first group consisting of Hf, Zr, Al, Cr, and Mg; and at least one element selected from a second group consisting of Ta, W, Mo, Nb, Si, Ge, Be, Li, Sn, Sb, and P, and the insulating layer including at least one element selected from the first group.

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

Abstract: According to one embodiment, an apparatus is capable of exchanging a frame with an external apparatus in a packet mode of serial attached small computer system interface (SAS). The apparatus includes a controller configured to transmit a frame to the external apparatus, and to transmit a PACKET_SYNC extended binary primitive to the external apparatus when the frame is not correctly received by the external apparatus.

Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including first and second magnetic layers having variable and fixed magnetization directions, respectively, and a nonmagnetic layer provided between the first and second magnetic layers and containing a first compound containing first cationic and anionic elements, and a predetermined-material layer provided around side surfaces of the stacked structure and containing a second compound containing second added cationic and second added anionic elements. An absolute value of a valence number (ionic valency) of the second added cationic element is less than that of the first cationic element, and an absolute value of a valence number (ionic valency) of the second added anionic element is less than that of the first anionic element.

Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.

Abstract: According to one embodiment, a semiconductor device of an embodiment includes a substrate, a metal plate having a main portion having a first width in a first direction and a second width in a second direction orthogonal to the first direction, a first semiconductor chip located between the metal plate and the substrate, the first semiconductor chip having a third width in the first direction and a fourth width in the second direction, and a second semiconductor chip located between the first semiconductor chip and the substrate, wherein the first width is smaller than the third width, and the second width is smaller than the fourth width.

Abstract: A solid state drive (SSD) with improved techniques for testing power loss protection (PLP) capacitors and a method for testing PLP capacitors of SSDs is disclosed. In one embodiment, the SSD includes a memory controller and one or more non-volatile memory devices and a volatile memory device coupled to the memory controller. The SSD also includes a PLP capacitor configured to supply a first voltage to the memory controller, the one or more non-volatile memory devices, and the volatile memory device in the event of a power loss or failure of the SSD. In one embodiment, the PLP capacitor is further configured to increase the first voltage to a second voltage prior to testing the PLP capacitor. In another embodiment, the memory controller is configured to reduce a volume of data stored in the volatile memory device prior to testing the PLP capacitor.

Abstract: According to one embodiment, a semiconductor storage device includes: a first memory cell and a second memory cell, each including a switching element and a resistance change element coupled to the switching element, and the first memory cell and the second memory cell being adjacent to each other; a non-active member having a switching function between the switching element of the first memory cell and the switching element of the second memory cell; and an insulator which covers at least one of an upper surface or a lower surface of the non-active member, a side surface of the non-active member, a side surface of the switching element of the first memory cell, and a side surface of the switching element of the second memory cell.

Abstract: According to one embodiment, a semiconductor device includes a device region covered with a resin film and a dicing region extending along at least one side of the device region, the dicing region including at least a first lithography mark and a second lithography mark. The resin film includes a first dicing region portion which covers a portion of the dicing region between the first lithography mark and the second lithography mark.

Abstract: A semiconductor device includes a stacked body including conductive layers and first insulating layers which are alternately stacked. The stacked body includes, on at least one side thereof, a staircase portion having stairs formed from the conductive layers and the first insulating layers. A second insulating layer different in material from the first insulating layer is provided on an upper surface of the first insulating layer of the staircase portion. The second insulating layer is away from the conductive layer on the same first insulating layer. A third insulating layer is provided on the staircase portion. Contacts are provided in the first, second, and third insulating layers situated in the respective stairs of the staircase portion. The contacts lead from an upper surface of the third insulating layer to the conductive layer under the first insulating layer.

Abstract: A memory system includes a semiconductor memory including memory cells and a memory controller configured to perform a first tracking process to determine a first voltage, and to read data using the first voltage in a read process after the first tracking process. In the first tracking process, the memory controller is configured to read only first, second, and third data respectively using a second, third, and fourth voltage, determine a number of first memory cells based on the first and second data, determine a number of second memory cells based on the second and third data, and determine the first voltage, based on the number of first and second memory cells.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.