Patents Assigned to TOSHIBA MEMORY CORPORATION
  • Patent number: 11031928
    Abstract: A semiconductor integrated circuit includes a first signal transmission path and a second signal transmission path in parallel with each other, a first variable delay circuit provided on the first signal transmission path and configured to cause a first signal to be delayed by a first delay amount, a duty adjustment circuit provided on the first signal transmission path in series with the first variable delay circuit, and a second variable delay circuit provided on the second signal transmission path and configured to cause a second signal to be delayed by a second delay amount. The first delay amount is smaller than the second delay amount by a third delay amount corresponding to an amount of delay applied to the first signal by the duty adjustment circuit.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: June 8, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takanobu Muraguchi
  • Patent number: 11031474
    Abstract: A semiconductor device is provided with: a substrate; a first region provided above the substrate; a second region provided away from the first region in a first direction; a third region provided between the first region and the second region, the third region facing an electrode portion; a fourth region provided between the first region and the third region; and a fifth region provided between the second region and the third region. The fourth and fifth regions include carbon (C). Carbon concentrations in the first and second regions are lower than carbon concentrations in the fourth and fifth regions.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 8, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshiyuki Kondo
  • Patent number: 11030043
    Abstract: An error correction circuit includes a syndrome calculator to calculate syndrome information of input data, an error position calculator to calculate error position information of the input data, a holder to hold the syndrome information or the error position information at a predetermined timing, an input switch to select one of error-corrected data of the input data, and the input data, and to input the selected data to the syndrome calculator, an error detection determiner to determine whether an error of the input data has been correctly detected, and an error corrector to correct the error of the input data based on information held by the holder and to output error-corrected input data when it is determined by the error detection determiner that the error has been correctly detected whereas to output the input data with no error correction when it is determined by the error detection determiner.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: June 8, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kosuke Hatsuda
  • Patent number: 11031306
    Abstract: According to one embodiment, a quality control method of a position measurement light source includes irradiating light of the position measurement light source on a plurality of marks having different heights and measuring a relationship between the height of the mark and an intensity of light reflected by the mark. The quality control method includes identifying a wavelength of the position measurement light source by comparing measurement data acquired by the measuring to reference data of a relationship between the height of the mark and an intensity of reflected light for each of a plurality of wavelengths.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 8, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Miki Toshima, Sadatoshi Murakami
  • Patent number: 11031416
    Abstract: According to one embodiment, a semiconductor storage device includes: a first stacked body in which a plurality of conductive layers are stacked via a first insulating layer, the first stacked body having a first stepped portion and a second stepped portion in which end portions of the plurality of conductive layers are formed in a step shape in a lower layer; a second stacked body in which a plurality of second insulating layers are stacked via a third insulating layer, the second stacked body having a third stepped portion in which end portions of the plurality of second insulating layers in an identical level as the conductive layers forming the first stepped portion are formed in a step shape. The first stepped portion and the third stepped portion oppose each other, and the second stepped portion and the third stepped portion overlap each other at least partially in a top view.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: June 8, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Maki Miyazaki
  • Patent number: 11029859
    Abstract: A memory system includes a memory controller having a bank command scheduler implemented in a hardware logic block and a power budget controller including a power budget register and a credit register. The hardware logic block is able to determine a command in a queue to be transmitted to a memory bank over a channel, estimate a power consumption value for the command, and query the power budget controller to determine if the power consumption value is within a threshold. If the power consumption value is within the threshold, the hardware logic block receives a grant response from the power budget controller, adds the power consumption value to the credit register value, transmits the command over the channel, and transmits a signal to the power budget controller indicating that the command has been executed and that the power consumption value should be subtracted from the credit register value.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: June 8, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Julien Margetts, Hyoun Kwon Jeong, Jonghyeon Kim
  • Patent number: 11031415
    Abstract: According to one embodiment, in a semiconductor storage device, a peripheral circuit supplies a first voltage to a second region when supplying a select potential to a region corresponding to the second region, in a second conductive layer. The peripheral circuit supplies a second voltage higher than the first voltage to a first region when supplying a select potential to a region corresponding to the first region, in the second conductive layer.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: June 8, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoichi Minemura, Michiaki Matsuo, Reiko Shamoto
  • Patent number: 11030353
    Abstract: In one embodiment, a guide layout creating apparatus includes a selection module that selects a first point as a point on which a guide to array a plurality of particles in a first array is arranged. The apparatus further includes a calculation module that calculates first free energy when the plurality of particles are arrayed in the first array by the guide arranged on the first point, and second free energy when the plurality of particles are arrayed in a second array by the guide arranged on the first point, a type of the second array being different from a type of the first array. The apparatus further includes a determination module that determines whether the first point is employed as the point on which the guide is arranged on the basis of the first free energy and the second free energy.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: June 8, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hironobu Sato
  • Publication number: 20210165713
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Masamichi FUJIWARA, Kazumasa YAMAMOTO, Naoaki KOKUBUN, Tatsuro HITOMI, Hironori UCHIKAWA
  • Publication number: 20210165571
    Abstract: According to one embodiment, when data is to be written to a first physical storage location that is designated by a first physical address, a memory system encrypts the data with the first physical address and a first encryption key, and writes the encrypted data to the first physical storage location. When the encrypted data is to be copied to a second physical storage location, the memory system decrypts the encrypted data with the first physical address and the first encryption key, and re-encrypts the decrypted data with a second encryption key and a copy destination physical address indicative of the second physical storage location.
    Type: Application
    Filed: January 21, 2021
    Publication date: June 3, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi KANNO
  • Publication number: 20210166755
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Application
    Filed: January 21, 2021
    Publication date: June 3, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Tokumasa HARA, Noboru SHIBATA
  • Publication number: 20210167085
    Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.
    Type: Application
    Filed: February 4, 2021
    Publication date: June 3, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takanobu ONO, Yusuke DOHMAE
  • Publication number: 20210167279
    Abstract: A magnetoresistive-effect element includes a first ferromagnet, a first layer on the first ferromagnet and a first layer comprising magnesium oxide, a second ferromagnet on the first layer, a metal layer above the second ferromagnet and a second layer on the metal layer. The second layer and the magnesium oxide have a selected ratio larger than 1 to etching by ion beams.
    Type: Application
    Filed: February 11, 2021
    Publication date: June 3, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Shuichi MURAKAMI
  • Publication number: 20210167176
    Abstract: An integrated circuit device of an embodiment includes a substrate, a first transistor, an insulation layer, a first contact, a second contact, and a first single crystal portion. The first transistor includes a first gate electrode, and a first drain region, and wherein the first source region and the first drain region are disposed in the substrate. The first contact faces the first gate electrode. The second contact faces a first region that is first one of the first source region and the first drain region. The first single crystal portion is disposed on the first region and convex from a surface of the first region, and is located between the first region and the second contact.
    Type: Application
    Filed: March 12, 2019
    Publication date: June 3, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoya INDEN, Katsuyuki KITAMOTO
  • Publication number: 20210166744
    Abstract: A semiconductor memory device according to an embodiment includes: a row decoder and a memory cell array including a first block. The first block includes: a first region, a second region adjacent to the first region in the first direction, and a third region configured to connect the first region and the second region- The memory cell array further includes: a first insulating layer buried in a first trench between the first region and the second region and in contact with the third region; a first contact plug provided in the first insulating layer and electrically connected to the row decoder; and a first interconnect configured to connect a selection gate line and the first contact plug.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Applicant: Toshiba Memory Corporation
    Inventor: Takuya FUTATSUYAMA
  • Patent number: 11023136
    Abstract: A storage device includes a non-volatile memory including a buffer of a first size and a controller. The controller is configured to transmit a control command to the non-volatile memory, and then repeat a process including a first process of changing a phase value of a timing signal indicating timing to read or write data from or to the non-volatile memory and a second process of reading or writing data having a second size smaller than the first size from or to the non-volatile memory in synchronization with the timing signal of the changed phase value, a certain plurality of times without transmitting any other control command to the non-volatile memory during repetition of the process.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: June 1, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hirotaka Higashi
  • Patent number: 11023371
    Abstract: According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: June 1, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11024375
    Abstract: According to one embodiment, there is provided a semiconductor storage device including N word lines, M bit lines, multiple memory cells, and a read circuit. N is an integer of four or greater. M is an integer of two or greater. The M bit lines intersect with the word lines. The multiple memory cells are placed at positions where the word lines and the bit lines intersect. The memory cell stores binary data. The read circuit is connected to the M bit lines. The read circuit is able to detect levels of a multi-ary signal.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 1, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Takeshi Sugimoto
  • Patent number: 11023132
    Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: June 1, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tetsuya Sunata, Daisuke Iwai, Kenichiro Yoshii
  • Patent number: 11023370
    Abstract: A memory system includes a non-volatile memory having a plurality of memory chips, a plurality of switches provided for each of the memory chips for switching on and off supply of power to the corresponding memory chip, and a memory controller configured to control the switches and data access to the non-volatile memory. The memory controller is further configured to determine whether there is a first memory chip among the plurality of memory chips that has no data item stored therein with an elapsed time from a most recent access thereof that is less than a threshold value, and if so, turn off the supply of power to the first memory chip while maintaining the supply of power to the plurality of memory chips other than the first memory chip.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: June 1, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Ryo Takeuchi