Patents Assigned to TOSHIBA MEMORY CORPORATION
  • Patent number: 12027380
    Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a substrate holder configured to hold a plurality of substrates such that the substrates are arranged in parallel to each other. The apparatus further includes a fluid injector including a plurality of openings that inject fluid to areas in which distances from surfaces of the substrates are within distances between centers of the substrates adjacent to each other, the fluid injector being configured to change injection directions of the fluid injected from the openings in planes that are parallel to the surfaces of the substrates by self-oscillation.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: July 2, 2024
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomohiko Sugita, Katsuhiro Sato, Hiroaki Ashidate
  • Patent number: 11847350
    Abstract: According to one embodiment, a storage system performs a first allocation operation of allocating, for a first namespace, a plurality of first blocks included in the blocks of a nonvolatile memory. The storage system performs a read operation, a write operation or an erase operation on one of the first blocks in response to a command received from a host to read, write or erase the one first block, counts the total number of erase operations performed on the first blocks, and notifies the host of the counted number of erase operations in response to a command received from the host to obtain an erase count associated with the first namespace.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: December 19, 2023
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Kanno
  • Publication number: 20220139471
    Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining l0 the first memory cells in the bit line direction.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Tomoharu TANAKA
  • Publication number: 20220130469
    Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.
    Type: Application
    Filed: January 7, 2022
    Publication date: April 28, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Akio SUGAHARA, Takaya HANDA, Ryosuke ISOMURA, Kazuto UEHARA, Junichi SATO, Norichika ASAOKA, Masashi YAMAOKA, Bushnaq SANAD, Yuzuru SHIBAZAKI, Noriyasu KUMAZAKI, Yuri TERADA
  • Publication number: 20220115403
    Abstract: A semiconductor memory device includes a plurality of electrode layers stacked above a first semiconductor layer, a second semiconductor layer and a first film. The second semiconductor layer extends through the plurality of electrode layers in a stacking direction of the plurality of electrode layers. The second semiconductor layer includes an end portion inside the first semiconductor layer. The first film is positioned inside the first semiconductor layer and contacts the first semiconductor layer. The first semiconductor layer includes a first portion, a second portion, and a third portion. The first film is positioned between the first portion and the second portion. The third portion links the first portion and the second portion. The third portion is positioned between the first film and the second semiconductor layer. The second semiconductor layer includes a contact portion contacting the third portion of the first semiconductor layer.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki MARUYAMA, Yoshiaki FUKUZUMI, Yuki SUGIURA, Shinya ARAI, Fumie KIKUSHIMA, Keisuke SUDA, Takashi ISHIDA
  • Publication number: 20220115064
    Abstract: A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 14, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru SHIBATA, Tokumasa HARA
  • Publication number: 20220107761
    Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks. The controller is electrically coupled to the nonvolatile memory. The controller controls the nonvolatile memory. When receiving, from the host, a first command for changing a state of an allocated block to a reallocatable state in a case where a second command that is yet to be executed or being executed involving read of data from the allocated block has been received from the host, the controller changes the state of the allocated block to the reallocatable state after the second command is finished.
    Type: Application
    Filed: December 17, 2021
    Publication date: April 7, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi KANNO
  • Publication number: 20220102262
    Abstract: A semiconductor device includes an insulating layer, a conductive member provided inside the insulating layer, a chip disposed on a first surface of the insulating layer and connected to the conductive member, and an electrode connected to the conductive member via a barrier layer. A resistivity of the barrier layer is higher than a resistivity of the conductive member. At least a portion of the electrode protrudes from a second surface of the insulating layer.
    Type: Application
    Filed: December 8, 2021
    Publication date: March 31, 2022
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki TAJIMA, Kazuo SHIMOKAWA
  • Publication number: 20220083278
    Abstract: According to one embodiment, a storage system performs a first allocation operation of allocating, for a first namespace, a plurality of first blocks included in the blocks of a nonvolatile memory. The storage system performs a read operation, a write operation or an erase operation on one of the first blocks in response to a command received from a host to read, write or erase the one first block, counts the total number of erase operations performed on the first blocks, and notifies the host of the counted number of erase operations in response to a command received from the host to obtain an erase count associated with the first namespace.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 17, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi KANNO
  • Publication number: 20220084846
    Abstract: A semiconductor manufacturing apparatus includes a mounting unit arranged to mount an annular member, having an annular shape, to a work substrate including a first substrate and a second substrate bonded to each other so that the annular member surrounds the first substrate. The apparatus further includes a holding unit arranged to hold the work substrate having the annular member mounted thereto. The apparatus further includes a first fluid supply unit arranged to supply a first fluid to the second substrate of the work substrate held by the holding unit.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 17, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Hidekazu HAYASHI
  • Publication number: 20220075686
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yuta KUMANO, Hironori UCHIKAWA, Kosuke MORINAGA, Naoaki KOKUBUN, Masahiro KIYOOKA, Yoshiki NOTANI, Kenji SAKURADA, Daiki WATANABE
  • Publication number: 20220077175
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second memory cells; a first and second word lines; and a first bit line. The device is configured to execute first to sixth operations. In the first operation, a first voltage is applied to the first word line and a second voltage is applied to a semiconductor layer. In the second operation, the first voltage is applied to the second word line. In the third operation, a third voltage is applied to the first word line. In the fourth operation, the third voltage is applied to the second word line. In the fifth operation, a fourth voltage is applied to the first word line. In the sixth operation, the fourth voltage is applied to the second word line.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Takuya FUTATSUYAMA
  • Patent number: 11260497
    Abstract: A polishing apparatus includes a holder holding a target. A polisher polishes the target. An irradiator irradiates the target with an irradiation light from below the polisher. A photoreceiver receives a reflection light reflected from the polishing target to detect a relation between a wavelength and a light quantity of the reflection light. A first reflector bends the irradiation light from the irradiator in a direction tilted to the polishing target. A second reflector bends the reflection light from the polishing target to the photoreceiver. The first reflector irradiates the polishing target with the irradiation light in a direction tilted to the polishing target.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: March 1, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takashi Watanabe
  • Patent number: 11257551
    Abstract: A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: February 22, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akio Sugahara, Takaya Handa, Ryosuke Isomura, Kazuto Uehara, Junichi Sato, Norichika Asaoka, Masashi Yamaoka, Bushnaq Sanad, Yuzuru Shibazaki, Noriyasu Kumazaki, Yuri Terada
  • Patent number: 11256947
    Abstract: According to one embodiment, an image data of a measurement object including a pattern is acquired. First data is acquired by extracting a contour of an element in composition of the pattern from the image data. Second data that specifies a design data of the measurement object and the pattern of the measurement object is acquired. The design data includes a pattern data. A measurement pattern is extracted by using the first data and the second data. An evaluation value for the measurement pattern with respect to the design data is calculated based on the difference between the measurement pattern and the design data.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: February 22, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Mitsuyo Asano
  • Publication number: 20220049036
    Abstract: According to one embodiment, a polymer material is disclosed. The polymer material contains a polymer. The polymer contains a first monomer unit having a lone pair and an aromatic ring at a side chain, and a second monomer unit including a crosslinking group at a terminal of the side chain, with its molar ratio of 0.5 mol % to 10 mol % to all monomer units in the polymer. The polymer material can be used for manufacturing a composite film as a mask pattern for processing a target film on a substrate. The composite film can be formed by a process including, forming an organic film on the target film with the polymer material, patterning the organic film, and forming the composite film by impregnating a metal compound into the patterned organic film.
    Type: Application
    Filed: October 29, 2021
    Publication date: February 17, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Koji ASAKAWA, Norikatsu SASAO, Shinobu SUGIMURA
  • Patent number: 11251193
    Abstract: A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 15, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ken Komiya, Takashi Ishida, Hiroshi Kanno
  • Publication number: 20220044987
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Application
    Filed: November 19, 2020
    Publication date: February 10, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Isao OZAWA
  • Patent number: 11243719
    Abstract: According to one embodiment, a storage device includes a non-volatile memory, an interface circuit, a first control circuit, a wireless transmitting and receiving circuit, and a second control circuit. The interface circuit is electrically connected to the host device and is capable of communicating the host device. The first control circuit performs control of writing write data received from the host device via the interface circuit into the non-volatile memory. The wireless transmitting and receiving circuit is capable of wirelessly communicating with a wireless device. The second control circuit determines whether or not the write data include a predetermined type of data based on measurement data of the write data, and stops wireless communication performed by the wireless transmitting and receiving circuit if it is determined that the write data include the predetermined type of data.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: February 8, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kuniaki Ito
  • Patent number: RE48983
    Abstract: A memory device includes a memory which has memory areas, and a controller has a first mode and a second mode. Upon receipt of write data, the controller writes data in the memory areas while managing correspondence between logical addresses of write data and memory areas which store corresponding write data. A plurality of the memory areas constitutes a management unit. The controller in the first mode is able to write pieces of data in respective memory areas and configured to maintain data in memory areas in one management unit which contains data to be updated. The controller in the second mode writes pieces of data in respective memory areas in the ascending order of logical addresses of the pieces of data and invalidates data in memory areas in one management unit which contains updated data.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: March 22, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akihisa Fujimoto