Patents Assigned to TOSHIBA MEMORY CORPORATION
  • Publication number: 20190181150
    Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.
    Type: Application
    Filed: February 5, 2019
    Publication date: June 13, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Wataru SAKAMOTO, Ryota SUZUKI, Tatsuya OKAMOTO, Tatsuya KATO, Fumitaka ARAI
  • Publication number: 20190181151
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.
    Type: Application
    Filed: February 14, 2019
    Publication date: June 13, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Wataru Sakamoto, Fumitaka Arai
  • Publication number: 20190180816
    Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.
    Type: Application
    Filed: February 13, 2019
    Publication date: June 13, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroyuki NAGASHIMA, Hirofumi INOUE
  • Publication number: 20190179745
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Application
    Filed: January 23, 2019
    Publication date: June 13, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
  • Publication number: 20190180819
    Abstract: A semiconductor memory device includes a substrate, a controller, a semiconductor memory component, first and second capacitors, and a jumper element. The substrate has a conductor pattern. The conductor pattern includes a first conductor portion and a second conductor portion. The first conductor portion overlaps at least a part of the first capacitor in a thickness direction of the substrate and is electrically connected to the first capacitor. The second conductor portion overlaps at least a part of the second capacitor in the thickness direction of the substrate and is electrically connected to the second capacitor. The first conductor portion and the second conductor portion are separated from each other, and are electrically connected to each other by the jumper element.
    Type: Application
    Filed: August 13, 2018
    Publication date: June 13, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi YAMASAKI, Shinichi Kikuchi
  • Publication number: 20190180827
    Abstract: According to one embodiment, a voltage generation circuit includes a first boost circuit, a voltage division circuit, a first detection circuit, capacitor and a first switch. The first boost circuit outputs a first voltage. The voltage division circuit divides the first voltage. The first detection circuit is configured to detect a first monitor voltage supplied to the first input terminal, based on a reference voltage which is supplied to a second input terminal of the first detection circuit, and to control an operation of the first boost circuit. The capacitor is connected between an output terminal of the first boost circuit and the first input terminal of the first detection circuit. The first switch cuts off a connection between the capacitor and the first detection circuit, based on an output signal of the first detection circuit, until the first voltage is output from the first boost circuit.
    Type: Application
    Filed: February 12, 2019
    Publication date: June 13, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuro MIDORIKAWA, Masami MASUDA
  • Patent number: 10320429
    Abstract: According to the embodiment, a memory controller includes a memory interface which performs a first reading using a read voltage including a hard decision voltage and a second reading using a plurality of read voltages within a predetermined voltage range, a shift value calculation unit which calculates an update value of the hard decision voltage based on the reading result by the second reading, a storage unit which stores the update value, a decoding unit which performs decoding based on likelihood information according to the reading result, and a controller which makes the memory controller perform the first reading, makes the decoding unit perform the decoding by using the likelihood information using a reading result by the second reading when the decoding has been failed, and makes the memory controller perform the first reading by using the update value when the corresponding update value is stored in the storage unit.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: June 11, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Kenji Sakurada
  • Patent number: 10319730
    Abstract: A memory device according to an embodiment includes: a stacked film having a plurality of semiconductor films, and a plurality of insulating films each provided between the semiconductor films; a first electrode provided above the stacked film; a second electrode provided above the stacked film; a plurality of first conductive pillars penetrating through the stacked film and having one end electrically connected to the first electrode and another end not connected and positioned below the stacked film; a plurality of memory cells each provided between each of the first conductive pillars and each of the semiconductor films; a plurality of second conductive pillars electrically connected to each of the semiconductor films and the second electrode; a peripheral circuit board provided above the first electrode and the second electrode; a third electrode provided between the first electrode and the peripheral circuit board, the third electrode electrically connected to the first electrode; a fourth electrode prov
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: June 11, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kouji Matsuo
  • Patent number: 10319734
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a second air gap, a first insulating film, a semiconductor film, and a stacked film. The stacked body is provided above the substrate and includes a plurality of electrode films stacked via a first air gap. The second air gap extends in a stacking direction of the stacked body. The second air gap separates the stacked body in a first direction crossing the stacking direction. The first insulating film is provided above the stacked body and covers an upper end of the second air gap. The stacked film is provided between a side surface of the electrode film and a side surface of the semiconductor film opposed to the side surface of the electrode film. The stacked film is in contact with the side surface of the electrode film and the side surface of the semiconductor film.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: June 11, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Akifumi Gawase, Kei Watanabe, Shinya Arai
  • Patent number: 10317330
    Abstract: A particle measuring apparatus includes a light source configured to irradiate a gas with light, a first optical detection unit configured to detect an intensity of reflected light from particles contained in the gas, and configured to output a first parameter value corresponding to the intensity of the reflected light, and a storage unit that stores first data indicating corresponding relationships between first parameter values particle components. The particle measuring apparatus further includes a calculation unit configured to compare the first parameter value transmitted from the first optical detection unit with the first data transmitted from the storage unit to determine a component of the particles contained in the gas.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: June 11, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaki Hirano, Yuichi Kuroda
  • Patent number: 10319786
    Abstract: A memory device includes: a wiring; an electrode that includes a first portion provided on the wiring, and a second portion provided on the first portion; a first pillar and a second pillar that are provided inside the second portion; a first conductive layer that is provided below the first pillar; and a second conductive layer that is provided below the second pillar. The second portion includes a first conductive portion provided around the first pillar and including a first conductive material, a second conductive portion provided around the second pillar and containing the first conductive material, and a third conductive portion provided around the first and second conductive portions, containing a second conductive material, and electrically connected to the first portion and the first and second conductive portions. The first portion includes the second conductive material.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 11, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kei Sakamoto
  • Patent number: 10319450
    Abstract: A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least eight threshold voltages, a first bit line, a word line, and a sense amplifier which is connected to the first bit line. A verification operation for verifying the threshold voltage of the first memory cell is performed after a programming operation is performed on the first memory cell, and the verification operation includes seven verification operations. The sense amplifier applies a charging voltage to the first bit line during two of the seven verification operations, and does not apply the charging voltage to the first bit line during the remaining five of the seven verification operations.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 11, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Maejima, Noboru Shibata
  • Patent number: 10319663
    Abstract: A semiconductor memory device includes a housing having a wall, a circuit board located in the housing and spaced from the wall and extending along the surface of the wall, a memory located on the circuit board, a heat conduction member interposed, and compressed, between the wall and the memory. The wall includes an uneven region comprising contact portions contacting the heat conduction member and recess portions located between the contact portions. The recess portions are recessed inwardly of the wall from the ends of the contact portions in a direction away from the location of the memory.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: June 11, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenichi Sawanaka
  • Patent number: 10319740
    Abstract: A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: June 11, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Yasuhito Yoshimizu
  • Publication number: 20190169461
    Abstract: According to one embodiment, a pattern formation method is disclosed. The method includes a preparation process, a block copolymer layer formation process, and a contact process. The preparation process includes preparing a pattern formation material including a block copolymer including a first block and a second block. The first block includes a first main chain and a plurality of first side chains. At least one of the first side chains includes a plurality of carbonyl groups. The block copolymer layer formation process includes forming a block copolymer layer on a first member. The block copolymer layer includes the pattern formation material and includes a first region and a second region. The first region includes the first block. The second region includes the second block. The contact process includes causing the block copolymer layer to contact a metal compound including a metallic element.
    Type: Application
    Filed: July 27, 2018
    Publication date: June 6, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Norikatsu Sasao, Koji Asakawa, Tomoaki Sawabe, Shinobu Sugimura
  • Publication number: 20190172794
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a plurality of columnar portions, a separation portion, and a wall portion. The separation portion extends through the stacked body in a first direction and separates the stacked body into a plurality of blocks in a second direction. The separation portion includes a conductive material contacting the substrate. The wall portion is disposed between the separation portion and a columnar portion of the plurality of columnar portions most proximal to the separation portion. The wall portion pierces a lowermost electrode layer of the plurality of electrode layers and pierces an interface between the substrate and the stacked body.
    Type: Application
    Filed: May 21, 2018
    Publication date: June 6, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Sachiyo ITO, Tatsuhiro ODA
  • Publication number: 20190172839
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a semiconductor body, and a charge storage portion. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The semiconductor body extends through the stacked body in a stacking direction of the stacked body. The charge storage portion is provided between the semiconductor body and each of the electrode layers. At least one of the electrode layers is a tungsten film or a molybdenum film including a portion having different fluorine concentration along the stacking direction.
    Type: Application
    Filed: September 11, 2018
    Publication date: June 6, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshinori TOKUDA
  • Publication number: 20190173875
    Abstract: According to one embodiment, a memory device includes: a nonvolatile semiconductor memory; and a controller which controls the semiconductor memory. The controller includes: a first memory which stores a first key; a second memory which stores a second key; a first generator which generates a third key based on a random number; a second generator which generates a fourth key based on the first key and the third key; and an encryptor which encrypts the second key with the third key. The third key and the encrypted second key are stored in a host device enabled to access the memory device.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 6, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Koichi NAGAI, Yuji Kashiwagi
  • Publication number: 20190172540
    Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.
    Type: Application
    Filed: January 18, 2019
    Publication date: June 6, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Hiroshi MAEJIMA
  • Patent number: 10310766
    Abstract: A memory system includes a nonvolatile semiconductor memory and a memory controller circuit. The memory controller circuit selects first and second blocks of the nonvolatile semiconductor memory, the first block being a garbage collection target block, the second block being a wear leveling target block or a refresh target block, relocates first data which is valid data stored in the first block in a series of write operations to a third block including first and second write operations, the third block being a block of the nonvolatile semiconductor memory having a free region, and relocates second data which is valid data stored in the second block in a series of write operations to a fourth block including a third write operation, the fourth block having a free region and being different from the third block, wherein the third write operation is performed between the first and second write operations.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: June 4, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichiro Nakazumi