ENCODING DATA IN A MODIFIED-MEMORY SYSTEM
Implementations of Data Bus Inversion (DBI) techniques within a memory system are disclosed. In one embodiment, a set of random access memory (RAM) integrated circuits (ICs) is separated from a logic system by a bus. The logic system can contain many of the logic functions traditionally performed on conventional RAM ICs, and accordingly the RAM ICs can be modified to not include such logic functions. The logic system, which can be a logic integrated circuit intervening between the modified RAM ICs and a traditional memory controller, additionally contains DBI encoding and decoding circuitry. In such a system, data is DBI encoded and at least one DBI bit issued when writing to the modified RAM ICs. The RAM ICs in turn store the DBI bit(s) with the encoded data. When the encoded data is read from the modified RAM ICs, it is transmitted across the bus in its encoded state along with the DBI bit(s). The logic integrated circuit then decodes the data using the DBI bit(s) to return it to its original state.
Embodiments of this invention relate to implementation of data bus inversion in a memory system.
BACKGROUNDAn example illustrating data transmission between high-speed components within a single semiconductor device, or between two devices on a printed circuit board, is represented by the system 1 shown in
As discussed in U.S. patent application Ser. No. 11/873,779, filed Oct. 17, 2007, a data bus is susceptible to cross talk, simultaneous switching noise, intersymbol interference, and draws power based on the state of the data and/or frequency of data transition. One way to reduce these adverse effects and to prevent unnecessary power consumption is to encode the data. One specific form of data encoding that can be used is Data Bus Inversion (DBI).
Implementation of DBI includes encoding circuitry at the transmitter that assesses the relationship between data bits to be transmitted across a data bus and then decides (based on a particular DBI algorithm) if it would be advantageous to invert some or all of the data bits prior to transmission. If the data bits are inverted, an additional signal, referred to as a DBI bit, is also set at the encoding circuitry to indicate that the data bits are inverted. Typically, as shown in
One specific DBI algorithm, illustrated in
The minimum transitions technique can be implemented in one embedment using the encoding circuitry 8 of
Other DBI algorithms exists, such as are discussed in the above-mentioned '779 application, and thus one skilled in the art will realize that the DBI technique illustrated in
The inventor believes that advances in system integration are making the implementation of DBI, and other data encoding algorithms, more attractive. At the same time, the use of such algorithms is becoming more important as systems shrink and as it becomes increasingly important that such systems reduce their power consumption and operate at high speeds.
Implementations of Data Bus Inversion (DBI) techniques within a memory system are disclosed. In one embodiment, a set of random access memory (RAM) integrated circuits (ICs) is separated from a logic system by a bus. The logic system can contain many of the logic functions traditionally performed on conventional RAM ICs, and accordingly the RAM ICs can be modified to not include such logic functions. The logic system, which can be a logic integrated circuit intervening between the modified RAM ICs and a traditional memory controller, additionally contains DBI encoding and decoding circuitry. In such a system, data is DBI encoded and at least one DBI bit issued when writing to the modified RAM ICs. The RAM ICs in turn store the DBI bit(s) with the encoded data. When the encoded data is read from the modified RAM ICs, it is transmitted across the bus in its encoded state along with the DBI bit(s). The logic integrated circuit then decodes the data using the DBI bit(s) to return it to its original state.
In another embodiment, DBI may be implemented only for data being transmitted in one direction over the bus, for example, when writing to the memory. In this implementation, the logic integrated circuit includes a DBI encoder, with the DBI decoder occurring on the modified RAM ICs. Data written to the modified RAM ICs is encoded and issued with at least one DBI bit on the bus. At the modified RAM ICs, the data is then decoded using the DBI bit(s) and stored in its original un-encoded state. When data is read from the modified RAM ICs, no DBI encoding occurs, and there is no need to have stored the DBI bit(s) in the modified RAM ICs.
A system 100 benefitting from the implementation of DBI is shown in
Intervening between the microprocessor 10 and the memory set 25 is a memory controller 12. Memory controllers 12 are well known in the art and work to create a standard interface 20 with which the microprocessor 10 can predictably communicate. The memory controller 12 couples to the microprocessor's data (DQ), address (A), and control (cntl) busses 11, and converts them to new busses 13 DQ′, A′, and cntl′ suitable for interfacing with a logic integrated circuit (IC) 14, discussed further below. Memory controller 12 typically comprises an integrated circuit separate and independent from other components in the system 100, but this is not strictly necessary, and the controller 12 could be integrated with other components if desired. The memory controller 12 can comprise any well known memory controller 12 used in the industry.
In the disclosed embodiment, a logic IC 14 intervenes between the memory controller 12 and the modified RAM ICs 16x, and in this respect both the logic IC 14 and the modified RAM ICs 16x differ from standard memory typically used. Departing from such standard solutions, the logic IC 14 contains much if not all of the logic circuitry 49 typically present on a standard RAM IC (not shown). For example, the logic IC 14 can contain command decode and queuing circuitry 50. Such circuitry 50 interprets the various command signals on the cntl′ data bus (such as signals write enable (WE), row address strobe (RAS), column address strobe (CAS), and chip select (CS), assuming the modified RAM arrays 16x comprise DRAM memory), and issues and organizes the commands as appropriate for distribution to the modified PAM ICs 16x along a control bus cntl″ intervening between the logic IC 14 and the RAM ICs 16x. The logic IC 14 may also contain redundancy circuitry 52 for determining faulty memory addresses in the modified RAM ICs 16x and for rerouting around such defective addresses to functioning memory cells using programmable fuses or antifuses, as is well known. Logic IC 14 may additionally contain error correction circuitry 54, which can comprise well known circuitry for assessing and correcting faulty data in accordance with any number of error correction algorithms. Further, logic IC 14 may contain test mode circuitry 56, which is typically used during manufacturing and/or under the application of special test commands to test the operation of the various modified RAM ICs 16x. Typically, such circuits 50-56 are formed as part of the peripheral logic of a standard memory integrated circuit (not shown), but in the illustrated system such circuitry has been removed from the modified RAM ICs 16x.
Logic IC 14 may also contain additional integration circuitry 58 not traditionally contained on a conventional RAM ICs, but which are relevant more globally to the modular integration of a number of memory arrays. For example, integration circuitry 58 can assess the operation of the various signals on bus 15 (DQ″, A″, cntl″) intervening between the logic IC 14 and the modified RAM ICs, and if necessary can reroute around any connections deemed to be faulty.
As a result of circuits 50-58 being present on the logic IC 14, the modified RAM ICs 16x need not contain such circuits, and instead modified RAM ICs 16x can comprise only the array of storage cells 61 and other minimal circuitry desirable for the functioning of such cells. Such other minimal circuitry can comprise the sense amplifiers 62 used to sense the data state of the cells, column decoder circuitry 64, row decoder circuitry 66, column driver circuitry 68, and row driver circuitry 70.
By moving the logic circuitry 49 off of the modified RAM ICs 16x, the RAM ICs 16x can be made smaller in area. Reducing the size of the RAM ICs 16x helps the yield and reliability of such devices, and allows their assembly into a smaller package or packages, as discussed further below with reference to
Because the logic circuitry 49 is moved off of the RAM ICs 16x and onto the logic IC 14, a bus 15 intervenes between the logic IC 14 and the modified RAM ICs 16x, as mentioned above. Bus 15 contains data (DQ″), address (A″), and control (cad″) signals that might otherwise appear internally on a standard RAM IC.
In the implementation shown in
Although shown with the memory controller 12 and module 40 on the same PCB 30, this is not strictly necessary. Additionally, the microprocessor 10 (not shown) could be on the same or separate PCBs from the memory controller 12 and/or the module 40. Further, any combination of the microprocessor 10, memory controller 12, and module 40 could be integrated within its own package or multichip module. Additionally, it is possible that the functionality contained within the memory controller 12 might also be moved to the logic IC 14, thus eliminating the need for the memory controller 12 and the bus 13 in the system. Thus, the assembled configuration shown in
With embodiments of basic systems described, discussion now turns to the application of Data Bus Inversion (DBI) to such systems. As shown in
Further details concerning such an implementation of DBI in system 200 is shown in
DBI encoding and decoding in the depicted example are implemented by encoding 210a and decoding 210b circuitry. Such circuitry 210a and 210b, in this embodiment, is present only on the logic IC 14 as opposed to the modified RAM ICs 216x, which is consistent with the desired intention in system 200 to move as much of the logic circuitry off of the modified RAM ICs 216x and onto the logic IC 14 as possible.
When writing to the modified RAM IC 216x (or more generally, the memory set 25), data is presented from the memory controller 12 to the logic IC 14 on bus DQ′, along with the appropriate address for that data and a write command as embodied in the signals present on control bus, cntl′. (The address bus from the memory controller 12, A′, is not shown in
Reading from the modified RAM IC 216x (i.e., from memory set 25) requires decoding of the stored data in accordance with the DBI bit stored with that data. This occurs as follows. control decoder 240 on the logic IC interprets a read command, and enables the decoder 210b via read enable signal, RIE. Encoded data is then read at the specified address from the modified. RAM IC 216x on bus DQ″ along with the DBI stored at that address. The decoder 210b interprets the DBI bit, and decodes, i.e., completely or partially un-inverts the data as necessary, and passes the decoded data to the memory controller 12 via bus DQ′.
This example allows for the implementation of DBI without requiring the modified RAM ICs 216x to have any DBI logic circuitry whatsoever. However, in this embodiment, the modified RAM ICs 216x will need to store the DBI bit, which will either require the modified. RAM ICs 216x to increase in size, or to store less data within the nominal size.
Another embodiment of the disclosed DBI technique that does not require storage of the DBI bits is shown in the system 200′ of
If it is undesired or impossible to include an additional modified RAM IC 250 within the module 40 as shown in
Operation of the one-way DBI algorithm in system 300 is explained further in
In any event, while writing (i.e., while W/E is asserted), decoder 310 will take the encoded data DQ″ after transmission on the bus 15 and un-invert such data as mandated by the DBI bit at the modified RAM ICs 316x. Such decoding can be accomplished by the simple utilization of XOR gates 315 for each of the data channels, DQ″, as shown in
To reiterate, by operation of the DBI encoder 210a on the logic IC 14 and decoder 310 on the RAM ICs 316x, data is or is not inverted during transmission to the modified RAM ICs 316x across bus 15 to improve power consumption, data integrity, and reliability. But, the inverted data is then decoded. and stored in its true state in the array of cells 61 of those RAM ICs 316x. By contrast, when reading from system 300, no DBI algorithm operates in this embodiment, and instead the true data is merely read from the modified RAM ICs 316x and is transmitted back across bus 15 without encoding.
As a result, and beneficially, in this embodiment of
However, this embodiment does require that the modified RAM ICs 316x include a DBI decoder 310. Generally, the provision of such a decoder 310 on the modified RAM ICs 316x is contrary to the desire that the modified RAM ICs contain as little excess circuitry as possible. But as shown in
In another embodiment (not shown), the DBI encoder can be provided on the modified RAM ICs, while a DB1 decoder is present on the logic IC 14. This presents essentially the reverse of the one-way DBI technique discussed in
Any of the DBI implementation set forth in
While envisioned for use with discrete integrated memory circuits, the disclosed technique can be used more generally with any memory structure having storage cells, even if not a discrete integrated circuit. For example, a plurality of memory sub-arrays could operate as the plurality of memory structures useable in the technique, even if such sub-arrays are themselves integrated on a single integrated circuit. Additionally, while illustrated in the context of a plurality of memory ICs (or a plurality of memory structures more generally), it should be noted that the disclosed technique still has applicability when used with a single memory IC (or memory structure).
As noted earlier, many different types of DBI algorithms exist. Different DBI algorithms are beneficial in different circumstances, and not all DBI algorithms are directed to minimizing the number of data transition across transmission channels. For example, other well-known DBI algorithms include the “minimum zeros” algorithm and the “minimum ones” algorithm. The purpose of these algorithms is, respectively, to minimize the number of binary zeros or binary ones transmitted across a channel. Such minimum zeros or ones algorithms conserve power when the driver or receiver circuits coupled to the transmission channels are not full CMOS and therefore will draw more power when transmitting or receiving a particular data state. For example, if a pull-up resistor connected to the voltage supply is used in a particular driver circuit, driving a logic ‘0’ will require more power than would driving a logic ‘1’. As a result, use of a minimum zeros DBI algorithm would be warranted. Likewise, if a pull-down resistor is used, a minimum ones algorithm would be warranted. The minimum transitions and either of the minimum zeros or ones algorithms can also be combined in a DBI algorithm, as is disclosed in U.S. patent application Ser. No. 12/015,311, filed Jan. 16, 2008. In another DBI algorithm, discussed in the above-mentioned Ser. No. 11/873,779 application, only a portion of the data bits on a bus are inverted to balance the logic states in an encoded byte across the bus, which can be referred to as a Balanced DBI algorithm. Regardless of the DBI algorithm used, all of these DBI algorithms have the common feature of sequentially receiving groups of N original data bits and selectively encoding each group to form a corresponding group of N encoded data bits while issuing at least one encoding (DBI) indicator associated with each group of the N encoded data bits. Any of these DBI algorithms can be used in the context of the disclosed embodiments of the invention, and therefore the illustration or focus given to the minimum transition DBI algorithm should be understood as merely exemplary and non-limiting.
While some implementations have been disclosed, it should be understood that the disclosed circuitry can be achieved in many different ways to the same useful ends as described herein. In short, it should be understood that the inventive concepts disclosed herein are capable of many modifications. To the extent such modifications fall within the scope of the appended claims and their equivalents, they are intended to be covered by this patent.
Claims
1. (canceled)
2. A device comprising:
- a logic circuit communicatively coupled to a memory controller using a first bus and a memory circuit using a second bus, the logic circuit configured to perform operations comprising: receiving a set of N original data bits from the memory controller over the first bus; selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits; generating an encoding indicator associated with the set of N encoded data bits; and transmitting the set of N encoded data bits and the encoding indicator to a memory circuit over the second bus to cause the memory circuit to store the set of N encoded data bits and the encoding indicator in the memory circuit, the memory circuit a separate circuit than the logic circuit.
3. The device of claim 2, wherein the logic circuit is further configured to perform the operations comprising:
- receiving the set of N encoded data bits and the encoding indicator from the memory circuit;
- decoding the set of N encoded data bits using the encoding indicator to recover the set of N original data bits; and
- transmitting the set of N original data bits to the memory controller over the first bus.
4. The device of claim 2, wherein the operations of selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits comprises selectively encoding the set of N original data bits based upon a set of previously processed data bits sent over the second bus.
5. The device of claim 4, wherein the operations of selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits comprises applying a data bit inversion (DBI) to minimize a number of bit transitions between the set of N encoded bits and the set of previously processed data bits.
6. The device of claim 2, wherein the operations of receiving the set of N original data bits comprises a write request to write the set of N original data bits to the memory circuit.
7. The device of claim 2, wherein the memory circuit is a random-access memory circuit.
8. The device of claim 2, wherein the logic circuit includes one or more of: command decode circuitry; queueing circuitry; redundancy circuitry; error correction circuitry; test mode circuitry; or integration circuitry.
9. A method comprising:
- at a logic circuit communicatively coupled to a memory controller using a first bus and a memory circuit using a second bus, performing operations of:
- receiving a set of N original data bits from the memory controller over the first bus;
- selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits;
- generating an encoding indicator associated with the set of N encoded data bits; and
- transmitting the set of N encoded data bits and the encoding indicator to a memory circuit over the second bus to cause the memory circuit to store the set of N encoded data bits and the encoding indicator in the memory circuit, the memory circuit a separate circuit than the logic circuit.
10. The method of claim 9, wherein the logic circuit is further configured to perform the operations comprising:
- receiving the set of N encoded data bits and the encoding indicator from the memory circuit;
- decoding the set of N encoded data bits using the encoding indicator to recover the set of N original data bits; and
- transmitting the set of N original data bits to the memory controller over the first bus.
11. The method of claim 9, wherein the operations of selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits comprises selectively encoding the set of N original data bits based upon a set of previously processed data bits sent over the second bus.
12. The method of claim 11, wherein the operations of selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits comprises applying a data bit inversion (DBI) to minimize a number of bit transitions between the set of N encoded bits and the set of previously processed data bits.
13. The method of claim 9, wherein the operations of receiving the set of N original data bits comprises a write request to write the set of N original data bits to the memory circuit.
14. The method of claim 9, wherein the memory circuit is a random-access memory circuit.
15. The method of claim 9, wherein the logic circuit includes one or more of: command decode circuitry; queueing circuitry; redundancy circuitry; error correction circuitry; test mode circuitry; or integration circuitry.
16. A memory system comprising:
- a memory controller;
- a memory circuit;
- a logic circuit interposed between the memory controller and the memory circuit, the logic circuit communicatively coupled to the memory controller using a first bus and the memory circuit using a second bus, the logic circuit comprising: receiving a set of N original data bits from the memory controller over the first bus; selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits; generating an encoding indicator associated with the set of N encoded data bits; and transmitting the set of N encoded data bits and the encoding indicator to a memory circuit over the second bus to cause the memory circuit to store the set of N encoded data bits and the encoding indicator in the memory circuit, the memory circuit a separate circuit than the logic circuit.
17. The memory system of claim 16, wherein the logic circuit is further configured to perform the operations comprising:
- receiving the set of N encoded data bits and the encoding indicator from the memory circuit;
- decoding the set of N encoded data bits using the encoding indicator to recover the set of N original data bits; and
- transmitting the set of N original data bits to the memory controller over the first bus.
18. The memory system of claim 16, wherein the operations of selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits comprises selectively encoding the set of N original data bits based upon a set of previously processed data bits sent over the second bus.
19. The memory system of claim 18, wherein the operations of selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits comprises applying a data bit inversion (DBI) to minimize a number of bit transitions between the set of N encoded bits and the set of previously processed data bits.
20. The memory system of claim 16, wherein the operations of receiving the set of N original data bits comprises a write request to write the set of N original data bits to the memory circuit.
21. The memory system of claim 16, wherein the memory circuit is a random-access memory circuit.
Type: Application
Filed: May 11, 2020
Publication Date: Oct 29, 2020
Inventor: Timothy Mowry Hollis (Meridian, ID)
Application Number: 16/871,540