DOUBLE MAGNETIC TUNNEL JUNCTION DEVICE, FORMED BY UVH WAFER BONDING
A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first magnetic tunnel junction stack. The first magnetic tunnel junction stack includes a first reference layer. The method also includes forming a second magnetic tunnel junction stack, where the second magnetic tunnel junction stack includes a second reference layer. The method also includes bonding the first magnetic tunnel junction stack to the second magnetic tunnel junction stack with ultra-high vacuum bonding to form the double magnetic tunnel junction device.
The present disclosure relates to double magnetic tunnel junction (“DMTJ”) devices and methods of manufacturing DMTJ devices. The tunnel magnetoresistance (“TMR”) and the write efficiency are factors that affect the performance of DMTJs.
SUMMARYEmbodiments of the present disclosure relate to a method of manufacturing a double magnetic tunnel junction device. The method includes forming a first magnetic tunnel junction stack. The first magnetic tunnel junction stack includes a first reference layer. The method also includes forming a second magnetic tunnel junction stack, where the second magnetic tunnel junction stack includes a second reference layer. The method also includes bonding the first magnetic tunnel junction stack to the second magnetic tunnel junction stack with ultra-high vacuum bonding to form the double magnetic tunnel junction device.
Other embodiments relate to a double magnetic tunnel junction device formed by the method described above.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure.
The drawings included in the present application are incorporated into, and form part of, the specification. They illustrate embodiments of the present disclosure and, along with the description, explain the principles of the disclosure. The drawings are only illustrative of certain embodiments and do not limit the disclosure.
The present disclosure describes double magnetic tunnel junction (“DMTJ”) devices and methods of manufacturing DMTJ devices. In particular, the present disclosure describes DMTJ devices that are formed by separately manufacturing two magnetic tunnel junction stacks (“MTJ”) in an ultra-high vacuum environment, and then later connecting them together with ultra-high vacuum (“UHV”) wafer bonding techniques.
Embedded DRAM (“eDRAM”) is a dynamic random-access memory (“DRAM”) integrated on the same die or multi-chip module (“MCM”) of an application-specific integrated circuit (“ASIC”) or microprocessor. eDRAM has been implemented in silicon-on-insulator (“SOI”) technology, which refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing. eDRAM technology has met with varying degrees of success, and demand for SOI technology as a server memory option has decreased in recent years.
Magnetoresistive random-access memory (“MRAM”) devices using magnetic tunnel junctions (“MTJ”) are one option to replace existing eDRAM technologies. MRAM is a non-volatile memory, and this benefit is a driving factor that is accelerating the development of this memory technology. Current MRAM MTJ structures are relatively slow, and the only way to reach MTJ write target speeds comparable to eDRAM (˜5 ns) are with double magnetic tunnel junctions (“DMTJ”). DMTJ devices reduce the write current by factor of two.
In related DMTJ devices, the DMTJ stack is fabricated from the bottom up. The growth starts with a seed layer, that erases the crystal lattice and grain information of the underlying substrate. After the seed layer is grown, a reference layer is grown. For the reference layer, a preferred crystallographic grain orientation is either <111>face centered cubic (“FCC”) or <0001>hexagon close packed (“HCP”). For example, a reference layer may be an HCP metal layer with high perpendicular magnetic anisotropy.
However, there is a problem with DMTJs because the reference layer for the top MTJ is situated on the top of the stack, thereby eliminating the advantage of having a lattice and grain information erasing layer (i.e., the seed layer). In this regard, the reference layer on the bottom MTJ has the advantage of being immediately formed on the very flat surface of the grain information erasing seed layer. However, as additional layers are formed on top of the reference layer for the first MTJ (e.g., magnetic free layers and tunnel barrier layers), the surface quality (e.g., surface flatness or crystal grain orientation) diminishes gradually with each subsequent layer being formed. As such, while the reference layer for the bottom MTJ device has the advantage of being formed on a relatively smooth surfaced underlying layer, by the time the reference layer for the top MTJ device is formed, its respective underlying layer has a lower surface quality. In other words, the relatively poor surface quality of the layer underlying the reference layer for the top MTJ stack would transmit to the top MTJ stack and inhibit its performance. Having such an imperfect top MTJ stack layer within the combined DMTJ stack would negatively impact the spin information in the DMTJ. Forming the top reference layer while maintaining a high tunnel magnetoresistance (“TMR”) and write efficiency is one of the main challenges for fabrication of high performance DMTJs.
In certain embodiments, during formation of the DMTJ devices, each of the two MTJ stacks includes, at a minimum, a grain erasing layer (e.g., a seed layer, or a substrate having a <0001>HCP crystal orientation structure) and at least a portion of a reference layer formed on the grain erasing layer. Thus, both of the reference layers (or at least significant portions of the reference layers) are formed on their own respective grain information erasing base layer. Therefore, not only does the reference layer for the bottom MTJ device has the advantage of being formed on a relatively smooth underlying layer, but the top MTJ stack has this advantage as well. Thus, when the two stacks are combined, the DMTJ devices are able to maintain a high tunnel magnetoresistance (“TMR”) and write efficiency.
As described in further detail below, different bonding interface locations between the first and second MTJ stacks (e.g., a bottom MTJ stack and a top MTJ stack) may be used. In the present embodiments, by forming the second MTJ stack separately from the first MTJ stack, the reference layer for the second MTJ stack is grown closer to the grain erasing layer of the second MTJ stack (i.e., rather than on top of the cumulative layered structure of the first MTJ stack). This has the effect of maintaining a high tunnel magnetoresistance (“TMR”) and write efficiency for the DMTJ device.
The flowcharts and cross-sectional diagrams in the Figures illustrate methods of manufacturing DMTJs according to various embodiments. In some alternative implementations, the manufacturing steps in the flowcharts may occur in a different order that that which is noted in the Figures. Moreover, any of the layers depicted in the Figures may contain multiple sublayers.
Referring now to the drawings in which like numerals represent the same or similar elements and initially to
In general, UHV wafer bonding is performed in an ultra-high vacuum system, where the pressure is reduced down to about the 10−9 to 10−10 Pa range. In certain embodiments, a combination of a UHV and MTJ deposition chamber with a UHV bonding system is used to allow stack deposition and bonding without air break. When the wafers are brought into contact, a bond wave propagates along the interface and a new solid is formed from the two pieces. The bonds are covalent, giving a very high bonding strength.
Forming the combined DMTJ structure by separately forming the MTJ stacks and then UVH bonding them together has the effect of eliminating (or significantly reducing) quality problems with the top reference layer. Because of the higher quality reference layer relative to related art techniques, the present embodiments provide DMTJ devices with a high TMR level and write efficiency.
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In step 112, the plurality of DMTJ devices are encapsulated with an encapsulating layer. In step 114, a low-k layer is formed between the devices. In general, in semiconductor manufacturing, a low-k is a material with a small relative dielectric constant relative to silicon dioxide. The low-k dielectric material layer separates the conducting parts (wire interconnects and transistors) of the different DMTJ devices from one another. In step 116, a metal line layer if formed on top of the DMTJ devices.
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In step 200, a substrate is used as a starting structure. The substrate may be a silicon wafer, a quartz glass wafer, or any other suitable wafer with a rigid and smooth surface. In certain embodiments, the substrate does not produce outgassing when it is in an ultra-high vacuum (“UVH”) environment. In certain embodiments, it is not necessary for the substrate to have high temperature resistivity.
In step 202, a debond layer is formed on top of the substrate. In one example, the debond layer is a thermal oxide layer. In another example, the debond layer is a UVH resistance glue, is rigid, has a smooth surface, and is not susceptible to outgas sing in a UVH environment. As with the substrate, and in certain embodiments, it is not necessary for the debond layer to have high temperature resistivity. It should be appreciated that the debond layer may be any suitable layer, and comprise any suitable combination of materials, that allows the substrate and the bonding layer to be later removed from the combined DMTJ device, as was described in step 108 of
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In step 302, a first metal layer is formed on top of the FEOL layers. In one example, the first metal layer includes contacts and vias. In step 304, a first electrode layer is formed on the first metal layer. In this example, the FEOL layers, the first metal layer and the first electrode layer are a starting structure upon which the bottom MTJ stack is later formed.
In certain embodiments, steps 306, 308, 310, 312, 314 and 316 are the steps for forming the bottom MTJ stack. In step 306, the reference layer is formed. Information is stored in the magnetic orientation of a free layer film in relation to that of the reference layer. The reference layer may be a single layer or a plurality of layers. In an embodiment, the reference layer of the bottom MTJ stack is a synthetic antiferromagnetic (“SAF”) layer. In certain embodiments, the reference layer of the bottom and top MTJ stacks includes a plurality of sublayers (e.g., twenty or more sublayers), and an outermost sublayer is composed of CoFeB.
In step 308, the first tunnel barrier layer is formed on top of the reference film. In an embodiment, the tunnel barrier layer is a barrier, such as a thin insulating layer or electric potential, between two electrically conducting materials. Electrons (or quasiparticles) pass through the tunnel barrier by the process of quantum tunneling. In certain embodiment, the first tunnel barrier layer includes a sublayer composed of MgO. In these embodiments, the MgO sublayer of the tunnel barrier layer is bonded to the outermost CoFeB sublayer of the reference layer.
In step 310, the first free layer is formed. The first free layer is a magnetic free layer that is adjacent to the first tunnel barrier layer so as to be opposite the reference layer. The first magnetic free layer has a magnetic moment or magnetization that can be flipped. In step 312, a metal spacer layer is formed on the first free layer. In step 314, the second free layer is formed on the metal spacer layer. As such, the metal spacer layer is sandwiched between the first and second free layers.
In step 316, the second tunnel barrier layer is formed on the second free layer. In an embodiment, the second tunnel barrier includes an outermost sublayer comprised of the same material (e.g., MgO) as the first tunnel barrier layer. Thus, the bottom MTJ stack is formed by steps 306, 308, 310, 312, 314 and 316, and includes the reference layer, the first tunnel barrier layer, the first free layer, the metal spacer layer, the second free layer, and the second tunnel barrier layer. It should be appreciated that the bottom MTJ stack may include additional layers, omit certain layers, and each of the layers may include sublayers. Thus, in certain embodiments, the steps in
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Bonding interface 1330 is between two of the sublayers of the second reference layer 1324. Thus, a plurality of sublayers of the second reference layer 1324 are formed during formation of the second MTJ stack 726 (see,
Bonding interface 1334 is between sublayers of the metal spacer layer 1312. Thus, at least one sublayer of the metal spacer layer 1312 is formed on the first MTJ stack 728 and at least one sublayer of the metal spacer layer 1312 is formed on the second MTJ stack 726. It should be appreciated that other locations for the bonding interface can occur as long as the first reference layer is formed during formation of the first MTJ stack and the second reference layer is formed during formation of the second MTJ stack, and as long as neither of the free layers 1310 and 1314 are the outermost layer. That is, the free layers would not form part of the bonding interface when joining the first and second MTJ stacks together. Also, the separate formation of the reference layers on the first and second MTJ stacks allow for higher quality reference layers relative to related art techniques, and this results in DMTJ devices with a high TMR level and write efficiency.
The descriptions of the various embodiments have been presented for purposes of illustration and are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims
1. A method of manufacturing a double magnetic tunnel junction device, the method comprising:
- forming a first magnetic tunnel junction stack, the first magnetic tunnel junction stack including a first reference layer;
- forming a second magnetic tunnel junction stack, the second magnetic tunnel junction stack including a second reference layer; and
- wafer bonding the first magnetic tunnel junction stack to the second magnetic tunnel junction stack with ultra-high vacuum (UHV) bonding to form the double magnetic tunnel junction device.
2. The method according to claim 1, wherein forming the first magnetic tunnel junction stack includes:
- providing a first substrate;
- forming the first reference layer on the first substrate;
- forming a first tunnel barrier layer on the first reference layer;
- forming a first magnetic free layer on the first tunnel barrier layer;
- forming a second magnetic free layer on the first magnetic free layer; and
- forming a second tunnel barrier layer on the second magnetic free layer.
3. The method according to claim 2, wherein forming the second magnetic tunnel junction stack includes:
- providing a second substrate; and
- forming a second reference layer on the second substrate.
4. The method according to claim 2, further comprising forming a metal spacer layer between the first magnetic free layer and the second magnetic free layer.
5. The method according to claim 1, wherein forming the first magnetic tunnel junction stack includes:
- providing a first substrate;
- forming the first reference layer on the first substrate;
- forming a first tunnel barrier layer on the first reference layer; and
- forming a first magnetic free layer on the first tunnel barrier layer.
6. The method according to claim 5, wherein forming the second magnetic tunnel junction stack includes:
- providing a second substrate;
- forming the second reference layer on the second substrate;
- forming a second tunnel barrier layer on the second reference layer; and
- forming a second magnetic free layer on the second tunnel barrier layer.
7. The method according to claim 6, further comprising forming a metal spacer layer between the first magnetic free layer and the second magnetic free layer.
8. The method according to claim 1, wherein the first reference layer comprises a plurality of sublayers, and an outermost sublayer of the first reference layer comprises CoFeB, and wherein the second reference layer comprises a plurality of sublayers, and an outermost sublayer of the second reference layer comprises CoFeB.
9. The method according to claim 1, wherein the first magnetic tunnel junction stack is formed in a first UHV system, the second magnetic tunnel junction stack is formed in a second UHV system, and the first and second UVH systems are connected under the same UVH conditions throughout their formation and subsequent wafer bonding.
10. The method according to claim 1, wherein the wafer bonding occurs at an interface between the first and second magnetic tunnel junction stacks, the interface being one selected from:
- an interface between a tunnel barrier layer of the first magnetic tunnel junction stack and the second reference layer of the second magnetic tunnel junction stack;
- an interface between a sublayer of the second reference layer of the second magnetic tunnel junction stack and a sublayer of a third reference layer of the first magnetic tunnel junction stack;
- an interface between the first reference layer of the first magnetic tunnel junction stack and a tunnel barrier layer of the second magnetic tunnel junction stack; and
- an interface between a first metal spacer layer of the first magnetic tunnel junction stack and a second metal spacer layer of the second magnetic tunnel junction stack.
11. A double magnetic tunnel junction device comprising:
- a first magnetic tunnel junction stack, the first magnetic tunnel junction stack including a first reference layer;
- a second magnetic tunnel junction stack formed separately from the first magnetic tunnel junction stack, the second magnetic tunnel junction stack including a second reference layer; and
- wherein the first magnetic tunnel junction stack is bonded to the second magnetic tunnel junction stack under ultra-high vacuum wafer bonding to form the double magnetic tunnel junction device.
12. The double magnetic tunnel junction device according to claim 11, wherein the first magnetic tunnel junction stack includes:
- a first substrate, the first reference layer provided on the first substrate;
- a first tunnel barrier layer provided on the first reference layer;
- a first magnetic free layer provided on the first tunnel barrier layer;
- a second magnetic free layer provided on the first magnetic free layer; and
- a second tunnel barrier layer provided on the second magnetic free layer.
13. The double magnetic tunnel junction device according to claim 12, wherein the second magnetic tunnel junction stack includes:
- a second substrate; and
- a second reference layer provided on the second substrate.
14. The double magnetic tunnel junction device according to claim 12, further comprising a metal spacer layer provided between the first magnetic free layer and the second magnetic free layer.
15. The double magnetic tunnel junction device according to claim 11, wherein the first magnetic tunnel junction stack includes:
- a first substrate, the first reference layer provided on the first substrate;
- a first tunnel barrier layer provided on the first reference layer; and
- a first magnetic free layer provided on the first tunnel barrier layer.
16. The double magnetic tunnel junction device according to claim 15, wherein the second magnetic tunnel junction stack includes:
- a second substrate, the second reference layer provided on the second substrate;
- a second tunnel barrier layer provided on the second reference layer; and
- a second magnetic free layer provided on the second tunnel barrier layer.
17. The double magnetic tunnel junction device according to claim 16, further comprising a metal spacer layer provided between the first magnetic free layer and the second magnetic free layer.
18. The double magnetic tunnel junction device according to claim 11, wherein the first reference layer comprises a plurality of sublayers, and an outermost sublayer of the first reference layer comprises CoFeB, and wherein the second reference layer comprises a plurality of sublayers, and an outermost sublayer of the second reference layer comprises CoFeB.
19. The double magnetic tunnel junction device according to claim 11, wherein the first magnetic tunnel junction stack is formed in a first UHV system, the second magnetic tunnel junction stack is formed in a second UHV system, and the first and second UVH systems are connected under the same UVH conditions throughout their formation and subsequent wafer bonding.
20. The double magnetic tunnel junction device according to claim 11, wherein the wafer bonding occurs at an interface between the first and second magnetic tunnel junction stacks, the interface being one selected from:
- an interface between a tunnel barrier layer of the first magnetic tunnel junction stack and the second reference layer of the second magnetic tunnel junction stack;
- an interface between a sublayer of the second reference layer of the second magnetic tunnel junction stack and a sublayer of a third reference layer of the first magnetic tunnel junction stack;
- an interface between the first reference layer of the first magnetic tunnel junction stack and a tunnel barrier layer of the second magnetic tunnel junction stack; and
- an interface between a first metal spacer layer of the first magnetic tunnel junction stack and a second metal spacer layer of the second magnetic tunnel junction stack.
Type: Application
Filed: Nov 22, 2019
Publication Date: May 27, 2021
Patent Grant number: 11114607
Inventors: Alexander Reznicek (Troy, NY), Virat Vasav Mehta (Albany, NY)
Application Number: 16/691,725