Abstract: A microelectronic structure including a nanosheet transistor that includes a source/drain. A frontside contact that includes a first section located on the frontside of the source/drain and a via section that extends to the backside of the nanosheet transistor. A shallow isolation layer located around a portion of the via section the first frontside contact. A backside metal line located on a backside surface of the via section and located on a backside surface of the shallow trench isolation layer. A dielectric liner located along a sidewall of the backside metal line and located along a bottom surface of the backside metal line.

Abstract: Embodiments of the invention are directed to a computer system having a memory coupled to a processor system, wherein the processor system is operable to perform processor system operations that include accessing a model of a physical object; and accessing instructions associated with the model of the physical object. The instructions are used to control a printhead coupled to a unique-identifier-element-infused (UIE-infused) filament source to print the physical object from UIE-infused filament.

Abstract: A flexible ultraviolet sensor circuit is provided comprising a number of solar cells, a reflective display device electrically connected to the solar cells, and a floating gate transistor electrically connected to the solar cells and reflective display device. A floating gate in the floating gate transistor discharges in response to ultraviolet light such that the floating gate transistor turns on when a threshold voltage of the floating gate transistor drops below a combined open circuit voltage of the solar cells minus a switching threshold of the reflective display device, thereby causing electrical current flow through the ultraviolet sensor circuit. The reflective display device changes as the electrical current flow increases, indicating total ultraviolet light exposure.

Abstract: A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.

Abstract: Methods, systems, and a computer program product are disclosed. The first method includes obtaining virtual session data in real time, identifying a positional utterance in the virtual session data, and generating a positional insight for the positional utterance. The first method also includes rendering a user avatar in a position recommended based on the positional insight. The second method includes obtaining virtual session data in real time, identifying a positional utterance in the virtual session data, and generating positional insights for the positional utterance. The second method also includes generating at least one position recommendation based on the positional insights.

Abstract: A Darlington pair sensor is disclosed. The Darlington pair sensor has an amplifying/horizontal bipolar junction transistor (BJT) and a sensing/vertical BJT and can be used as a biosensor. The amplifying bipolar junction transistor (BJT) is horizontally disposed on a substrate. The amplifying BJT has a horizontal emitter, a horizontal base, a horizontal collector, and a common extrinsic base/collector. The common extrinsic base/collector is an extrinsic base for the amplifying BJT. The sensing BJT has a vertical orientation with respect to the amplifying BJT. The sensing BJT has a vertical emitter, a vertical base, an extrinsic vertical base, and the common extrinsic base/collector (in common with the amplifying BJT). The common extrinsic base/collector acts as the sensing BJT collector. The extrinsic vertical base is separated into a left extrinsic vertical base and a right extrinsic vertical base giving the sensing BJT has two separated (dual) bases, a sensing base and a control base.

Abstract: A semiconductor device is provided. The semiconductor device includes a first device including a first nanosheet stack formed on a substrate, the first nanosheet stack including alternating layers of a first work function metal (WFM) gate layer and an active semiconductor layer, a second nanosheet stack formed on the substrate, the second nanosheet stack including alternating layers of a second WFM gate layer and the active semiconductor layer, a shallow trench isolation (STI) region formed in the substrate between the first nanosheet stack and the second nanosheet stack, and an STI divot formed in the STI region. The first WFM gate layer of the first nanosheet stack is formed in the STI divot.

Abstract: An approach for providing real-time information and guidance for oxygen management to a user operating a self-contained breathing apparatus (SCBA) is disclosed. The approach receives data from IoT devices associated with a user, analyzes the data using machine learning algorithms trained on a dataset of historical data and simulated scenarios. The approach generates an oxygen-use prediction based on the analyzing. Furthermore, the approach generates one or more recommendations based on the prediction and displaying the prediction and the recommendation on a HUD (head up display) of a user.

Abstract: A 3D printed dental implant. The 3D printed dental implant includes a 3D printed dental implant body, and a plurality of sensors embedded within the 3D printed dental implant body.

Abstract: A stacked field-effect transistors (FETs) layout and a method for fabrication are provided. The stacked FETs include a buried interconnect within the stacked devices which provides power to buried components without requiring a wired connection from a top of the stacked FET to the buried components. The buried interconnect allows for efficient scaling of the stacked devices without extraneous wiring from a top of the device to each epitaxial region/device within the overall device.

Abstract: A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a first electrode and a second electrode separated by a dielectric film. A portion of the dielectric film directly above the first electrode may be crystalline. The semiconductor structure may include a stud below and in electrical contact with the first electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

Abstract: A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a bottom electrode and a top electrode separated by a dielectric film. A portion of the dielectric film directly above the bottom electrode may be doped and crystalline. The semiconductor structure may include a stud below and in electrical contact with the bottom electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

Abstract: Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

Abstract: Embodiments are disclosed for a field effect transistor (FET) device. The FET device includes a semiconductor channel. Additionally, the FET device includes a first gate dielectric in contact with the semiconductor channel. Further, the FET device includes a metal-insulator-metal (MIM) structure. The MIM structure includes a liner comprising a first metal, an insulator, and a second metal. The first metal is in contact with the first gate dielectric. Additionally, the insulator is in contact with the first metal and the second metal. Further, the FET device includes a floating gate. The floating gate includes the first metal and an extension. Additionally, the extension is disposed to one side of the MIM structure, and includes a surface for sensing a sample in contact with the surface.

Abstract: A memory device including a pedestal structure containing a cobalt aluminum layer and a magnesium-aluminum-oxide containing base layer both of which have a (001) crystal orientation is provided. The memory device further includes a magnetic tunnel junction (MTJ) pillar containing an ordered alloy forming an interface with the cobalt aluminum alloy layer. The use of the structural and textural engineered pedestal structure provides improved control of resistance, as well as improved magnetic properties such as higher tunnel magnetoresistance (TMR) and higher perpendicular magnetic anisotropy (PMA), and closer distribution of the ordered alloy.

Abstract: An integrated sensor array may include a semiconductor substrate. The integrated sensor array may be arranged in multiple sensor sub-arrays formed on the substrate. Each sensor sub-array may include multiple, densely packed cross-reactive sensors. Each cross-reactive sensor of within the same sensor sub-array may be functionalized differently than each of the other cross-reactive sensor of the same sensor sub-array.

Abstract: A spin-orbit torque (SOT)-MRAM comprising a first magnetic tunneling junction (MTJ) having a first distance and having a first critical voltage. A second MTJ having a second distance and having a second critical voltage, wherein the first distance and the second distance are different, wherein the first critical voltage and the second critical voltages are different. A metal rail in direct contact with the first MTJ and the second MTJ, wherein the metal rail injects a spin current in to both the first MTJ and the second MTJ.

Abstract: In an approach to improve the generation of a virtual object in a three-dimensional virtual environment, embodiments of the present invention identify a virtual object to be generated in a three-dimensional virtual environment based on a natural language utterance. Additionally, embodiments generate the virtual object based on a CLIP-guided Generative Latent Space (CLIP-GLS) analysis, and monitor usage of the generated virtual object in the three-dimensional virtual space. Moreover, embodiments infer human perception data from the monitoring, and generate a utility score for the virtual object based on the human perception data.

Abstract: A magnetic tunnel junction (MTJ) stack structure includes a reference layer; a tunnel barrier; and a free layer that comprises three distinct materials. All of the three distinct materials in the free layer are magnetic material. One of the three distinct materials in the free layer is a C38 structure alloy.

Abstract: A semiconductor device includes a vertical insulator pillar extending from the substrate. A first stack of horizontal sheets of a first channel device is coupled to a lateral first side of the vertical insulator pillar and a second stack of horizontal sheets of a second channel device is coupled to a lateral second side of the vertical insulator pillar, opposite the first stack of horizontal sheets. A first gate stack is wrapped around the first stack of horizontal sheets. A second gate stack is wrapped around the second stack of horizontal sheets. A first gate extension is coupled to a center portion of the first gate stack and extending laterally away from the second gate stack and a second gate extension is coupled to a center portion of the second gate stack and extending laterally away from the first gate stack.