Abstract: Embodiments of the invention are directed to a transistor device that includes a channel stack having stacked, spaced-apart, channel layers. A first source or drain (S/D) region is communicatively coupled to the channel stack. A tunnel extends through the channel stack, wherein the tunnel includes a central region and a first set of end regions. The first set of end regions is positioned closer to the first S/D region than the central region is to the first S/D region. A first type of work-function metal (WFM) is formed in the first set of end regions, the first WFM having a first work-function (WF). A second type of WFM is formed in the central region, the second type of WFM having a second WF, wherein the first WF is different than the second WF.

Abstract: A pillar or trench structure in a substrate includes vertical portions and one or more indented cavities in a sidewall between the vertical portions. The indented cavities are partial undercuts substantially traverse to the vertical portions pillar structure, or separate undercuts attached to an anchor. A higher capacitance density is achieved through the layering of multiple conductive contact layers and insulating layers in the undercuts and the vertical portions of the pillar or trench structure.

Abstract: A semiconductor structure, and a method of making the same includes a fin extending upward from a substrate, an epitaxially grown bottom source/drain region in direct contact with the substrate and a bottom portion of the fin. A bottom surface and sidewalls of a metal silicide layer are in direct contact with the epitaxially grown bottom source/drain region. A bottom spacer is located above and in direct contact with the metal silicide layer and a portion of the epitaxially grown bottom source/drain region not covered by the metal silicide layer, the bottom spacer surrounding the fin.

Abstract: A semiconductor structure including a dielectric bar arranged between and physically separating a first source drain region from a second source drain region, a first silicide liner directly beneath the first source drain region, and second silicide liner directly beneath the second source drain region, where the first silicide liner is a different material than the second silicide liner.

Abstract: A bite guard configured to conform to teeth of a patient, and an array of sensor assemblies encapsulated in the bite guard, where the array of sensor assemblies is distributed throughout the bite guard, and where each sensor assembly includes a piezo pressure sensor.

Abstract: Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a field effect transistor (FET). The FET includes a source/drain (S/D) epitaxy and a metal gate. Additionally, the semiconductor structure includes a backside epitaxy in electrical contact with the S/D epitaxy. Further, the backside epitaxy includes a highly doped epitaxy. Additionally, the semiconductor structure includes a backside contact in electrical contact with the backside epitaxy. Further, the semiconductor structure includes a backside power distribution network in electrical contact with the backside contact.

Abstract: Strained semiconductor FET devices with epitaxial quality improvement are provided. In one aspect, a semiconductor FET device includes: a substrate; at least one device stack including active layers oriented horizontally one on top of another on the substrate; gates surrounding at least a portion of each of the active layers; gate spacers alongside the gates; and source/drains, interconnected by the active layers, on opposite sides of the gates, wherein the source/drains are offset from the gates by inner spacers, wherein the source/drains include an epitaxial material having a low defect density which induces strain in the active layers, and wherein the gate spacers are formed from a same material as the inner spacers. A method of forming the semiconductor FET device using a spacer last process is also provided.

Abstract: Embodiments of the invention are directed to a computer system having a memory coupled to a processor system, wherein the processor system is operable to perform processor system operations that include accessing a model of a physical object; and accessing instructions associated with the model of the physical object. The instructions are used to control a printhead coupled to a unique-identifier-element-infused (UIE-infused) filament source to print the physical object from UIE-infused filament.

Abstract: A flexible ultraviolet sensor circuit is provided comprising a number of solar cells, a reflective display device electrically connected to the solar cells, and a floating gate transistor electrically connected to the solar cells and reflective display device. A floating gate in the floating gate transistor discharges in response to ultraviolet light such that the floating gate transistor turns on when a threshold voltage of the floating gate transistor drops below a combined open circuit voltage of the solar cells minus a switching threshold of the reflective display device, thereby causing electrical current flow through the ultraviolet sensor circuit. The reflective display device changes as the electrical current flow increases, indicating total ultraviolet light exposure.

Abstract: A microelectronic structure including a nanosheet transistor that includes a source/drain. A frontside contact that includes a first section located on the frontside of the source/drain and a via section that extends to the backside of the nanosheet transistor. A shallow isolation layer located around a portion of the via section the first frontside contact. A backside metal line located on a backside surface of the via section and located on a backside surface of the shallow trench isolation layer. A dielectric liner located along a sidewall of the backside metal line and located along a bottom surface of the backside metal line.

Abstract: A Darlington pair sensor is disclosed. The Darlington pair sensor has an amplifying/horizontal bipolar junction transistor (BJT) and a sensing/vertical BJT and can be used as a biosensor. The amplifying bipolar junction transistor (BJT) is horizontally disposed on a substrate. The amplifying BJT has a horizontal emitter, a horizontal base, a horizontal collector, and a common extrinsic base/collector. The common extrinsic base/collector is an extrinsic base for the amplifying BJT. The sensing BJT has a vertical orientation with respect to the amplifying BJT. The sensing BJT has a vertical emitter, a vertical base, an extrinsic vertical base, and the common extrinsic base/collector (in common with the amplifying BJT). The common extrinsic base/collector acts as the sensing BJT collector. The extrinsic vertical base is separated into a left extrinsic vertical base and a right extrinsic vertical base giving the sensing BJT has two separated (dual) bases, a sensing base and a control base.

Abstract: A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.

Abstract: A semiconductor device is provided. The semiconductor device includes a first device including a first nanosheet stack formed on a substrate, the first nanosheet stack including alternating layers of a first work function metal (WFM) gate layer and an active semiconductor layer, a second nanosheet stack formed on the substrate, the second nanosheet stack including alternating layers of a second WFM gate layer and the active semiconductor layer, a shallow trench isolation (STI) region formed in the substrate between the first nanosheet stack and the second nanosheet stack, and an STI divot formed in the STI region. The first WFM gate layer of the first nanosheet stack is formed in the STI divot.

Abstract: Methods, systems, and a computer program product are disclosed. The first method includes obtaining virtual session data in real time, identifying a positional utterance in the virtual session data, and generating a positional insight for the positional utterance. The first method also includes rendering a user avatar in a position recommended based on the positional insight. The second method includes obtaining virtual session data in real time, identifying a positional utterance in the virtual session data, and generating positional insights for the positional utterance. The second method also includes generating at least one position recommendation based on the positional insights.

Abstract: An approach for providing real-time information and guidance for oxygen management to a user operating a self-contained breathing apparatus (SCBA) is disclosed. The approach receives data from IoT devices associated with a user, analyzes the data using machine learning algorithms trained on a dataset of historical data and simulated scenarios. The approach generates an oxygen-use prediction based on the analyzing. Furthermore, the approach generates one or more recommendations based on the prediction and displaying the prediction and the recommendation on a HUD (head up display) of a user.

Abstract: A 3D printed dental implant. The 3D printed dental implant includes a 3D printed dental implant body, and a plurality of sensors embedded within the 3D printed dental implant body.

Abstract: A stacked field-effect transistors (FETs) layout and a method for fabrication are provided. The stacked FETs include a buried interconnect within the stacked devices which provides power to buried components without requiring a wired connection from a top of the stacked FET to the buried components. The buried interconnect allows for efficient scaling of the stacked devices without extraneous wiring from a top of the device to each epitaxial region/device within the overall device.

Abstract: A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a first electrode and a second electrode separated by a dielectric film. A portion of the dielectric film directly above the first electrode may be crystalline. The semiconductor structure may include a stud below and in electrical contact with the first electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

Abstract: A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a bottom electrode and a top electrode separated by a dielectric film. A portion of the dielectric film directly above the bottom electrode may be doped and crystalline. The semiconductor structure may include a stud below and in electrical contact with the bottom electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

Abstract: Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.