Abstract: An approach for providing real-time information and guidance for oxygen management to a user operating a self-contained breathing apparatus (SCBA) is disclosed. The approach receives data from IoT devices associated with a user, analyzes the data using machine learning algorithms trained on a dataset of historical data and simulated scenarios. The approach generates an oxygen-use prediction based on the analyzing. Furthermore, the approach generates one or more recommendations based on the prediction and displaying the prediction and the recommendation on a HUD (head up display) of a user.

Abstract: A 3D printed dental implant. The 3D printed dental implant includes a 3D printed dental implant body, and a plurality of sensors embedded within the 3D printed dental implant body.

Abstract: A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a first electrode and a second electrode separated by a dielectric film. A portion of the dielectric film directly above the first electrode may be crystalline. The semiconductor structure may include a stud below and in electrical contact with the first electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

Abstract: A stacked field-effect transistors (FETs) layout and a method for fabrication are provided. The stacked FETs include a buried interconnect within the stacked devices which provides power to buried components without requiring a wired connection from a top of the stacked FET to the buried components. The buried interconnect allows for efficient scaling of the stacked devices without extraneous wiring from a top of the device to each epitaxial region/device within the overall device.

Abstract: A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a bottom electrode and a top electrode separated by a dielectric film. A portion of the dielectric film directly above the bottom electrode may be doped and crystalline. The semiconductor structure may include a stud below and in electrical contact with the bottom electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

Abstract: Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

Abstract: Embodiments are disclosed for a field effect transistor (FET) device. The FET device includes a semiconductor channel. Additionally, the FET device includes a first gate dielectric in contact with the semiconductor channel. Further, the FET device includes a metal-insulator-metal (MIM) structure. The MIM structure includes a liner comprising a first metal, an insulator, and a second metal. The first metal is in contact with the first gate dielectric. Additionally, the insulator is in contact with the first metal and the second metal. Further, the FET device includes a floating gate. The floating gate includes the first metal and an extension. Additionally, the extension is disposed to one side of the MIM structure, and includes a surface for sensing a sample in contact with the surface.

Abstract: A memory device including a pedestal structure containing a cobalt aluminum layer and a magnesium-aluminum-oxide containing base layer both of which have a (001) crystal orientation is provided. The memory device further includes a magnetic tunnel junction (MTJ) pillar containing an ordered alloy forming an interface with the cobalt aluminum alloy layer. The use of the structural and textural engineered pedestal structure provides improved control of resistance, as well as improved magnetic properties such as higher tunnel magnetoresistance (TMR) and higher perpendicular magnetic anisotropy (PMA), and closer distribution of the ordered alloy.

Abstract: An integrated sensor array may include a semiconductor substrate. The integrated sensor array may be arranged in multiple sensor sub-arrays formed on the substrate. Each sensor sub-array may include multiple, densely packed cross-reactive sensors. Each cross-reactive sensor of within the same sensor sub-array may be functionalized differently than each of the other cross-reactive sensor of the same sensor sub-array.

Abstract: A spin-orbit torque (SOT)-MRAM comprising a first magnetic tunneling junction (MTJ) having a first distance and having a first critical voltage. A second MTJ having a second distance and having a second critical voltage, wherein the first distance and the second distance are different, wherein the first critical voltage and the second critical voltages are different. A metal rail in direct contact with the first MTJ and the second MTJ, wherein the metal rail injects a spin current in to both the first MTJ and the second MTJ.

Abstract: In an approach to improve the generation of a virtual object in a three-dimensional virtual environment, embodiments of the present invention identify a virtual object to be generated in a three-dimensional virtual environment based on a natural language utterance. Additionally, embodiments generate the virtual object based on a CLIP-guided Generative Latent Space (CLIP-GLS) analysis, and monitor usage of the generated virtual object in the three-dimensional virtual space. Moreover, embodiments infer human perception data from the monitoring, and generate a utility score for the virtual object based on the human perception data.

Abstract: A magnetic tunnel junction (MTJ) stack structure includes a reference layer; a tunnel barrier; and a free layer that comprises three distinct materials. All of the three distinct materials in the free layer are magnetic material. One of the three distinct materials in the free layer is a C38 structure alloy.

Abstract: A semiconductor device includes a vertical insulator pillar extending from the substrate. A first stack of horizontal sheets of a first channel device is coupled to a lateral first side of the vertical insulator pillar and a second stack of horizontal sheets of a second channel device is coupled to a lateral second side of the vertical insulator pillar, opposite the first stack of horizontal sheets. A first gate stack is wrapped around the first stack of horizontal sheets. A second gate stack is wrapped around the second stack of horizontal sheets. A first gate extension is coupled to a center portion of the first gate stack and extending laterally away from the second gate stack and a second gate extension is coupled to a center portion of the second gate stack and extending laterally away from the first gate stack.

Abstract: Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a first pair of field effect transistors (FETs). Additionally, the semiconductor structure includes a second pair of FETs. Further, the semiconductor structure includes a shallow gate cut that separates a first pair of gates, a first pair of channels, and a first pair of source/drain (S/D) epitaxies of the first pair of FETs. Additionally, the first pair of S/D epitaxies are wired to a backside power rail (BPR) by a backside contact. Further, the semiconductor structure includes a deep gate cut that separates a second pair of S/D epitaxies of the second pair of FETs. Additionally, one of the second pair of S/D epitaxies is wired to a back end of line (BEOL) interconnect via a frontside contact. Further, another of the second pair of S/D epitaxies is wired to the BPR by a backside contact.

Abstract: A top pinned SAF-containing magnetic tunnel junction structure is provided that contains a coupling spacer composed of a paramagnetic hexagonal metal phase material that has a stoichiometric ratio of Me3X or Me2X, wherein Me is a magnetic metal having a magnetic moment and X is a metal that alloys with Me in a hexagonal phase and dilutes the magnetic moment of Me. In embodiments in which a Me3X coupling spacer is present, Me is cobalt, and X is vanadium, niobium, tantalum, molybdenum or tungsten. In embodiments in which a Me2X coupling spacer is present, Me is iron and X is tantalum or tungsten. The coupling spacer is formed by providing a material stack including at least a precursor paramagnetic hexagonal metal phase material forming multilayered structure that includes alternating layers of magnetic metal, Me, and metal, X, and then thermally soaking the material stack.

Abstract: Fabrication method for forming a resistance tunable fuse stack structure includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer, a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer. First and second fuse contacts are formed in the fuse stack structure vertically extending through the layers and contacting at least one of the first and second fuse conductive layers. Selection of various attributes of the fuse stack structure tunes a resistance of a fuse formed between the first and second fuse contacts.

Abstract: An integrated short channel omega gate FinFET and long channel FinFET semiconductor device includes a first fin and second fin on a buried oxide (BOX) layer. The BOX layer includes a fin well outside and substantially adjoining a footprint of a respective fin. A first gate dielectric layer is upon the second fin and a second gate dielectric layer is upon the first dielectric layer. The BOX layer further includes an undercut below the first fin that exposes a portion of a bottom surface of the first fin. An omega-gate is around the first fin. A tri-gate is upon the second gate dielectric layer over the second fin.

Abstract: A method is presented for forming a wrap around contact. The method includes forming a p-type epitaxial region and an n-type epitaxial region over a substrate, forming a dielectric pillar between the p-type epitaxial region and the n-type epitaxial region, depositing sacrificial liners around both the p-type epitaxial region and the n-type epitaxial region, and depositing an inter-layer dielectric (ILD). The method further includes forming trenches in the ILD extending into the sacrificial liners, wherein the trenches are vertically aligned with the p-type epitaxial region and the n-type epitaxial region, removing the sacrificial liners to define irregular-shaped openings exposing the p-type epitaxial region and the n-type epitaxial region, and filling the irregular-shaped openings with a conductive material defining the wrap around contact.

Abstract: A structure that includes a substrate and a nanofilter formed on the substrate, wherein the nanofilter is adapted to allow nanoparticles of a predetermined size to pass through the nanofilter.

Abstract: A semiconductor device includes one or more lower transistors and includes one or more upper transistors. The upper transistor(s) may be forksheet transistors or cells separated by a forksheet pillar. The upper transistor(s) are stacked vertically above respective lower transistor(s). The device width of the upper transistor(s) is relatively small compared to the device width of the lower transistor. As such, adequate space exists for both a lower source/drain (S/D) contact and an upper S/D contact to exist in a same YY cross sectional plane. The lower S/D contact may bypass the upper transistor and contact the underlying lower S/D region there below.