Abstract: A semiconductor structure including a substrate, a first stack of channel layers on the substrate and a second stack of channel layers vertically aligned above the first stack. The width of the first is greater than the second. Additionally, the first channel layers can be cladded with germanium while the second channel layers can have a dog-bone shape.

Abstract: A semiconductor device comprising a first nanosheet located on top of a substrate, wherein the first nanosheet is tapered the Y-direction to have a width W1 and the first nanosheet is tapered in the X-direction to have a length L1. A second nanosheet located on top of the first nanosheet, wherein the second nanosheets is tapered in the Y-direction to have a width W2 and the first nanosheet is tapered in the X-direction to have a length L2. Wherein the widths W1 and W2 are different from each other and the lengths L1 and L2 are different from each other and wherein the substrate includes a tapered surface in the Y-direction.

Abstract: Embodiments of present invention provide a semiconductor structure, which includes a first FET layer having a first and a second FET with a first and a second S/D region respectively; a second FET layer having a third and a fourth FET with a third and a fourth S/D region respectively, the second FET layer being on top of the first FET layer; a first deep via extending from a top level that is at or above a top surface of the third and the fourth S/D region to a bottom level that is at or below a bottom surface of the first and the second S/D region, the first deep via having an inverted trapezoidal shape; and a second deep via extending at least from the top level to the bottom level, the second deep via having a trapezoidal shape. A method of manufacturing the same is also provided.

Abstract: A computer-implemented method (CIM), according to one embodiment, includes enacting a first policy. Enacting the first policy includes collecting location data and camera data for a first user device. Enacting the first policy further includes causing a predetermined machine learning model to use the data to determine whether the first user device is authorized to perform an image capture at a current location of the first user device. In response to a determination that an output of the predetermined machine learning model indicates that the first user device is not authorized to perform the image capture at the current location, the first user device is restricted from performing the image capture. In response to a determination that the output of the predetermined machine learning model indicates that the first user device is authorized to perform the image capture, the first user device is allowed to perform the image capture.

Abstract: A semiconductor device that includes a substrate, a crystalline bottom electrode layer on an upper side of the semiconductor substrate, a conductive crystalline metal layer above the crystalline bottom electrode layer, and a conductive oxide layer above the conductive crystalline metal layer. The conductive oxide layer has a low resistance. The semiconductor device also includes a magnetic tunnel junction (MTJ) above the conductive crystalline metal layer, the MTJ including a tunnel barrier layer, a free layer on a first side of the tunnel barrier layer and a reference layer on a second side of the tunnel barrier layer opposite the first side.

Abstract: Embodiments of the present invention include a phase change memory (PCM) array. The PCM array may include a plurality of PCM cells. Each PCM cell in the plurality of PCM cells may include a top electrode, a resistive element, and a bottom electrode. The PCM array may also include a global heater surrounding the plurality of PCM cells having a thermally conductive material contacting each of the plurality of PCM cells. The global heater may be configured to receive an electric signal to heat the plurality of PCM cells simultaneously.

Abstract: A computer-implemented method, a computer program product, and a computer system for phygital integration in commerce-based checkout experiences. A computer aggregates data from one or more personal devices of a user and data from one or more biosensors of the user. A computer trains a machine learning model on features extracted from aggregated data. A computer uses the machine learning model to predict purchase preferences of the user and to generate for the user personalized recommendations, promotions, and loyalty rewards. A computer generates notifications about the personalized recommendations, promotions, and loyalty rewards. A computer transmits the notifications to the one or more personal devices. A computer monitors interactions of the user with the personalized recommendations, promotions, and loyalty rewards.

Abstract: A semiconductor integrated circuit (IC) device includes a diffusion break region that has a diffusion break dielectric adjacent to or between diffusion break isolation wall(s). The diffusion break region may separate adjacent transistors. The diffusion break isolation wall(s) may include respective retained portions of a backside spacer, a bottom isolation, respective inner spacers, and residual active semiconductor nanolayers. The diffusion break region may be fabricated by depositing a diffusion break dielectric within a diffusion break opening against the diffusion break isolation wall(s).

Abstract: A semiconductor device comprises a plurality of gate structures stacked with a plurality of core channel layers comprising a first semiconductor material, and a plurality of cladding channel layers disposed around the plurality of gate structures and comprising a second semiconductor material different from the first semiconductor material. A source/drain region is disposed on a side of the plurality of gate structures and the plurality of core channel layers. Respective ones of a plurality of buffer semiconductor layers are disposed between respective ones of the plurality of core channel layers and the source/drain region.

Abstract: A semiconductor structure includes a first source/drain region having a first sidewall shape and a second source/drain region having a second sidewall shape, the second sidewall shape being different than the first sidewall shape. At least one of the first source/drain region and the second source/drain region is disposed over a placeholder layer. The first source/drain region may be an n-type source/drain region and the second source/drain region may be a p-type source/drain region, and the first sidewall shape may be diamond-shaped sidewalls and the second sidewall shape may be trench-confined sidewalls.

Abstract: A semiconductor device includes a PCM stack that includes bottom electrode liner over a lower heater. The bottom electrode liner has a top-down view plus (+) geometry with a ‘horizontal’ portion being orthogonal to a ‘vertical’ portion. An airgap is formed within the PCM stack in an area located adjacent and between the ‘horizontal’ portion and the ‘vertical’ portion. The airgap has a substantially smaller dielectric constant than the surrounding PCM stack material(s). Therefore, the airgap may effectively reduce the amount of current that leaks from the PCM stack when flowing from the bottom electrode liner to a top contact or top electrode. Further, the airgap may allow for expansion of the surrounding PCM stack material(s) that may result from the heating of the PCM stack.

Abstract: A stacked field effect transistor (stacked-FET) device includes a first layer comprising at least one first layer transistor structure comprising a plurality of first layer terminals, a diffusion break dielectric fill region adjacent to one of the first layer terminals, a second layer overlying and adjacent to the first layer and comprising at least one second layer transistor structure comprising a plurality of second layer terminals, and a contact wiring between the first layer and the second layer passing through the diffusion break dielectric fill region of the first layer and connecting with one of the second layer terminals.

Abstract: A semiconductor device is provided that includes a local passthrough interconnect structure present in a non-active device region of the device. A dielectric fill material structure is located between the local passthrough interconnect structure and a functional gate structure that is present in an active device region that is laterally adjacent to the non-active device region. The semiconductor device has reduced capacitance (and thus circuit speed is not compromised) as compared to an equivalent device in which a metal-containing sacrificial gate structure is used instead of the dielectric fill material structure.

Abstract: Arrays of PCM devices and techniques for fabrication thereof having an integrated resistor formed during heater patterning for uniform voltage drop amongst the PCM devices are provided. In one aspect, a PCM device includes: at least one PCM cell including a phase change material disposed on a heater; and at least one resistor in series with the at least one PCM cell, wherein the at least one resistor includes a same combination of materials as the heater. A memory array and a method of forming a PCM device are also provided.

Abstract: A biosensor device is provided. The biosensor includes an amplifying bipolar junction transistor (BJT) and a sensing BJT defining a sensing trench. The sensing BJT and the amplifying BJT are coupled to form a Sziklai pair with an emitter of the sensing BJT connected to a collector of the amplifying BJT and a collector of the sensing BJT connected to a base of the amplifying BJT.

Abstract: A microelectronic structure that includes a nanosheet transistor. The nanosheet transistor includes a source epi and a drain epi. A first inner spacer located adjacent to the source epi, where the first inner spacer has a first width as measured perpendicular to a gate direction. A second inner spacer located adjacent to the drain epi. The second inner spacer has second width as measured perpendicular to the gate direction. The first width and the second width are different.

Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

Abstract: Embodiments of the present disclosure include a semiconductor structure including a transistor. The transistor includes a channel region separating a first epitaxial region from a second epitaxial region. A conductive piece is embedded in the first epitaxial region.

Abstract: A semiconductor device includes a first-type transistor, a second-type transistor, and a t-shaped backbone. The first-type transistor includes a first-type source/drain and the second-type transistor includes a second-type source/drain. The t-shaped backbone includes a wall and a sub-wall. The wall separates the first-type transistor and the second-type source/drain. The sub-wall extends from the wall and into the second-type source/drain.

Abstract: Embodiments of the invention are directed to a computer-implemented method that includes accessing, using a processor system, a three-dimensional (3D) model of a device-under-design (DUD). The processor system is used to receive a first design operation associated with the 3D model of the DUD. A collaboration dependency model is used to make a prediction of a dependency relationship between the first design operation and a second design operation.