Abstract: A semiconductor device includes a first-type transistor, a second-type transistor, and a t-shaped backbone. The first-type transistor includes a first-type source/drain and the second-type transistor includes a second-type source/drain. The t-shaped backbone includes a wall and a sub-wall. The wall separates the first-type transistor and the second-type source/drain. The sub-wall extends from the wall and into the second-type source/drain.

Abstract: A semiconductor integrated circuit (IC) device includes a diffusion break region that has a diffusion break dielectric adjacent to or between diffusion break isolation wall(s). The diffusion break region may separate adjacent transistors. The diffusion break isolation wall(s) may include respective retained portions of a backside spacer, a bottom isolation, respective inner spacers, and residual active semiconductor nanolayers. The diffusion break region may be fabricated by depositing a diffusion break dielectric within a diffusion break opening against the diffusion break isolation wall(s).

Abstract: A magnetic tunnel junction (MTJ) stack structure includes a reference layer; a tunnel barrier; and a free layer that comprises three distinct materials. All of the three distinct materials in the free layer are magnetic material. One of the three distinct materials in the free layer is a C38 structure alloy.

Abstract: Embodiments of present invention provide a magnetoresistive random-access-memory (MRAM). The MRAM includes a reference layer; a tunnel barrier layer of magnesium-oxide (MgO); and a free layer, where the free layer includes a first cobalt-iron-boron (CoFeB) layer on top of the tunnel barrier layer; a spacer layer on top of the first CoFeB layer; a second CoFeB layer on top of the spacer layer; and a capping layer of MgO on top of the second CoFeB layer. Additionally, the first and the second CoFeB layer are substantially depleted of boron (B) to include respectively a first region adjacent to the tunnel barrier layer and the capping layer respectively and a second region adjacent to the spacer layer, where the first regions of the first and the second CoFeB layer include crystallized cobalt-iron (CoFe) and the second regions of the first and the second CoFeB layer include amorphous CoFe alloy.

Abstract: A semiconductor device includes a transistor having a source/drain region and a contact disposed on the source/drain region. The semiconductor device further includes a via extending from the contact along a side of the source/drain region to a power element. The contact and the via each comprise a plurality of conductive materials.

Abstract: Methods and systems for fabricating an object include fabricating a three-dimensional (3D) structure using additive processing. A defect is detected in the 3D structure. A location of the 3D structure is identified that corresponds to a 3D space occupied by the defect. Material is removed from the location of the 3D structure using subtractive processing to correct the defect.

Abstract: Systems and methods are provided for intelligent alloy selection for five dimensional printing. Structural weaknesses in a target model for five dimensional (5D) printing can be determined, with an artificial intelligence-based controller (AIC), based on strength requirement thresholds of an identified strength requirement of the target model. An alloy infusion strategy can be determined, with the AIC, based on the identified strength requirements and the structural weaknesses in the target model to determine an additive material. The additive material can be infused into a base filament material for the target model to generate an alloy by generating instruction commands for a smart filament extruder based on the alloy infusion strategy while 5D printing. The alloy infusion strategy and the identified strength requirement can be adjusted based on strength ameliorating parameters determined from monitored operational parameters while 5D printing to update the additive material for infusing.

Abstract: A semiconductor structure includes a source/drain region having a recessed portion. The semiconductor structure further includes a metal contact having a first portion and a second portion. The first portion of the metal contact has a first width and the second portion of the metal contact has a second width greater than the first width. At least a portion of the second portion of the metal contact is disposed in the recessed portion of the source/drain region.

Abstract: Power consumption optimization of IoT devices is provided. A device upgrade plan is generated outlining a sequence of actions for AI chip upgrade of a number of IoT devices based on assessment of hardware and software specification information corresponding to the number of IoT devices against requirements for the AI chip upgrade. A set of AI chip configurations is run in a simulation environment based on operational parameters corresponding to the number of IoT devices to identify a best AI chip configuration that delivers a lowest power consumption for the number of IoT devices while meeting defined performance benchmarks. At least one of a set of firmware updates, a set of driver software, and a set of configuration settings is transmitted to one or more of the number of IoT devices for the AI chip upgrade in accordance with the device upgrade plan based on the best AI chip configuration.

Abstract: A computer-implemented method, a computer program product, and a computer system for phygital integration in commerce-based checkout experiences. A computer aggregates data from one or more personal devices of a user and data from one or more biosensors of the user. A computer trains a machine learning model on features extracted from aggregated data. A computer uses the machine learning model to predict purchase preferences of the user and to generate for the user personalized recommendations, promotions, and loyalty rewards. A computer generates notifications about the personalized recommendations, promotions, and loyalty rewards. A computer transmits the notifications to the one or more personal devices. A computer monitors interactions of the user with the personalized recommendations, promotions, and loyalty rewards.

Abstract: A high bandwidth memory is provided. The high bandwidth memory includes a region of dynamic random access memory devices, a region of non-volatile memory devices adjacent to the region of dynamic random access memory devices, and a region of logic devices adjacent to both the region of dynamic random access memory devices and the region of non-volatile memory devices.

Abstract: A magnetic tunnel junction (MTJ) stack structure includes a reference layer, a tunnel barrier, and a free layer that includes multiple separate materials including a first material that exhibits greater than 100% tunnel magnetoresistance when paired with the tunnel barrier, and an ordered alloy material coupled to the first material. At least one part of the free layer is a ferromagnetic material.

Abstract: A semiconductor device includes a semiconductor substrate and a field effect transistor disposed on the semiconductor substrate. The field effect transistor includes a vertical fin defining a longitudinal length along a first axis, a width along a second axis and a vertical height along a third axis. The vertical fin includes source and drain regions separated by a gate region and a gate structure over the gate region. The gate structure includes a dipole layer and a gate electrode layer over the dipole layer. A first longitudinal section of the gate structure includes the dipole layer and a second longitudinal section of the gate structure is devoid of the dipole layer.

Abstract: A semiconductor structure includes a bottom MTJ stack with a bottom fixed layer, a bottom barrier layer, and a bottom free layer. The semiconductor structure also includes a top MTJ stack with a top fixed layer, a top barrier layer, and a top free layer. Additionally, the semiconductor structure also includes a spin-Hall effect (SHE) rail with a dielectric, a top heavy metal layer, and a bottom heavy metal layer.

Abstract: Fork sheet FET devices with airgap isolation are provided. In one aspect, a fork sheet FET device includes: at least a first nanosheet FET and a second nanosheet FET; and a dielectric pillar disposed directly between the first nanosheet FET and the second nanosheet FET, wherein the dielectric pillar includes an airgap. For instance, the first nanosheet FET and the second nanosheet FET can have nanosheets that extend horizontally on opposite sides of the dielectric pillar. A method of forming a fork sheet FET device having airgap isolation is also provided.

Abstract: A biosensor device is provided. The biosensor includes an amplifying bipolar junction transistor (BJT) and a sensing BJT defining a sensing trench. The sensing BJT and the amplifying BJT are coupled to form a Sziklai pair with an emitter of the sensing BJT connected to a collector of the amplifying BJT and a collector of the sensing BJT connected to a base of the amplifying BJT.

Abstract: A method of fabrication a semiconductor device includes forming a stack of semiconductor nanosheets on a semiconductor substrate, and performing a nanosheet fin reveal cut process that etches the stack of semiconductor nanosheets to from a first nanosheet fin and a second nanosheet fin. The first and second nanosheet fins are separated by one another by a distance defining an isolation region. The method further includes forming an isolation wall in the isolation region, where the isolation wall extends continuously from a wall based contacting the semiconductor substrate to an opposing wall upper surface. The method further includes forming an electrically conductive gate stack that surrounds the first nanosheet fin, the second nanosheet fin, and the isolation wall, and forming a gate interlayer dielectric (ILD) on an upper surface the electrically conductive gate stack such that the wall upper surface contacts the gate ILD.

Abstract: A semiconductor device includes one or more lower transistors and includes one or more upper transistors. The upper transistor(s) may be forksheet transistors or cells separated by a forksheet pillar. The upper transistor(s) are stacked vertically above respective lower transistor(s). The device width of the upper transistor(s) is relatively small compared to the device width of the lower transistor. As such, adequate space exists for both a lower source/drain (S/D) contact and an upper S/D contact to exist in a same YY cross sectional plane. The lower S/D contact may bypass the upper transistor and contact the underlying lower S/D region there below.

Abstract: Embodiments of the invention are directed to a method of forming an integrated circuit (IC). The method includes performing fabrication operations that form the IC. The fabrication operations include forming a channel fin. A gate structure is formed along a sidewall surface of the channel fin. The gate structure includes a conductive gate having an L-shape profile, and the L-shape profile includes a conductive gate foot region. The conductive gate foot region is replaced with a dielectric foot region.

Abstract: A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth.