Patents by Inventor Alexander Reznicek

Alexander Reznicek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250107453
    Abstract: A magnetic tunnel junction device is provided. The magnetic tunnel junction device includes a seed layer, and a free layer structure on the seed layer. The free layer structure includes a first free layer, a spacer layer formed on the first free layer, and a second free layer formed on the spacer layer. The first and second free layers each include an ordered magnetic alloy.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 27, 2025
    Inventors: Guohan Hu, Matthias Georg Gottwald, Alexander Reznicek, Gukcheon Kim
  • Patent number: 12262552
    Abstract: Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a first set of nanosheets and a second set of nanosheets on top of the first set of nanosheets, wherein the first set of nanosheets has an uppermost nanosheet and the second set of nanosheets has a lowermost nanosheet, the lowermost nanosheet being separated from the uppermost nanosheet by a first gap; forming a conformal liner covering the first set of nanosheets and the first gap; covering a first portion of the conformal liner at the first gap with a protective stud; selectively removing a second portion of the conformal liner from end surfaces of the first set of nanosheets; and forming source/drain at the end surfaces of the first set of nanosheets. A structure formed thereby is also provided.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: March 25, 2025
    Assignee: International Business Machines Corporation
    Inventors: Tsung-Sheng Kang, Daniel Schmidt, Alexander Reznicek, Ruilong Xie
  • Publication number: 20250098245
    Abstract: A semiconductor device comprises a stacked structure, the stacked structure comprising a plurality of gate structures alternately stacked with a plurality of channel layers. At least one epitaxial source/drain region disposed on a side of the stacked structure, and the stacked structure is disposed on at least one dielectric layer. A portion of the at least one epitaxial source/drain region is disposed in the at least one dielectric layer.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Inventors: Sagarika Mukesh, Alexander Reznicek, Tao Li, Ruilong Xie
  • Publication number: 20250098229
    Abstract: A semiconductor device comprises at least one epitaxial source/drain region, and a dielectric layer disposed in a trench in the at least one epitaxial source/drain region. The dielectric layer comprises one of a material with a negative coefficient of thermal expansion and a material with a positive coefficient of thermal expansion.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 20, 2025
    Inventors: Sagarika Mukesh, Ruilong Xie, Alexander Reznicek, Tsung-Sheng Kang
  • Patent number: 12255106
    Abstract: A method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices without patterning between nanosheet channels. The method includes forming a first set of nanosheet stacks having a first intersheet spacing, forming a second set of nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing, depositing a high-k (HK) layer within the first and second nanosheet stacks, depositing a material stack that, when annealed, creates a crystallized HK layer in the first set of nanosheet stacks and an amorphous HK layer in the second nanosheet stacks, depositing a dipole material, and selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the different gate threshold voltages for the plurality of FET devices.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: March 18, 2025
    Assignee: INTERATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jingyun Zhang, Takashi Ando, ChoongHyun Lee, Alexander Reznicek
  • Patent number: 12245530
    Abstract: A ring-shaped heater, system, and method to gradually change the conductance of the phase change memory through a concentric ring-shaped heater. The system may include a phase change memory. The phase change memory may include a bottom electrode. The phase change memory may also include a ring-shaped heater patterned on top of the bottom electrode, the ring-shaped heater including: a plurality of concentric conductive heating layers, and a plurality of insulator spacers, where each insulator spacer separates each conductive heating layer. The phase change memory may also include a phase change material proximately connected to the ring-shaped heater. The phase change memory may also include a top electrode proximately connected to the phase change material.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: March 4, 2025
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Carl Radens, Juntao Li, Ruilong Xie, Praneet Adusumilli, Oscar van der Straten, Alexander Reznicek
  • Patent number: 12237328
    Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: February 25, 2025
    Assignee: Adeia Semiconductor Solutions LLC
    Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
  • Patent number: 12236539
    Abstract: Methods, systems, and a computer program product are disclosed. The first method includes obtaining virtual session data in real time, identifying a positional utterance in the virtual session data, and generating a positional insight for the positional utterance. The first method also includes generating a best-practices recommendation based on the positional insight. The second method includes obtaining virtual session data, identifying positional utterances in the virtual session data, and generating positional insights for each of the positional utterances. The second method also includes selecting each of the positional insights having confidence scores above a threshold score and generating best-practices recommendations based on the selected positional insights.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: February 25, 2025
    Assignee: International Business Machines Corporation
    Inventors: Martin G. Keen, Jeremy R. Fox, Alexander Reznicek, Bahman Hekmatshoartabari
  • Patent number: 12230676
    Abstract: A nanosheet device includes a bottom dielectric isolation formed by a first portion of a high-k dielectric layer above a semiconductor substrate, a spacer material above the first portion of the high-k dielectric layer and a second portion of the high-k dielectric layer above the spacer material. A sequence of semiconductor channel layers are stacked perpendicularly to the semiconductor substrate above the bottom dielectric isolation and are separated by and vertically aligned with a metal gate stack. Source/drain regions extend laterally from opposite ends of the semiconductor channel layers with a bottom surface of the source/drain regions being in direct contact with the bottom dielectric isolation for electrically isolating the source/drain regions from the semiconductor substrate.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: February 18, 2025
    Assignee: International Business Machines Corporation
    Inventors: Xin Miao, Jingyun Zhang, Alexander Reznicek, Choonghyun Lee
  • Patent number: 12225835
    Abstract: Embodiments of the invention are directed to a structure that includes a resistive switching device (RSD). The RSD includes a first terminal having an outer sidewall surface; a second terminal; an active region having a switchable conduction state; and a first protective layer on the outer sidewall surface of the first terminal.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: February 11, 2025
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Ruilong Xie, Alexander Reznicek, Pouya Hashemi
  • Publication number: 20250045976
    Abstract: Rendering an emotional state of a virtual reality headset user is provided. An emotion feature vector predicting a current emotional state of a user of a virtual reality headset is mapped to a matching set of existing avatar vectors a mapping function. A best matching avatar vector is selected from the matching set of existing avatar vectors based on determining that values of the best matching avatar vector most closely match values of the emotion feature vector predicting the current emotional state of the user of the virtual reality headset. An avatar associated with the user is rendered in a metaverse consistent with the current emotional state of the user of the virtual reality headset based on the best matching avatar vector to the emotion feature vector predicting the current emotional state of the user.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Jeremy R. Fox, Alexander Reznicek, Bahman Hekmatshoartabari, Martin G. Keen
  • Publication number: 20250044119
    Abstract: The present inventive concept provides for a method of unique hiking interaction via IoT data assimilation. The method includes obtaining health data for a user and location data for a location that includes at least one activity trail. Health features are extracted from the health data and terrain features are extracted from the location data. The extracted health features and the extracted terrain features are analysed and mapped. The extracted health features include biometric measurements from at least one IoT device and the extracted terrain features include characteristics of the at least one activity trail. A unique activity experience is calculated for the user to perform a preselected activity on the at least one activity trail based at least in part on the analysed and mapped extracted health features and the extracted terrain features.
    Type: Application
    Filed: August 2, 2023
    Publication date: February 6, 2025
    Inventors: Jeremy R. Fox, Alexander Reznicek, Martin G. Keen, Bahman Hekmatshoartabari
  • Publication number: 20250044862
    Abstract: A computer-implemented method, a computer system and a computer program product recommend an optimal break for a user. The method includes capturing activity data for the user from an environment using a device. The method also includes obtaining prior activity data related to the user and identifying a preferred break type for the user, wherein the preferred break type for the user is associated with a prior activity of the user. In addition, the method includes determining that the user needs a break from a current activity based on the activity data. The method further includes generating a break recommendation for the user, wherein the break recommendation associates the preferred break type for the user with the current activity in the activity data. Lastly, the method includes displaying the break recommendation to the user.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Martin G. Keen, Jeremy R. Fox, Bahman Hekmatshoartabari, Alexander Reznicek
  • Patent number: 12219884
    Abstract: A phase change memory, system, and method for gradually changing the conductance and resistance of the phase change memory while preventing resistance drift. The phase change memory may include a phase change material. The phase change memory may also include a bottom electrode. The phase change memory may also include a heater core proximately connected to the bottom electrode. The phase change memory may also include a set of conductive rings surrounding the heater core, where the set of conductive rings comprises one or more conductive rings, and where the set of conductive rings are proximately connected to the phase change material. The phase change memory may also include a set of spacers, where a spacer, from the set of spacers, separates a portion of a conductive ring, from the set of conductive rings, from the heater core.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: February 4, 2025
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Carl Radens, Juntao Li, Ruilong Xie, Praneet Adusumilli, Oscar van der Straten, Alexander Reznicek, Zuoguang Liu, Arthur Gasasira
  • Publication number: 20250040444
    Abstract: Embodiments of present invention provide a magnetoresistive random-access-memory (MRAM). The MRAM includes a reference layer; a tunnel barrier layer of magnesium-oxide (MgO); and a free layer, where the free layer includes a first cobalt-iron-boron (CoFeB) layer on top of the tunnel barrier layer; a spacer layer on top of the first CoFeB layer; a second CoFeB layer on top of the spacer layer; and a capping layer of MgO on top of the second CoFeB layer. Additionally, the first and the second CoFeB layer are substantially depleted of boron (B) to include respectively a first region adjacent to the tunnel barrier layer and the capping layer respectively and a second region adjacent to the spacer layer, where the first regions of the first and the second CoFeB layer include crystallized cobalt-iron (CoFe) and the second regions of the first and the second CoFeB layer include amorphous CoFe alloy.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 30, 2025
    Inventors: MATTHIAS GEORG GOTTWALD, Guohan Hu, Virat Vasav Mehta, John Bruley, Alexander Reznicek
  • Patent number: 12191352
    Abstract: Embodiments of the invention are directed to a transistor device that includes a channel stack having stacked, spaced-apart, channel layers. A first source or drain (S/D) region is communicatively coupled to the channel stack. A tunnel extends through the channel stack, wherein the tunnel includes a central region and a first set of end regions. The first set of end regions is positioned closer to the first S/D region than the central region is to the first S/D region. A first type of work-function metal (WFM) is formed in the first set of end regions, the first WFM having a first work-function (WF). A second type of WFM is formed in the central region, the second type of WFM having a second WF, wherein the first WF is different than the second WF.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: January 7, 2025
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Ruilong Xie, Pouya Hashemi, Alexander Reznicek
  • Publication number: 20250006780
    Abstract: A pillar or trench structure in a substrate includes vertical portions and one or more indented cavities in a sidewall between the vertical portions. The indented cavities are partial undercuts substantially traverse to the vertical portions pillar structure, or separate undercuts attached to an anchor. A higher capacitance density is achieved through the layering of multiple conductive contact layers and insulating layers in the undercuts and the vertical portions of the pillar or trench structure.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: Joshua M. Rubin, Alexander Reznicek, Theodorus E. Standaert, Koichi Motoyama
  • Patent number: 12183826
    Abstract: A semiconductor structure, and a method of making the same includes a fin extending upward from a substrate, an epitaxially grown bottom source/drain region in direct contact with the substrate and a bottom portion of the fin. A bottom surface and sidewalls of a metal silicide layer are in direct contact with the epitaxially grown bottom source/drain region. A bottom spacer is located above and in direct contact with the metal silicide layer and a portion of the epitaxially grown bottom source/drain region not covered by the metal silicide layer, the bottom spacer surrounding the fin.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: December 31, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Choonghyun Lee, Soon-Cheon Seo, Injo Ok, Alexander Reznicek
  • Publication number: 20240423827
    Abstract: A bite guard configured to conform to teeth of a patient, and an array of sensor assemblies encapsulated in the bite guard, where the array of sensor assemblies is distributed throughout the bite guard, and where each sensor assembly includes a piezo pressure sensor.
    Type: Application
    Filed: June 20, 2023
    Publication date: December 26, 2024
    Inventors: Jeremy R. Fox, Martin G. Keen, Alexander Reznicek, Bahman Hekmatshoartabari
  • Publication number: 20240429284
    Abstract: A semiconductor structure including a dielectric bar arranged between and physically separating a first source drain region from a second source drain region, a first silicide liner directly beneath the first source drain region, and second silicide liner directly beneath the second source drain region, where the first silicide liner is a different material than the second silicide liner.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 26, 2024
    Inventors: Ruilong Xie, Tsung-Sheng Kang, Alexander Reznicek, Sagarika Mukesh