SEMICONDUCTOR DEVICE WITH CONNECTING STRUCTURE AND METHOD FOR FABRICATING THE SAME
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, and a first connecting structure including a first connecting insulating layer positioned on the first semiconductor structure, a plurality of first connecting contacts positioned in the first connecting insulating layer, and a plurality of first supporting contacts positioned in the first connecting insulating layer. A top surface of the first connecting insulating layer, top surfaces of the plurality of first connecting contacts, and top surfaces of the plurality of first supporting contacts are substantially coplanar. Bottom surfaces of the plurality of first connecting contacts contact a top surface of the first semiconductor structure.
The present disclosure relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly, to a semiconductor device with a connecting structure and a method for fabricating the semiconductor device with the connecting structure.
DISCUSSION OF THE BACKGROUNDSemiconductor devices are used in a variety of electronic applications, such as personal computers, cellular telephones, digital cameras, and other electronic equipment. The dimensions of semiconductor devices are continuously being scaled down to meet the increasing demand of computing ability. However, a variety of issues arise during the down-scaling process, and such issues are continuously increasing in quantity and complexity. Therefore, challenges remain in achieving improved quality, yield, performance, and reliability and reduced complexity.
This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.
SUMMARYOne aspect of the present disclosure provides a semiconductor device including a first semiconductor structure, and a first connecting structure including a first connecting insulating layer positioned on the first semiconductor structure, a plurality of first connecting contacts positioned in the first connecting insulating layer, and a plurality of first supporting contacts positioned in the first connecting insulating layer. A top surface of the first connecting insulating layer, top surfaces of the plurality of first connecting contacts, and top surfaces of the plurality of first supporting contacts are substantially coplanar. Bottom surfaces of the plurality of first connecting contacts contact a top surface of the first semiconductor structure.
In some embodiments, the plurality of first connecting contacts have a thickness greater than a thickness of the plurality of first supporting contacts.
In some embodiments, the first semiconductor structure includes a first substrate positioned below the first connecting structure and a first interconnection structure positioned between the first substrate and the first connecting structure. The first connecting insulating layer is positioned on the first interconnection structure.
In some embodiments, the first interconnection structure includes a first insulating layer positioned on the first substrate and a plurality of first conductive features positioned in the first insulating layer. The bottom surfaces of the first connecting contacts contact top surfaces of the plurality of first conductive features coplanar with a top surface of the first insulating layer.
In some embodiments, a semiconductor device includes a second semiconductor structure positioned on the first connecting structure. The top surfaces of the plurality of first connecting contacts contact a bottom surface of the second semiconductor structure.
In some embodiments, the second semiconductor structure includes a second interconnection structure positioned on the first connecting structure and a second substrate positioned on the second interconnection structure. The second interconnection structure includes a second insulating layer positioned on the first connecting structure and a plurality of second conductive features positioned in the second insulating layer. The top surfaces of the plurality of first connecting contacts contact bottom surfaces of the plurality of second conductive features coplanar with a bottom surface of the second insulating layer.
In some embodiments, the second interconnection structure includes a plurality of guard rings positioned in the second insulating layer. Bottom surfaces of the plurality of guard rings contact the top surfaces of the plurality of first supporting contacts.
In some embodiments, a semiconductor device includes a plurality of first liners positioned on sidewalls of the plurality of first connecting contacts and the bottom surfaces of the plurality of first connecting contacts.
In some embodiments, a semiconductor device includes a first porous layer positioned between the first connecting insulating layer and the second insulating layer, between the first connecting insulating layer and the plurality of first connecting contacts, and between the first connecting insulating layer and the plurality of first supporting contacts. A porosity of the first porous layer is between about 25% and about 100%.
In some embodiments, a semiconductor device includes a plurality of first liners positioned between the first porous layer and the plurality of first connecting contacts and between the first porous layer and the first supporting contacts.
In some embodiments, a semiconductor device includes a through substrate via positioned in the second substrate.
In some embodiments, the first connecting insulating layer includes a first bottom insulating layer positioned on the top surface of the first semiconductor structure, a first middle insulating layer positioned on the first bottom insulating layer, and a first top insulating layer positioned on the first middle insulating layer. The plurality of first connecting contacts penetrate the first bottom insulating layer, the first middle insulating layer, and the first top insulating layer, and the plurality of first supporting contacts are positioned in the first top insulating layer.
In some embodiments, a semiconductor device includes a second connecting structure positioned on the first connecting structure, and a second semiconductor structure positioned on the second connecting structure. The second connecting structure includes a second connecting insulating layer positioned on the first connecting structure, a plurality of second connecting contacts positioned in the second connecting insulating layer, and a plurality of second supporting contacts positioned in the second connecting insulating layer. Bottom surfaces of the plurality of second connecting contacts contact the top surfaces of the plurality of first connecting contacts.
In some embodiments, a cross-sectional profile of sidewalls of the plurality of first connecting contacts is slanted.
Another aspect of the present disclosure provides a method for fabricating a semiconductor device including providing a first semiconductor structure, and forming a first connecting structure including a first connecting insulating layer on the first semiconductor structure, a plurality of first connecting contacts in the first connecting insulating layer, and a plurality of first supporting contacts in the first connecting insulating layer.
In some embodiments, the first connecting insulating layer includes a first bottom insulating layer formed on the first semiconductor structure, a first middle insulating layer formed on the first bottom insulating layer, and a first top insulating layer formed on the first middle insulating layer. The plurality of first connecting contacts penetrate the first top insulating layer, the first middle insulating layer, and the first bottom insulating layer, and the plurality of first supporting contacts are formed in the first top insulating layer.
In some embodiments, a method for fabricating a semiconductor device includes forming a layer of an energy-removable material on a top surface of the first connecting insulating layer, between the plurality of first connecting contacts and the first connecting insulating layer, and between the plurality of first supporting contacts and the first connecting insulating layer, and performing an energy treatment to turn the layer of energy-removable material into a first porous layer. A porosity of the first porous layer is between about 25% and about 100%.
In some embodiments, the energy-removable material includes a base material and a decomposable porogen material.
In some embodiments, the base material includes methylsilsesquioxane, low-dielectric materials, or silicon oxide.
In some embodiments, an energy source of the energy treatment is heat, light, or a combination thereof.
Due to the design of the semiconductor device of the present disclosure, multiple semiconductor devices may be connected together through the first connecting structure to provide more sophisticated functionality while occupying less volume. Therefore, the cost of the semiconductor device may be reduced, and the profit of the semiconductor device may be increased. In addition, the plurality of first supporting contacts may improve the bonding strength between the first connecting structure and the multiple semiconductor structures.
The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
It should be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected to or coupled to another element or layer, or intervening elements or layers may be present.
It should be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. Unless indicated otherwise, these terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component or a first section discussed below could be termed a second element, a second component or a second section without departing from the teachings of the present disclosure.
Unless the context indicates otherwise, terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to reflect this meaning. For example, items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.
In the present disclosure, a semiconductor device generally means a device which can function by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of the semiconductor device.
It should be noted that, in the description of the present disclosure, above (or up) corresponds to the direction of the arrow of the direction Z, and below (or down) corresponds to the opposite direction of the arrow of the direction Z.
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In some embodiments, the plurality of device elements may be disposed in a lower portion of the first insulating layer 105. The plurality of device elements may be disposed on the first substrate 101. The plurality of device elements may be, for example, bipolar junction transistors, metal-oxide-semiconductor field-effect transistors, diodes, system large-scale integration, flash memories, dynamic random-access memories, static random-access memories, electrically erasable programmable read-only memories, image sensors, micro-electro-mechanical systems, active devices, or passive devices. In some embodiments, portions of the device elements may be disposed in the first substrate 101. For example, source/drain regions of a metal-oxide-semiconductor field-effect transistor may be disposed in the first substrate 101. In some embodiments, the device elements may be electrically insulated from neighboring device elements by insulating structures such as shallow trench isolations.
It should be noted that, in the description of the present disclosure, a surface of an element (or a feature) located at the highest vertical level along the direction Z is referred to as a top surface of the element (or the feature). A surface of an element (or a feature) located at the lowest vertical level along the direction Z is referred to as a bottom surface of the element (or the feature).
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It should be noted that referring to an element as a “dummy” element means the element is electrically insulated from all of the device elements. In addition, when the semiconductor device is in operation, no exterior voltage or current will apply to the element.
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In some embodiments, the bottom surfaces of some of the plurality of first conductive contacts 111 and the bottom surface of the first insulating layer 105 may be substantially coplanar. In some embodiments, the bottom surfaces of some of the plurality of first conductive contacts 111, the bottom surfaces of some other of the plurality of first guard rings 115, the bottom surface of the first insulating layer 105, and the top surface of the first substrate 101 may be substantially coplanar. The plane consisting of the bottom surfaces of some of the plurality of first conductive contacts 111, the bottom surfaces of some other of the plurality of first guard rings 115, and the bottom surface of the first insulating layer 105 may be referred to as the bottom surface of the first interconnection structure 103.
The plurality of first conductive lines 107, the plurality of first conductive vias 109, and the plurality of first conductive contacts 111 may be formed of, for example, copper, aluminum, titanium, the like, or a combination thereof. The plurality of first conductive lines 107, the plurality of first conductive vias 109, and the plurality of first conductive contacts 111 may be formed of different materials, but are not limited thereto. The plurality of first barrier layers 113 may be formed of, for example, titanium nitride, tantalum nitride, titanium, tantalum, titanium tungsten, the like, or a combination thereof.
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It should be noted that, in the present disclosure, silicon oxynitride refers to a substance which contains silicon, nitrogen and oxygen and in which a proportion of oxygen is greater than that of nitrogen. Silicon nitride oxide refers to a substance which contains silicon, oxygen and nitrogen and in which a proportion of nitrogen is greater than that of oxygen.
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The second under bump metallization layer 227 may be a single layer structure or a stacked structure of multiple layers. For example, the second under bump metallization layer 227 may include a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially. The first conductive layer may serve as an adhesive layer for stably attaching the second conductive bump 229 to the second redistribution layer 225 and the second top passivation layer 223. For example, the first conductive layer may include at least one of titanium, titanium-tungsten, chromium, and aluminum. The second conductive layer may serve as a barrier layer for preventing a conductive material contained in the second conductive bump 229 from diffusing into the second redistribution layer 225 or the second top passivation layer 223. The second conductive layer may include at least one of copper, nickel, chromium-copper, and nickel-vanadium. The third conductive layer may serve as a seed layer for forming the second conductive bump 229 or as a wetting layer for improving wetting characteristics of the second conductive bump 229. The third conductive layer may include at least one of nickel, copper, and aluminum.
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In some embodiments, the plurality of first connecting contacts 409 may penetrate the first connecting insulating layer 401 along the direction Z and electrically connect the device elements of the first semiconductor structure 100 and the device elements of the second semiconductor structure 200 through some of the plurality of first conductive features and some of the plurality of second conductive features. In some embodiments, the first connecting insulating layer 401 may be a multi-layer structure including a first bottom insulating layer 403, a first middle insulating layer 405, and a first top insulating layer 407. The first bottom insulating layer 403 may be disposed on the top surface of the first interconnection structure 103. The first bottom insulating layer 403 may be an etch stop layer and may be formed of, for example, silicon nitride, silicon carbide, silicon oxide, low-k dielectric materials, extremely low-k dielectric materials, the like, or a combination thereof. The low-k dielectric materials may be, for example, carbon doped oxides. The extremely low-k dielectric materials may be, for example, porous carbon doped silicon oxide.
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The first porous layer 415 may include a skeleton and a plurality of empty spaces disposed throughout the skeleton. The plurality of empty spaces may connect to each other and may be filled with air. The skeleton may include, for example, silicon oxide, low-dielectric materials, or methylsilsesquioxane. The first porous layer 415 may have a porosity between 25% and 100%. It should be noted that, when the porosity is 100%, it means the first porous layer 415 includes only an empty space and the first porous layer 415 may be regarded as an air gap. In some embodiments, the porosity of the first porous layer 415 may be between 45% and 95%. The plurality of empty spaces of the first porous layer 415 may be filled with air. As a result, a dielectric constant of the first porous layer 415 may be significantly lower than a layer formed of, for example, silicon oxide. Therefore, the first porous layer 415 may significantly reduce the parasitic capacitance between the plurality of first connecting contacts 409 and the plurality of first supporting contacts 411. That is, the first porous layer 415 may significantly alleviate an interference effect between electrical signals induced or applied to the first connecting structure 400.
The energy-removable material may include a material such as a thermal decomposable material, a photonic decomposable material, an e-beam decomposable material, or a combination thereof. For example, the energy-removable material may include a base material and a decomposable porogen material that is sacrificially removed upon being exposed to an energy source.
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It should be noted that the terms “forming,” “formed” and “form” may mean and include any method of creating, building, patterning, implanting, or depositing an element, a dopant or a material. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusing, depositing, growing, implantation, photolithography, dry etching and wet etching.
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A series of photolithography processes, etching processes, deposition processes, and planarization processes may be performed to form the plurality of first connecting contacts 409, the plurality of first supporting contacts 411, and the plurality of first liners 413. The plurality of first connecting contacts 409 may be formed so as to penetrate the first top insulating layer 407, the first middle insulating layer 405, and the first bottom insulating layer 403 and may be electrically connected to some of the plurality of first conductive features adjacent to a top surface of the first interconnection structure 103. The plurality of first supporting contacts 411 may be formed in the first top insulating layer 407. The plurality of first liners 413 may be formed between the plurality of first connecting contacts 409 and the first connecting insulating layer 401, between the plurality of first supporting contacts 411 and the first connecting insulating layer 401, and between the plurality of first connecting contacts 409 and the some of the plurality of first conductive features adjacent to a top surface of the first interconnection structure 103.
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Alternatively, in another embodiment, the base material may be silicon oxide. The decomposable porogen material may include compounds including unsaturated bonds such as double bonds or triple bonds. During the energy treatment, the unsaturated bonds of the decomposable porogen material may cross-link with silicon oxide of the base material. As a result, the decomposable porogen material may shrink and generate empty spaces, with the base material remaining in place. The empty spaces may be filled with air so that a dielectric constant of the empty spaces may be significantly low. In some embodiments, the base material may be low-k dielectric materials.
In some embodiments, the energy-removable material 417 may include a relatively high concentration of the decomposable porogen material and a relatively low concentration of the base material, but is not limited thereto. For example, the energy-removable material 417 may include about 75% or greater of the decomposable porogen material, and about 25% or less of the base material. In another example, the energy-removable material 417 may include about 95% or greater of the decomposable porogen material, and about 5% or less of the base material. In another example, the energy-removable material 417 may include about 100% of the decomposable porogen material, and no base material. In another example, the energy-removable material 417 may include about 45% or greater of the decomposable porogen material, and about 55% or less of the base material.
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One aspect of the present disclosure provides a semiconductor device including a first semiconductor structure, and a first connecting structure including a first connecting insulating layer positioned on the first semiconductor structure, a plurality of first connecting contacts positioned in the first connecting insulating layer, and a plurality of first supporting contacts positioned in the first connecting insulating layer. A top surface of the first connecting insulating layer, top surfaces of the plurality of first connecting contacts, and top surfaces of the plurality of first supporting contacts are substantially coplanar. Bottom surfaces of the plurality of first connecting contacts contact a top surface of the first semiconductor structure.
Another aspect of the present disclosure provides a method for fabricating a semiconductor device including providing a first semiconductor structure, and forming a first connecting structure including a first connecting insulating layer on the first semiconductor structure, a plurality of first connecting contacts in the first connecting insulating layer, and a plurality of first supporting contacts in the first connecting insulating layer.
Due to the design of the semiconductor device of the present disclosure, the first semiconductor structure 100 and the second semiconductor structure 200 may be connected together through the first connecting structure 400 to provide more sophisticated functionality while occupying less volume. Therefore, the cost of the semiconductor device may be reduced, and the profit of the semiconductor device may be increased. In addition, the plurality of first supporting contacts 411 may improve the bonding strength between the first connecting structure 400 and the first semiconductor structure 100 or the second semiconductor structure 200.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, and steps.
Claims
1. A semiconductor device, comprising:
- a first semiconductor structure; and
- a first connecting structure comprising a first connecting insulating layer positioned on the first semiconductor structure, a plurality of first connecting contacts positioned in the first connecting insulating layer, and a plurality of first supporting contacts positioned in the first connecting insulating layer;
- wherein a top surface of the first connecting insulating layer, top surfaces of the plurality of first connecting contacts, and top surfaces of the plurality of first supporting contacts are substantially coplanar;
- wherein bottom surfaces of the plurality of first connecting contacts contact a top surface of the first semiconductor structure.
2. The semiconductor device of claim 1, wherein the plurality of first connecting contacts have a thickness greater than a thickness of the plurality of first supporting contacts.
3. The semiconductor device of claim 2, wherein the first semiconductor structure comprises a first substrate positioned below the first connecting structure and a first interconnection structure positioned between the first substrate and the first connecting structure, wherein the first connecting insulating layer is positioned on the first interconnection structure.
4. The semiconductor device of claim 3, wherein the first interconnection structure comprises a first insulating layer positioned on the first substrate and a plurality of first conductive features positioned in the first insulating layer, wherein the bottom surfaces of the first connecting contacts contact top surfaces of the plurality of first conductive features coplanar with a top surface of the first insulating layer.
5. The semiconductor device of claim 4, further comprising a second semiconductor structure positioned on the first connecting structure, wherein the top surfaces of the plurality of first connecting contacts contact a bottom surface of the second semiconductor structure.
6. The semiconductor device of claim 5, wherein the second semiconductor structure comprises a second interconnection structure positioned on the first connecting structure and a second substrate positioned on the second interconnection structure, wherein the second interconnection structure comprises a second insulating layer positioned on the first connecting structure and a plurality of second conductive features positioned in the second insulating layer, wherein the top surfaces of the plurality of first connecting contacts contact bottom surfaces of the plurality of second conductive features coplanar with a bottom surface of the second insulating layer.
7. The semiconductor device of claim 6, wherein the second interconnection structure comprises a plurality of guard rings positioned in the second insulating layer, wherein bottom surfaces of the plurality of guard rings contact the top surfaces of the plurality of first supporting contacts.
8. The semiconductor device of claim 7, further comprising a plurality of first liners positioned on sidewalls of the plurality of first connecting contacts and the bottom surfaces of the plurality of first connecting contacts.
9. The semiconductor device of claim 7, further comprising a first porous layer positioned between the first connecting insulating layer and the second insulating layer, between the first connecting insulating layer and the plurality of first connecting contacts, and between the first connecting insulating layer and the plurality of first supporting contacts, wherein a porosity of the first porous layer is between about 25% and about 100%.
10. The semiconductor device of claim 9, further comprising a plurality of first liners positioned between the first porous layer and the plurality of first connecting contacts and between the first porous layer and the first supporting contacts.
11. The semiconductor device of claim 10, further comprising a through substrate via positioned in the second substrate.
12. The semiconductor device of claim 1, wherein the first connecting insulating layer comprises a first bottom insulating layer positioned on the top surface of the first semiconductor structure, a first middle insulating layer positioned on the first bottom insulating layer, and a first top insulating layer positioned on the first middle insulating layer, wherein the plurality of first connecting contacts penetrate the first bottom insulating layer, the first middle insulating layer, and the first top insulating layer, and the plurality of first supporting contacts are positioned in the first top insulating layer.
13. The semiconductor device of claim 2, further comprising a second connecting structure positioned on the first connecting structure, and a second semiconductor structure positioned on the second connecting structure, wherein the second connecting structure comprises a second connecting insulating layer positioned on the first connecting structure, a plurality of second connecting contacts positioned in the second connecting insulating layer, and a plurality of second supporting contacts positioned in the second connecting insulating layer, wherein bottom surfaces of the plurality of second connecting contacts contact the top surfaces of the plurality of first connecting contacts.
14. The semiconductor device of claim 2, wherein a cross-sectional profile of sidewalls of the plurality of first connecting contacts is slanted.
15. A method for fabricating a semiconductor device, comprising:
- providing a first semiconductor structure; and
- forming a first connecting structure comprising a first connecting insulating layer on the first semiconductor structure, a plurality of first connecting contacts in the first connecting insulating layer, and a plurality of first supporting contacts in the first connecting insulating layer.
16. The method for fabricating the semiconductor device of claim 15, wherein the first connecting insulating layer comprises a first bottom insulating layer formed on the first semiconductor structure, a first middle insulating layer formed on the first bottom insulating layer, and a first top insulating layer formed on the first middle insulating layer, wherein the plurality of first connecting contacts are formed so as to penetrate the first top insulating layer, the first middle insulating layer, and the first bottom insulating layer and the plurality of first supporting contacts are formed in the first top insulating layer.
17. The method for fabricating the semiconductor device of claim 15, further comprising:
- forming a layer of an energy-removable material on a top surface of the first connecting insulating layer, between the plurality of first connecting contacts and the first connecting insulating layer, and between the plurality of first supporting contacts and the first connecting insulating layer; and
- performing an energy treatment to turn the layer of energy-removable material into a first porous layer,
- wherein a porosity of the first porous layer is between about 25% and about 100%.
18. The method for fabricating the semiconductor device of claim 17, wherein the energy-removable material comprises a base material and a decomposable porogen material.
19. The method for fabricating the semiconductor device of claim 18, wherein the base material comprises methylsilsesquioxane, low-dielectric materials, or silicon oxide.
20. The method for fabricating the semiconductor device of claim 19, wherein an energy source of the energy treatment is heat, light, or a combination thereof.
Type: Application
Filed: Feb 19, 2020
Publication Date: Aug 19, 2021
Inventor: Shing-Yih SHIH (NEW TAIPEI CITY)
Application Number: 16/794,998