SPLIT GATE STRUCTURE, POWER MOS DEVICE, AND MANUFACTURING METHOD
A split gate structure is disclosed. The split gate structure includes a first polysilicon, a characteristic oxide, and a second polysilicon sequentially disposed in a trench in a vertical direction upward from a bottom of the trench. An upper surface of the characteristic oxide has a height difference less than 1500 Å between a higher center portion and a lower periphery portion. The split gate structure effectively improves the breakdown performance and the IGSS performance. A power MOS device having the split gate structure and a manufacturing method of the split gate structure are also provided.
This application claims the priority of CN patent application No. 202010193258.3, filed on Mar. 18, 2020, which is incorporated herewith by reference.
BACKGROUND OF THE INVENTION 1. Field of the InventionThe present invention relates to the technical field of semiconductor, particularly to a split gate structure which can effectively improve the breakdown performance and the IGSS performance, a power MOS device, and a manufacturing method.
2. The Prior ArtsGenerally, a split gate power MOS (split gate power FET) is used as a switching device in an integrated circuit. When the device is turned off, it is preferable to have a small leakage, otherwise, the electric device will be power consuming. As such, the IGSS performance and the breakdown performance are important parameters for evaluating the performance of a split gate power MOS. Therefore, the improvement of the breakdown performance and the IGSS performance of a split gate power MOS becomes a problem to be solved in the technical field of semiconductor.
SUMMARY OF THE INVENTIONIn order to solve the existing technical problem, a split gate structure which can effectively improve the breakdown performance and the IGSS performance, a power MOS device having the same, and a manufacturing method of the same are provided in the present invention.
According to the present invention, a split gate structure is provided. The split gate structure comprises a first polysilicon, a characteristic oxide, and a second polysilicon sequentially disposed in a trench in a vertical direction upward from a bottom of the trench. An upper surface of the characteristic oxide has a height difference less than 1500 Å between a higher center portion and a lower periphery portion.
According to one embodiment of the present invention, the characteristic oxide is further disposed between the first polysilicon and a wall and the bottom of the trench.
According to one embodiment of the present invention, an effective distance between the first polysilicon and the second polysilicon, which is the smallest distance between the first polysilicon and the second polysilicon, is larger than 0.2 mm.
According to the present invention, a power MOS device is provided. The power MOS device comprises any split gate structure as described above.
According to the present invention, a manufacturing method of a split gate structure is provided. The manufacturing method comprises:
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- step 1: performing an etching back process on a first polysilicon in a trench with a characteristic oxide on a wall thereof;
step 2: performing a first etching process on the first polysilicon;
step 3: dipping in an acid solution such that a portion of the characteristic oxide is removed;
step 4: performing a second etching process on the first polysilicon such that the first polysilicon has a height lower than a height of the characteristic oxide disposed in the trench;
step 5: performing a thermal oxidation process such that a characteristic oxide with an upper surface having a height difference less than 1500 Å between a higher center portion and a lower periphery portion is formed on a top of the first polysilicon; and
step 6: depositing a second polysilicon in the trench.
According to one embodiment of the present invention, in said step 4, a height difference between the first polysilicon and the characteristic oxide is 0.05 to 0.15 mm.
According to one embodiment of the present invention, an effective distance between the first polysilicon and the second polysilicon, which is the smallest distance between the first polysilicon and the second polysilicon, is larger than 0.2 mm.
Since the technical solutions as described above are adopted, the present invention has the following advantages over the existing technology. Compared to a conventional split gate structure, in the new split gate structure fabricated by the manufacturing method of a split gate structure according to the present invention, the flatness of the contact surface between the characteristic oxide and the polysilicon is improved, and thereby the effective distance between the first polysilicon and the second polysilicon is increased. As such, the breakdown performance and the IGSS performance of the split gate power MOS are effectively improved.
The present invention will be described in detail through the following embodiments with appending drawings such that the objectives, technical solutions, and advantages of the present invention will be more clear. It should be understood that the specific embodiments are provided for an illustrative purpose only, and should not be interpreted in a limiting manner.
As illustrated in
step 1: performing an etching back process on a first polysilicon 212 in a trench 204 with a characteristic oxide 210A on a wall thereof such that the first polysilicon 212 has a height higher than a depth of the trench 204 (
step 2: performing a first etching process on the first polysilicon 212 such that the first polysilicon 212 has a height lower than the depth of the trench 204 (
step 3: performing a dipping process on the split gate, in which the split gate is dipped into an acid solution such that a portion of the characteristic oxide 210A at an upper part of the trench 204 is removed, and at this time, the first polysilicon 212 has a height higher than a height of an upper surface of the characteristic oxide 210A in the trench 204 (
step 4: performing a second etching process on the first polysilicon 212 such that the first polysilicon 212 has a height lower than a height of the characteristic oxide 210A disposed in the trench 204 (
step 5: forming a characteristic oxide 210B on a top of the first polysilicon 212 by means of illumination or the like, wherein the newly formed characteristic oxide 210B is combined with the original characteristic oxide 210A and together form the characteristic oxide 210, and as such, the first polysilicon 212 is isolated from the empty space at the upper part of the trench 204 (
step 6: finally, a second polysilicon 214 is deposited into the empty space at the upper part of the trench 204, and a split gate structure is formed (
The new split gate structure fabricated by the method described above has a characteristic oxide 210 with a flat surface and a uniform thickness distribution, it makes the effective distance, i.e., the smallest distance, between the first polysilicon 212 and the second polysilicon 214 significantly larger than that in the existing technology, preferably, the effective distance is larger than 0.2 mm, and thereby the anti-breakdown performance and the anti-leakage performance at the characteristic oxide 210 are effectively improved. In one embodiment, as shown in
While the present invention has been described in terms of the specific and detailed embodiments, the present invention is not limited thereto. It should be understood that various modifications and variations can be made without departing the scope and spirit of the present invention, and these modifications and variations therefore should be encompassed in the present invention. As such, the scopes of the present invention should be defined and indicated by the following claims and their equivalents.
Claims
1. A split gate structure, comprising:
- a first polysilicon, a characteristic oxide, and a second polysilicon sequentially disposed in a trench in a vertical direction upward from a bottom of the trench;
- wherein an upper surface of the characteristic oxide has a height difference less than 1500 Å between a higher center portion and a lower periphery portion; and
- wherein an effective distance between the first polysilicon and the second polysilicon, which is a smallest distance between the first polysilicon and the second polysilicon, is larger than 0.2 mm.
2. The split gate structure according to claim 1, wherein the characteristic oxide is further disposed between the first polysilicon and a wall and the bottom of the trench.
3. (canceled)
4. A power MOS device, comprising:
- the split gate structure according to claim 1.
5. A power MOS device, comprising:
- the split gate structure according to claim 2.
6. A power MOS device, comprising:
- the split gate structure according to claim 1.
7. A manufacturing method of a split gate structure, comprising:
- step 1: performing an etching back process on a first polysilicon in a trench with a characteristic oxide on a wall thereof;
- step 2: performing a first etching process on the first polysilicon;
- step 3: dipping in an acid solution such that a portion of the characteristic oxide is removed;
- step 4: performing a second etching process on the first polysilicon such that the first polysilicon has a height lower than a height of the characteristic oxide disposed in the trench;
- step 5: performing a thermal oxidation process such that another characteristic oxide with an upper surface having a height difference less than 1500 Å between a higher center portion and a lower periphery portion is formed on a top of the first polysilicon; and
- step 6: depositing a second polysilicon in the trench;
- wherein an effective distance between the first polysilicon and a second polysilicon, which is a smallest distance between the first polysilicon and the second polysilicon, is larger than 0.2 mm.
8. The manufacturing method according to claim 7, wherein, in said step 4, a height difference between the first polysilicon and the characteristic oxide is 0.05 to 0.15 mm.
9. (canceled)
Type: Application
Filed: May 14, 2020
Publication Date: Sep 23, 2021
Inventors: Yuan Cheng ZHENG (Suzhou), Xin Huan SHI (Suzhou)
Application Number: 15/931,603