CAPACITOR INTERPOSER LAYER (CIL) IN A DIE-TO-WAFER THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) (3DIC)
A capacitor interposer layer (CIL) in a die-to-wafer three dimensional integrated circuit (3DIC) and methods of forming the same are disclosed. A CIL is formed in a wafer under a powder distribution network (PDN) die area of a chip. Electrical connections between the wafer and the chip are formed using a copper-to-copper bond. This placement allows the capacitor to be close to the PDN die area within the chip to reduce equivalent series resistance (ESR) and equivalent series inductance (ESL), while permitting a relatively low profile device with reduced PDN voltage droop.
The technology of the disclosure relates generally to integrated circuits (IC) and, more particularly, to providing a capacitor in an interposer layer between a die and a wafer of an IC.
II. BackgroundComputing devices typically rely on integrated circuits (ICs) to handle various functions. As the size of many computing devices shrink, there has been pressure to change the geometries of the ICs. One such change in the geometry is a three-dimensional (3D) IC (3DIC), where a chip may be stacked on top of a wafer. Such arrangement may be desirable to conserve space. However, such high-performance IC may be vulnerable to excessive voltage drop in a power distribution network extending between the battery of the computing device and the IC where voltage drop may be caused, at least in part, by equivalent series resistance (ESR) and/or equivalent series inductance (ESL) of the conductors between the battery and the internal power origin within the IC.
One technique used in some situations is to add a bypass capacitor. Current proposals place such bypass capacitors underneath a substrate, which is relatively remote from the internal power distribution network. Accordingly, there is room for improved bypass capacitors.
SUMMARY OF THE DISCLOSUREAspects disclosed in the detailed description include a capacitor interposer layer (CIL) in a die-to-wafer three-dimensional (3D) integrated circuit (IC) (3DIC) and methods of forming the same. In an exemplary aspect, a CIL is formed in a wafer under a power distribution network (PDN) die area of a chip. Electrical connections between the wafer and the chip are formed using a copper-to-copper bond. This placement allows a capacitor to be close to the PDN die area within the chip to reduce equivalent series resistance (ESR) and equivalent series inductance (ESL), while permitting a relatively low profile device with reduced PDN voltage droop.
In this regard in one aspect, an IC is disclosed. The IC includes a chip comprising a first copper pad. The IC also includes a CIL. The CIL includes a trench capacitor comprising a plurality of trenches, at least two trenches defining a gap therebetween. The CIL also includes a second copper pad coupled to the first copper pad, the second copper pad positioned between the at least two trenches. The CIL also includes a metal pad conductively coupled to the second copper pad. The CIL also includes a via extending from a lower surface of the gap to the metal pad.
In another aspect, a method of forming an IC is disclosed. The method includes forming gaps between trench capacitors in a CIL. The method also includes etching the CIL at the gaps to form a via cavity. The method also includes forming a via in the via cavity. The method also includes attaching the CIL to a chip using a copper-to-copper bond between two copper pads.
With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
Aspects disclosed in the detailed description include a capacitor interposer layer (CIL) in a die-to-wafer three-dimensional (3D) integrated circuit (IC) (3DIC) and methods of forming the same. In an exemplary aspect, a CIL is formed in a wafer under a power distribution network (PDN) die area of a chip. Electrical connections between the wafer and the chip are formed using a copper-to-copper bond. This placement allows a capacitor to be close to the PDN die area within the chip to reduce equivalent series resistance (ESR) and equivalent series inductance (ESL), while permitting a relatively low profile device with reduced PDN voltage droop.
In this regard,
The IC 120 may require specific voltage levels to operate as designed. The explicit inductive elements as well as ESR and ESL created by the metal traces within the PCB 100, the vias, and the like may cause unwanted voltage drops. Accordingly, a bypass capacitor may be used to help compensate for such voltage drops. As noted, there are traditionally two locations where bypass capacitors can be added. In particular, as illustrated in
Exemplary aspects of the present disclosure provide a method for placing a trench bypass capacitor as an interposer layer in such a manner that the ESR and ESL are reduced relative to other designs. In this regard,
More details about the structure of the IC 500 will become apparent by reference to
With continued reference to
With continued reference to
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With continued reference to
It should be appreciated that the present disclosure provides flexibility in how the wafer 508 is sized. For example, multiple uniformly-sized wafers 800 may be attached to a first chip 802 as illustrated in
The CIL in a die-to-wafer 3DIC and methods of forming the same according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart, watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multi copter.
In this regard,
Other devices can be connected to the system bus 908. As illustrated in
The CPU(s) 902 may also be configured to access the display controllers) 920 over the system bus 908 to control information sent to one or more displays 926. The display controllers) 920 sends information to the display(s) 926 to be displayed via one or more video processors 928, which process the information to be displayed into a format suitable for the display(s) 926. The display(s) 926 can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.
In the interests of complete disclosure, more details about trench capacitors are provided with reference to
The first electrically conductive layer 1012, the dielectric layer 1014, the second electrically conductive layer 1016, and the filler 1015 may be located over a first surface of the substrate 1002 and in one or more trenches of the substrate 1002. The first electrically conductive layer 1012 is located (e.g., formed) over the first surface of the substrate 1002 and in one or more trenches of the substrate 1002. The dielectric layer 1014 is located over the first electrically conductive layer 1012. Portions of the dielectric layer 1014 may be located in one or more trenches of the substrate 1002. The second electrically conductive layer 1016 may be located over the dielectric layer 1014. Portions of the second electrically conductive layer 1016 may be located in one or more trenches of the substrate 1002. The second contact layer 1018 may be located over the second electrically conductive layer 1016. The first contact layer 1030 may be located over the first electrically conductive layer 1012.
The trench capacitor 1000 includes the first electrically conductive layer 1012, the dielectric layer 1014 and the second electrically conductive layer 1016. In some implementations, the trench capacitor 1000 may be defined by portions of the first electrically conductive layer 1012, portions of the dielectric layer 1014 and portions of the second electrically conductive layer 1016 that are located in the trench of substrate 1002. It is noted that the trenches of the substrate 1002 may not be visible in
The substrate 1002 may include silicon (Si). The first electrically conductive layer 1012 may include N+ silicon. The second electrically conductive layer 1016 may include N+ poly silicon. The first electrically conductive layer 1012 may include N+ poly silicon, and the second electrically conductive layer 1016 may include N+ silicon. It is noted that different implementations may use different materials and/or different combinations of materials for the first electrically conductive layer 1012 and/or the second electrically conductive layer 1016. For example, the first electrically conductive layer 1012 and/or the second electrically conductive layer 1016 may include P+ silicon, P+ poly silicon, copper (Cu), aluminum (Al), and/or other metals. The dielectric layer 1014 may include SiNx, SiO2, Al2O3, HfO2, ZrO2, Ta2O5, and/or combinations thereof. The filler 1015 may include Ajinomoto Buildup Film (ABF), Tungsten (W), or other similar materials. The second contact layer 1018 and/or the first contact layer 1030 may include metal (e.g., Cu, Al).
As shown in
Each respective trench capacitor (e.g., 1000a, 1000b, 1000c, 1000d, 1000e) from the plurality of the trench capacitors 1000 may be defined by respective portions of the first electrically conductive layer 1012, respective portions of the dielectric layer 1014, and respective portions of the second electrically conductive layer 1016 that are located in a respective trench of the substrate 1002. Thus, for example a first trench capacitor 1000a may be defined in a first trench of the substrate 1002, and a second trench capacitor 1000b may be defined in a second trench of the substrate 1002. The first trench capacitor 1000a may be configured to be electrically coupled in parallel to the second trench capacitor 1000b. It is noted that any trench capacitor from the plurality of trench capacitors 1000 may be the first or second trench capacitors. As such, the use of the terms first trench capacitor and second trench capacitor are not limited to any particular trench capacitor in the disclosure. As mentioned above, a trench capacitor may be a type of capacitor. Thus, for example, the first trench capacitor may be a first capacitor, and the second trench capacitor may be a second capacitor.
As shown in
In some implementations, the interconnect that travels through the cavity 1130 of the substrate 1002 may be coupled to an integrated device and a substrate. In some implementations, the interconnect that travels through the cavity 1130 of the substrate 1002 may be coupled to a substrate and a board (e.g., PCB). The interconnect that travels through the cavity 1130 may include one or more interconnects. The interconnect that travels through the cavity 1130 may include a pillar, a via, and/or a solder interconnect.
Different implementations may include different configurations, arrangements and/or placements of the trench capacitors 1000. For example, the capacitor structure 1101 may include a different number of trench capacitors 1000.
Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The devices described herein may be employed in any circuit, hardware component, IC, or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. An integrated circuit (IC) comprising:
- a chip comprising a first copper pad; and
- a capacitor interposer layer (CIL) comprising: at least two trench capacitors, each trench capacitor comprising a plurality of trenches, the at least two trench capacitors defining a gap therebetween; a second copper pad coupled to the first copper pad, the second copper pad positioned between the at least two trench capacitors; a metal pad conductively coupled to the second copper pad; and a via extending from a lower surface of the gap to the metal pad.
2. The IC of claim 1, wherein the chip comprises an application processor.
3. The IC of claim 1, wherein the chip comprises a mobile device modem.
4. The IC of claim 1, further comprising an external bump conductively coupled to the via.
5. The IC of claim 1, wherein the via extends through at least one intervening metal layer without contacting metal therein.
6. The IC of claim 1, further comprising a liner surrounding the via, wherein the liner comprises a dielectric material.
7. The IC of claim 4, further comprising a copper bump positioned between the external bump and the via.
8. The IC of claim 1, further comprising a mold compound surrounding the CIL.
9. The IC of claim 1, further comprising an additional via positioned outside the CIL and coupling another external bump to the chip.
10. The IC of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
11. A method of forming an integrated circuit (IC), comprising:
- forming gaps between trench capacitors in a capacitor interposer layer (CIL);
- etching the CIL at the gaps to form a via cavity;
- forming a via in the via cavity; and
- attaching the CIL to a chip using a copper-to-copper bond between two copper pads.
12. The method of claim 11, further comprising lining the via cavity with a dielectric material.
13. The method of claim 11, wherein the chip comprises an application processor.
14. The method of claim 11, wherein the chip comprises a mobile device modem.
15. The method of claim 11, further comprising thinning the CIL.
16. The method of claim 11, wherein forming the via comprises filling the via cavity with a conductor.
17. The method of claim 11, further comprising adding copper plating at one end of the via.
18. The method of claim 17, further comprising adding a passivation layer adjacent to the copper plating.
19. The method of claim 11, further comprising forming other vias outside the CIL and coupling the chip to external bumps.
20. The method of claim 11, further comprising adding a mold compound around the CIL.
Type: Application
Filed: Apr 23, 2020
Publication Date: Oct 28, 2021
Inventors: Je-Hsiung Lan (San Diego, CA), Jonghae Kim (San Diego, CA), Jinseong Kim (San Diego, CA), Periannan Chidambaram (San Diego, CA)
Application Number: 16/856,132