SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes: a plurality of active layers stacked in a first direction perpendicular to a substrate and laterally oriented in a second direction intersecting with the first direction; a plurality of bit lines each of which is coupled to one side of each of the active layers and laterally oriented in a direction intersecting with the first direction and the second direction; a plurality of capacitors each of which is coupled to another side of each of the active layers; and a word line vertically oriented penetrating the active layers in the first direction.
The present application claims priority to Korean Patent Application No. 10-2020-0134490, filed on Oct. 16, 2020, which is incorporated herein by reference in its entirety.
BACKGROUND 1. FieldVarious embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a memory cell stack, and a method for fabricating the same.
2. Description of the Related ArtRecently, in order to increase the net die of a memory device, the size of the memory cell has been continuously reduced.
As the size of memory cells becomes smaller, parasitic capacitance Cb should be reduced and capacitance should be increased. However, it is difficult to increase the net die due to structural limitations of memory cells.
SUMMARYEmbodiments of the present invention are directed to a semiconductor device including highly integrated memory cells, and a method for fabricating the semiconductor device.
In accordance with an embodiment of the present invention, a semiconductor device includes: a plurality of active layers stacked in a first direction perpendicular to a substrate and laterally oriented in a second direction intersecting with the first direction; a plurality of bit lines each of which is coupled to one side of each of the active layers and laterally oriented in a direction intersecting with the first direction and the second direction; a plurality of capacitors each of which is coupled to another side of each of the active layers; and a word line vertically oriented penetrating the active layers in the first direction.
In accordance with another embodiment of the present invention, a method for fabricating a semiconductor device includes: forming an etch stop layer over a substrate; forming a mold stack in which dielectric layers and semiconductor layers are alternately stacked over the etch stop layer; forming a first trench by etching the mold stack; recessing one side of the semiconductor layers through the first trench to form first recess portions between the dielectric layers; forming bit lines that are laterally oriented in the first recess portions; etching the mold stack in a direction intersecting with the bit lines to form a second trench that divides the mold stack into a plurality of line-type stacks; and forming a vertically oriented word line through the line-type stacks.
In accordance with yet another embodiment of the present invention, a method for fabricating a semiconductor device includes: preparing a substrate including a peripheral circuit; forming a mold stack in which dielectric layers and active layers are alternately stacked over the substrate; replacing one side of the active layers with laterally oriented bit lines; forming an isolation layer that divides the mold stack into a plurality of line-type stacks; forming a vertically oriented word line that penetrates the active layers; and forming a laterally oriented capacitor that is coupled to another side of the active layers.
These and other features and advantages will become better understood from the following drawings and detailed description.
Various embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.
The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate.
In the following embodiment of the present invention, memory cells may be vertically stacked to increase memory cell density and reduce parasitic capacitance.
Referring to
The substrate LS may be made of any material suitable for semiconductor processing. The substrate LS may include at least one among a conductive material, a dielectric material, and a semiconductor material. Diverse materials may be formed over the substrate LS. The substrate LS may include a semiconductor substrate. The substrate LS may be formed of a silicon-containing material. The substrate LS may include silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a mufti-layer thereof, The substrate LS may also include other semiconductor materials, such as germanium. The substrate LS may include a III/V-group semiconductor substrate, for example, a compound semiconductor substrate, such as gallium arsenide (GaAs). The substrate LS may include a Silicon-On-Insulator (SOI) substrate.
The substrate LS may include a peripheral circuit (not shown). The peripheral circuit may include a plurality of control circuits for controlling the memory cell stacks MCS1 and MCS2. At least one control circuit of the peripheral circuit may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit may include an address decoder circuit, a read circuit, and a write circuit, At least one control circuit of the peripheral circuit may include a planar channel transistor, a recess channel transistor, a buried gate transistor, a fin channel transistor (FinFET), etc.
For example, at least one control circuit of the peripheral circuit may be electrically connected to a bit line BL. The peripheral circuit may include a sense amplifier SA, and the sense amplifier SA may be electrically connected to a bit line. Although not illustrated, a multi-level metal wire MLM may be positioned between the memory cell stacks MCS1 and MCS2 and the substrate LS. The peripheral circuit and the bit line BL may be coupled to each other through the multi-level metal wire MLM.
The bit line BL may extend in the third direction D3 which is parallel to the upper surface of the substrate LS. The bit line BL may be spaced apart from the substrate LS to be laterally oriented. The bit line BL may be referred to as a laterally oriented bit line. The bit line BL may include a conductive material. The bit line BL may include a silicon-based material, a metal-based material, or a combination thereof. The bit line BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The memory cells MC arranged laterally in a same row in the third direction D3 may share one bit line BL. The bit line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line BL may include polysilicon or titanium nitride (TiN) that is doped with an N-type impurity. The bit line BL may include a stack of titanium nitride and tungsten (TiN/W). The bit line BL may further include an ohmic contact layer, such as a metal silicide.
The transistor TR may be disposed in a lateral arrangement along the second direction D2 which is parallel to the surface of the substrate LS. The transistor TR may be laterally positioned between the bit line BL and the capacitor CAP. The transistor TR may be positioned at a higher level than the substrate LS. The transistor TR and the substrate LS may be spaced apart from each other.
The transistor TR may include an active layer ACT, a gate dielectric layer GD, and a word line WL. The word line WL may extend vertically in the first direction D1, and the active layer ACT may extend in the second direction D2. The first direction D1 may be a direction perpendicular to the second direction D2. The active layer ACT may be laterally arranged with respect to the bit line BL. The active layer ACT may be oriented parallel to the plane of the substrate LS.
The word line WL may have a pillar shape penetrating the active layer ACT. The word line WL may have a cross-sectional area in the shape of a circle as sown in
The gate dielectric layer GD may include, for example, silicon oxide, silicon nitride, a metal oxide, a metal oxynitride, a metal silicate, a high-k material, a ferroelectric material, an anti-ferroelectric, or a combination thereof. For example, the gate dielectric layer GD may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, and the like.
The word line WL may include a metal, a metal mixture, a metal alloy, or a semiconductor material. For example, the word line WL may include titanium nitride, tungsten, polysilicon, or a combination thereof, For example, the word line WL may include a TiN/W stack in which titanium nitride and tungsten are sequentially stacked. The word line WL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of approximately 4.5 eV or less, and the P-type work function material may have a high work function of approximately 4.5 eV or more.
The word line WL and the bit line BL may extend in intersecting directions,
The active layer ACT may include any suitable semiconductor material, including, for example, polysilicon. The active layer ACT may include a plurality of impurity regions. The impurity regions may include first and second regions SD1 and SD2, which may be a source or a drain and are referred to hereinafter also as a first source/drain region SD1 and a second source/drain region SD2. The active layer ACT may include, for example, doped polysilicon, undoped polysilicon, amorphous silicon, or an oxide semiconductor material. The first source/drain region SD1 and the second source/drain region SD2 may be doped with an N-type impurity or a P-type impurity. The first source/drain region SD1. and the second source/drain region SD2 may be doped with an impurity of the same conductivity type. The first source/drain region SD1 and the second source/drain region SD2 may be doped with an N-type impurity. The first source/drain region SD1 and the second source/drain region SD2 may be doped with a P-type impurity. The first source/drain region SD1 and the second source/drain region SD2 may include at least one impurity selected among arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The bit line BL may be electrically connected to a first edge portion of the active layer ACT, and a capacitor CAP may be electrically connected to a second edge portion of the active layer ACT. The first edge portion of the active layer ACT may be provided by the first source/drain region SD1, and the second edge portion of the active layer ACT may be provided by the second source/drain region SD2.
The active layers ACT neighboring in the third direction D3 may be isolated and supported by an isolation layer IL shown in
The capacitor CAP may be disposed laterally with respect to the transistor TR. The capacitor CAP may laterally extend from the active layer ACT in the second direction D2. The capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node PN. The storage node SN, the dielectric layer DE, and the plate node PN may be laterally arranged in the second direction D2. The storage node SN may have a laterally oriented cylinder shape, and the plate node PN may have a shape extending into the cylinder inner wall and the cylinder outer wall of the storage node SN. The dielectric layer DE may be positioned inside the storage node SN while surrounding the plate node PN. The plate node PN may be coupled to the plate line PL. The storage node SN may be electrically connected to the second source/drain region SD2.
The capacitor CAP may include a Metal-insulator-Metal (MIM) capacitor. The storage node SN and the plate node PN may include a metal-based material. The dielectric layer DE may include, for example, silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of approximately 3.9, and the dielectric layer DE may include a high dielectric constant material having a dielectric constant of approximately 4 or more. The high-k material may have a dielectric constant of approximately 20 or more. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2Os), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). According to another embodiment of the present invention, the dielectric layer DE may be formed of a composite layer including two or more layers of the high-k materials mentioned above.
The dielectric layer DE may be formed of zirconium-based oxide. The dielectric layer DE may have a stacked structure including zirconium oxide (ZrO2). The stacked structure including zirconium oxide (ZrO2) may include a ZA (ZrO2/Al2O3) stack or a ZAZ (ZrO2/Al2O3/ZrO2) stack. The ZA stack may have a structure in which aluminum oxide (Al2O3) is stacked over zirconium oxide (ZrO2). The ZAZ stack may have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2) are sequentially stacked. The ZA stack and the ZAZ stack may be referred to as zirconium oxide-based layers. According to another embodiment of the present invention, the dielectric layer DE may be formed of hafnium-based oxide. The dielectric layer DE may have a stacked structure including hafnium oxide (HfO2). The stacked structure including hafnium oxide (HfO2) may include an HA (HfO2/Al2O3) stack or an HAH (HfO2/Al2O3/HfO2) stack. The HA stack may have a structure in which aluminum oxide (Al2O3) is stacked over hafnium oxide (HfO2). The HAH stack may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2) are sequentially stacked. The HA stack and the HAH stack may be referred to as a hafnium oxide-based layer (HfO2-based layer). In the ZA stack, ZAZ stack, HA stack, and HAH stack, aluminum oxide (Al2O3) may have a larger band gap than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (A12O3) may have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Accordingly, the dielectric layer DE may include a stack of a high-k material and a high band gap material having a larger band gap than that of the high-k material. The dielectric layer DE may include, for example, silicon oxide (SiO2) as a high band gap material other than aluminum oxide (Al2O3). Since the dielectric layer DE contains a high band gap material, leakage current may be suppressed. The high bandgap material may be extremely thin. The high band gap material may be thinner than the high-k material. According to another embodiment of the present invention, the dielectric layer DE may include a laminated structure in which a high-k material and a high band gap material are alternately stacked. For example, the dielectric layer DE may include ZAZA (ZrO2/Al2O3/ZrO2/Al2O3), ZAZAZ (ZrO2/Al2O3/ZrO2/Al2O3/ZrO2), HAHA (HfO2/Al2O3/HfO2/Al2O3) or HAHAH (HfO2/Al2O3/HfO2/Al2O3/HfO2). Tn the above laminated structure, aluminum oxide (Al2O3) may be extremely thin.
According to another embodiment of the present invention, the dielectric layer DE may include a stacked structure, a laminated structure, or a mixed structure including zirconium oxide, hafnium oxide, and aluminum oxide.
According to another embodiment of the present invention, an interface control layer (not shown) for improving leakage current may be further formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2). The interface control layer may also be formed between the plate node PN and the dielectric layer DE.
The storage node SN and the plate node PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the storage node SN and the plate node PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), a titanium nitride, tungsten (TiN/W) stack, a tungsten nitride/tungsten (WN/W) stack. The plate node PN may include a combination of a metal-based material and a silicon-based material. For example, the plate node PN may be a stack of titanium nitride/silicon germanium/tungsten nitride (TiN/SiGe/WN). In the titanium nitride/silicon germanium/tungsten nitride (TiN/SiGe/WN) stack, silicon germanium may be a gap-fill material filling the cylindrical inside of the storage node SN, and titanium nitride (TiN) may serve as a plate node of a substantial capacitor CAP, and tungsten nitride may be a low-resistance material. The neighboring plate nodes PN may be commonly coupled to the plate line PL. The bottom portion of the plate line PL may be insulated from the substrate LS.
The storage node SN may have a three-dimensional (3D) structure, and the storage node SN having a 3D structure may have a lateral 3D structure which is oriented in the second direction D2. As an example of a three-dimensional structure, the storage node SN may have a cylinder shape, a pillar shape, or a pylinder shape. The pylinder shape may refer to a structure in which a pillar shape and a cylinder shape are merged.
Referring back to
The semiconductor device 100 of
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to FIGS, 11A and 11B, a second isolation layer 29 may be formed in the second trenches 28. The second isolation layer 29 may completely fill the second trenches 28. The second isolation layer 29 may include a dielectric material. The second isolation layer 29 may include, for example, silicon oxide, For example, the second isolation layer 29 may be formed by forming silicon oxide to fill the second trenches 28 and then planarizing the silicon oxide,
The line-type stacks 20L may be separated from each other not only by the second isolation layer 29 but also by the neighboring first isolation layer 27. Each of the line-type stacks 20L may be formed by alternately stacking a plurality of dielectric layer lines 21L and a plurality of semiconductor layer lines 22L.
Referring to FIGS, 12A and 12B, a through hole 30 penetrating the line-type stacks 20L may be formed. The through hole 30 may extend vertically in the first direction D1. At least two through holes 30 may penetrate one individual line-type stack 20L. The through holes 30 may penetrate the (dielectric layer lines 21L and the semiconductor layer lines 22L. The through holes 30 may not penetrate the lowermost dielectric layer 21. The through holes 30 may be positioned closer to the ends of the line-type stacks 20L but may not touch the impurity regions 25.
Referring to
Subsequently, a word line 32 filling the through holes 30 may be formed over the gate dielectric layers 31. The word line 32 may be formed by depositing a conductive material to fill the through holes and performing a planarization process, such as Chemical Mechanical Polishing (CMP). The word lines 31 may extend vertically in the first direction D1. At least two word lines 32 may penetrate one individual line-type stack 20L. The word lines 32 may penetrate the dielectric layer lines 21L and the semiconductor layer lines 22L.
Referring to
As the third trench 33 is formed, a plurality of cell stacks 20M may be formed over the substrate 11, Each of the cell stacks 20M may include a plurality of isolation layers 21M and a plurality of active layers 22M. Each of the cell stacks 20M may be formed by alternately stacking the isolation layers 21M and the active layers 22M. The isolation layers 21M may be formed by cutting the dielectric layer lines 21L. The active layers 22M may be formed by cutting the semiconductor layer lines 22L.
Referring to
Subsequently, second impurity regions 35 may be formed in the second edges E2 of the active layers 22M exposed by the second recess portions 34, respectively. The second impurity regions 35 may be formed by ion implantation of an impurity introduced via the third trench 33. The second impurity regions 35 may be formed by a plasma doping process. The second impurity regions 35 may include an N-type impurity or a P-type impurity. The second impurity regions 35 may include phosphorus, arsenic, antimony, boron, or indium, The second impurity regions 35 may be referred to as source/drain regions. The word lines 32 may penetrate the active layers 22M, and a first impurity region 25 and a second impurity region 35 may be formed on both sides of the word lines 32.
Referring to
Referring to FIGS, 17A and 17B, one side of each of the isolation layers 21M may be recessed by an etching process indicated by reference numeral 37. The second isolation layer 29 may be recessed together with the isolation layers 21M. Accordingly, both inner walls and outer walls of the storage nodes 36 may be exposed.
Referring to
Referring to FIG, 19, the same reference numerals as those in
Referring to
The active layer ACT′ may include an active layer body BE and protrusions PE on both sides of the active layer body BE. The protrusions PE may be symmetrical to each other with respect to a center line of the active layer body BE. The active layer body BE and the protrusions PE may form a generally cross shape with the active layer body BE and the protrusions PE each having a generally rectangular shape. The protrusions PE may be substantially smaller than the active layer body BE. The protrusions PE may have a width smaller than that of the active layer body BE. For example, the width of the protrusions PE in the third direction D3 may be smaller than the active layer body BE. The word line WL may penetrate the active layer body BE.
According to embodiments of the present invention, since memory cells are vertically stacked, cell density may be improved.
While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
Claims
1. A semiconductor device, comprising:
- a plurality of active layers stacked in a first direction perpendicular to a substrate and laterally oriented in a second direction intersecting with the first direction;
- a plurality of bit lines each of which is coupled to one side of each of the active layers and laterally oriented in a direction intersecting with the first direction and the second direction;
- a plurality of capacitors each of which is coupled to another side of each of the active layers; and
- a word line vertically oriented penetrating the active layers in the first direction.
2. The semiconductor device of claim 1, wherein the active layer includes:
- an active layer body laterally oriented in the second direction; and
- protrusions extending in the second direction from the active layer body.
3. The semiconductor device of claim 2, wherein each of the protrusions has a smaller width than the active layer body.
4. The semiconductor device of claim 1, wherein the active layers, the bit lines, and the capacitors are positioned at the same level.
5. The semiconductor device of claim 1, wherein each of the capacitors includes:
- a cylindrical storage node coupled to another side of each of the active layers;
- a dielectric layer over the storage node; and
- a plate node over the dielectric layer,
- wherein the cylindrical storage node is laterally oriented in the second direction,
6. The semiconductor device of claim 5, further comprising:
- a plate line commonly coupled to the plate nodes of the capacitors,
- wherein the plate line is vertically oriented in the first direction,
7. The semiconductor device of claim 1, further comprising:
- gate dielectric layers between the active layers and the word line.
8. The semiconductor device of claim 1, further comprising:
- a first impurity region between one side of the active layers and the bit lines; and
- a second impurity region between another side of the active layers and the capacitor.
9. The semiconductor device of claim 1, wherein the substrate includes at least one peripheral circuit.
10. A method for fabricating a semiconductor device, comprising:
- forming an etch stop layer over a substrate;
- forming a mold stack in which dielectric layers and semiconductor layers are alternately stacked over the etch stop layer;
- forming a first trench by etching the mold stack;
- recessing one side of the semiconductor layers through the first trench to form first recess portions between the dielectric layers;
- forming bit lines that are laterally oriented in the first recess portions;
- etching the mold stack in a direction intersecting with the bit lines to form a second trench that divides the mold stack into a plurality of line-type stacks; and
- forming a vertically oriented word line through the line-type stacks.
11. The method of claim 10, wherein the semiconductor layers include polysilicon.
12. The method of claim 10, further comprising:
- forming a third trench that is spaced apart from the word line by etching the line-type stack, after the forming of the vertically oriented word line through the line-type stacks;
- recessing another side of the semiconductor layers through the third trench to form a second recess portion between the (dielectric layers;
- forming storage nodes inside the second recessed portions;
- forming a dielectric layer over the storage nodes; and
- forming a plate node over the dielectric layer,
13. The method of claim 12, wherein the storage nodes include a cylindrical storage node.
14. The method of claim 12, further comprising:
- forming a plate line that is commonly coupled to the plate nodes.
15. A method for fabricating a semiconductor device, comprising:
- preparing a substrate including a peripheral circuit;
- forming a mold stack in which dielectric layers and active layers are alternately stacked over the substrate;
- replacing one side of the active layers with laterally oriented bit lines;
- forming an isolation layer that divides the mold stack into a plurality of line-type stacks;
- forming a vertically oriented word line that penetrates the active layers; and
- forming a laterally oriented capacitor that is coupled to another side of the active layers.
16. The method of claim 15, wherein the replacing of the one side of the active layers with the laterally oriented bit lines includes:
- forming a first trench by etching the mold stack;
- recessing one side of the active layers through the first trench to form first recess portions between the dielectric layers; and
- filling the first recess portions with a conductive material to form the laterally oriented bit lines.
17. The method of claim 15, wherein the forming of the isolation layer that divides the mold stack into the plurality of line-type stacks includes:
- forming a second trench that extends in a direction intersecting with the bit lines by etching the mold stack; and
- filling the second trench with a dielectric material.
18. The method of claim 15, wherein the forming of the laterally oriented capacitor that is coupled to another side of the active layers includes:
- forming a third trench by etching the mold stack;
- recessing another side of the active layers through the third trench to form second recess portions between the dielectric layers;
- filling the second recess portions with a conductive material to form the cylindrical storage node;
- forming a dielectric layer over the cylindrical storage node; and
- forming a plate node over the dielectric layer.
19. The method of claim 15, wherein each of the active layers includes:
- an active layer body penetrating the word line; and
- protrusions extending from both sides of the active layer body,
- wherein the protrusions are formed to have a smaller width than the active layer body.
20. The method of claim 15, wherein each of the active layers includes polysilicon.
Type: Application
Filed: Mar 25, 2021
Publication Date: Apr 21, 2022
Inventor: Seung Hwan KIM (Gyeonggi-do)
Application Number: 17/212,693