Successive Approximation Register Analog to Digital Converter
A successive approximation analog-to-digital with an input for receiving an input analog voltage, and an amplifier with a first set of electrical attributes in a sample phase and a second set of electrical attributes, differing from the first set of electrical attributes, in a conversion phase.
Not applicable.
BACKGROUNDThe example embodiments relate to analog-to-digital converters (ADC singular, ADCs plural) and, more particularly, to successive approximation register (SAR) ADCs.
A SAR ADC converts an analog input voltage signal to a digital output value, sometimes referred to as a code, by successively comparing the input to an internally-generated and changing reference voltage. For each successive comparison, the reference voltage is adjusted to converge toward the value of the analog input voltage signal, while each such adjustment and comparison determines a respective bit of the SAR ADC output code. Further, as the differential between the input and reference voltage thus converges, the reference voltage change is smaller in each successive comparison, and the smaller reference voltage and differential is therefore more susceptible to error.
A SAR ADC is typically embodied as, or part of, an integrated circuit (IC). Accordingly, typical IC design considerations are factors for the SAR ADC, such as area and power consumed by the device. Further, as SAR ADCs have advanced, for example operating at higher speed and with a greater number of output bits, additional design considerations are directed to output accuracy. For example, noise impacts the SAR ADC input signal, its components that process the input signal, and the proper assessment of the converging differential between the input signal and reference voltage. Accordingly, noise effects may be considered to the extent those can cause a signal state change greater than the least significant bit (LSB) resolution of the device, that is, potentially producing an error in the output or limiting the resolution of the output code.
While the preceding considerations are generally common to most SAR ADCs, different designers may prioritize different design considerations, for example considering different sources of noise and designs to mitigate nose effects. Accordingly, example embodiments are provided in this document that may improve on various of such noise considerations as well as other concepts, as further described below.
SUMMARYA successive approximation analog-to-digital converter an input for receiving an input analog voltage. The converter further comprises sample phase circuitry comprising an amplifier and for providing the amplifier with a first set of electrical attributes and for sampling the input analog voltage in a sample phase, and conversion phase circuitry comprising the amplifier and for providing the amplifier with a second set of electrical attributes differing from the first set of electrical attributes and for converting a comparison, of the sampling of the input analog voltage relative to a reference voltage, to a digital value in a conversion phase.
Other aspects are also disclosed and claimed.
The general operation of the SAR ADC 100 is as follows, with additional structural and operational details provided later. The SAR ADC 100 in a first phase samples VIN and then in a second phase performs conversion by iteratively comparing the sampled VIN to different internally-generated reference voltages, provided from the DAC 112. Transitions between the sample phase and iterative conversion phase are executed in part by the input switch 106 and the first bias switch 114, as described later. Further, the overall SAR ADC 100 operation is improved by implementing into the sample phase an auto zeroing (AZ) sample phase noise suppression (AZSPNS) aspect, shown generally in
The preceding description of the first conversion phase iteration of the SAR ADC 100 repeats so that in total N conversion phase iterations occur, each iteration corresponding to a respective bit in the N bits of the N-bit register 104. Accordingly, following the first iteration, N−1 successive iterations occur, where each iteration is for a next less significant bit in the N-bit register 104 and until all N bits in the register 104 have been processed through respective conversion phase iterations. At the completion of those operations, the N bits in the N-bit register 104 present a digital approximation of VIN, and are provided to the output 118 as the CODE.
The operation of the
During the sample phase, recall that AZ is concurrently implemented and AZSPNS is asserted. Accordingly in
As described above, a number N of conversion phase iterations follow the sample phase. In the conversion phase iterations, recall that AZSPNS is de-asserted, and as a result in
From the above, example embodiments include an ADC, such as a SAR ADC, with improved performance from selectively adjusting the ADC electrical attributes during different ADC phase operations. The adjustment as performed desirably reduces the possible storage of higher frequency noise as part of the AZ offset voltage during the sample phase. Further, in an example embodiment, the selectively-adjusted electrical attribute includes changing the amplification stage bandwidth to differ in the ADC sample phase versus its conversion phase. Further, the selectively adjusted bandwidth may be accomplished by changing the amplification signal path capacitance to differ in the sample phase from that of the conversion phase, for example, by switching a capacitor in and out of the amplifier output signal path in the sample and conversion phase, respectively. Still further, in the example embodiment, the changed capacitance is implemented in a first amplifier of cascaded amplifiers if the amplification stage includes plural amplifiers, as the gain of the first amplifier is the most impactful if cascading through plural amplifiers. Further, while the above-described attributes are shown and described, also contemplated are changes in various parameters, including dimensions, with the preceding providing only some examples, with others ascertainable, from the teachings herein, by one skilled in the art. Accordingly, additional modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the following claims.
Claims
1. A circuit comprising:
- an input configured to receive an input analog voltage;
- a first switch that includes: a first input coupled to the input of the circuit; a second input coupled to receive a reference voltage; and an output;
- a first capacitor coupled to the output of the first switch; and
- a comparator that includes: an amplifier that includes: a transconductor that includes an input coupled to the first capacitor and an output; a buffer coupled to the output of the transconductor; a second capacitor coupled to a ground node; and a second switch coupled between the second capacitor and the output of the transconductor; a third capacitor coupled to the amplifier; and a latch coupled to the third capacitor.
2. The circuit of claim 1, wherein the comparator includes a third switch that includes:
- an input coupled to receive a bias voltage; and
- an output coupled to the latch.
3. The circuit of claim 2, wherein the second switch and the third switch are coupled to be controlled by an auto zeroing signal.
4. The circuit of claim 1 further comprising a digital-to-analog converter coupled to the second input of the first switch to provide the reference voltage.
5. A successive approximation analog-to-digital converter, comprising:
- an input for receiving an input analog voltage;
- sample phase circuitry comprising an amplifier and for providing the amplifier with a first set of electrical attributes and for sampling the input analog voltage in a sample phase; and
- conversion phase circuitry comprising the amplifier and for providing the amplifier with a second set of electrical attributes differing from the first set of electrical attributes and for converting a comparison, of the sampling of the input analog voltage relative to a reference voltage, to a digital value in a conversion phase, wherein the sample phase circuitry comprises circuitry for switching a capacitance between an output of the amplifier and a fixed potential in the sample phase; and wherein the circuitry for switching is further for disconnecting the capacitance from between the output of the amplifier and the fixed potential in the conversion phase.
6. The successive approximation analog-to-digital converter of claim 5 wherein the conversion phase circuitry is for iteratively converting a comparison, of the sampling of the input analog voltage relative to an iteration respective reference voltage, to a digital value in the conversion phase.
7. The successive approximation analog-to-digital converter of claim 5:
- wherein the sample phase circuitry is for providing an output of the amplifier with the first set of electrical attributes; and
- wherein the sample phase circuitry is for providing the output of the amplifier with the second set of electrical attributes.
8. The successive approximation analog-to-digital converter of claim 7 wherein the first set of electrical attributes and the second set of electrical attributes comprise frequency bandwidth.
9. The successive approximation analog-to-digital converter of claim 7:
- wherein the first set of electrical attributes comprises a first frequency bandwidth; and
- wherein the second set of electrical attributes comprises a second frequency bandwidth larger than the first frequency bandwidth.
10. The successive approximation analog-to-digital converter of claim 5:
- wherein the first set of electrical attributes comprises a first frequency bandwidth with a first upper corner frequency; and
- wherein the second set of electrical attributes comprises a second frequency bandwidth with a second upper corner frequency larger than the first upper corner frequency.
11. The successive approximation analog-to-digital converter of claim 5 wherein the first set of electrical attributes and the second set of electrical attributes comprise frequency bandwidth.
12. The successive approximation analog-to-digital converter of claim 5:
- wherein the first set of electrical attributes comprises a first frequency bandwidth; and
- wherein the second set of electrical attributes comprises a second frequency bandwidth larger than the first frequency bandwidth.
13. (canceled)
14. The successive approximation analog-to-digital converter of claim 5 wherein the amplifier comprises a first amplifier in a cascade of a plurality of amplifiers.
15. The successive approximation analog-to-digital converter of claim 5 and further comprising a digital-to-analog converter for outputting the reference voltage.
16. The successive approximation analog-to-digital converter of claim 15 and further comprising an N-bit register for providing a digital value to the digital-to-analog converter for outputting the reference voltage; and.
- wherein the conversion phase circuitry is for converting a comparison of the sampling of the input analog voltage for a number of iterations, each iteration converting, relative to an iteration respective reference voltage, to a digital value in the conversion phase; and
- wherein the number of iterations equals N.
17. The successive approximation analog-to-digital converter of claim 5 wherein the first set of electrical attributes provides reduced thermal noise in the amplifier relative to thermal noise in the amplifier in the second set of electrical attributes.
18. A method of successive approximation of a digital code from an input analog voltage, comprising:
- sampling the input analog voltage with an amplifier having a first set of electrical attributes in a sample phase, wherein the sampling in the sample phase include switchably coupling a capacitor to an output of the amplifier such that the capacitor is coupled between the output of the amplifier and a ground node; and
- converting a comparison, of the sampling of the input analog voltage relative to a reference voltage, to a digital value in a conversion phase while providing the amplifier a second set of electrical attributes differing from the first set of electrical attributes, wherein the converting in the conversion phase includes decoupling the capacitor from the output of the amplifier.
19. The method of claim 18:
- wherein the first set of electrical attributes comprises a first frequency bandwidth; and
- wherein the second set of electrical attributes comprises a second frequency bandwidth larger than the first frequency bandwidth.
20. The method of claim 18:
- wherein the first set of electrical attributes comprises a first frequency bandwidth with a first upper corner frequency; and
- wherein the second set of electrical attributes comprises a second frequency bandwidth with a second upper corner frequency larger than the first upper corner frequency.
21. The circuit of claim 1 further comprising a resistor coupled between the output of the transconductor and the ground node in parallel with the second switch and the second capacitor.
Type: Application
Filed: Dec 30, 2020
Publication Date: Jun 30, 2022
Inventors: Krishnaswamy Nagaraj (Plano, TX), Joonsung Park (Allen, TX)
Application Number: 17/137,691