Patents by Inventor Krishnaswamy Nagaraj

Krishnaswamy Nagaraj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200204183
    Abstract: A circuit includes a first filter, a plurality of binary-weighted capacitors, and a current source device. The circuit also includes a first plurality of switches. Each of the first plurality of switches is connected to a separate capacitor of the plurality of binary-weighted capacitors. The first plurality of switches are connected together, and the first plurality of switches are not connected to the first filter. A second plurality of switches is also included, and each of the second plurality of switches is connected to a separate capacitor of the plurality of binary-weighted capacitors and to the first filter and to a control input of the current source device. The first plurality of switches are not connected to the control input.
    Type: Application
    Filed: December 23, 2018
    Publication date: June 25, 2020
    Inventors: Krishnaswamy NAGARAJ, Wei FU
  • Patent number: 10666276
    Abstract: In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: May 26, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Krishnaswamy Nagaraj
  • Publication number: 20190215002
    Abstract: In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 11, 2019
    Inventor: Krishnaswamy Nagaraj
  • Patent number: 10277238
    Abstract: In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 30, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Krishnaswamy Nagaraj
  • Publication number: 20190039091
    Abstract: In described examples, a first and second driver each include a first-rail output transistor including a first terminal coupled to a first power rail and a second-rail output transistor including a first terminal coupled to a second power rail. The first-rail output transistor of each of the first and second drivers includes a second terminal coupled to a second terminal of the second-rail output transistor of an output node of each respective first and second driver. A resistive load includes a first terminal coupled to the first-driver output node and includes a second terminal coupled to the second-driver output node. A sampling circuit generates an indication of an impedance of at least one of the output transistors of the first and second drivers.
    Type: Application
    Filed: August 2, 2018
    Publication date: February 7, 2019
    Inventors: Krishnaswamy Nagaraj, Asif Qaiyum, Baher S. Haroun
  • Publication number: 20180219555
    Abstract: In some embodiments, an analog-to-digital converter (ADC) comprises a loop filter configured to produce an error signal based on a difference between an analog input signal and a feedback signal. The ADC also comprises a main comparator set comprising one or more main comparators, the main comparator set configured to digitize the error signal and further configured to drive a main digital-to-analog converter (DAC). The ADC further comprises an auxiliary comparator set comprising a plurality of auxiliary comparators, the auxiliary comparator set configured to digitize the error signal when the ADC is in a runaway state and further configured to drive an auxiliary DAC to bring the error signal into a predetermined range.
    Type: Application
    Filed: June 20, 2017
    Publication date: August 2, 2018
    Inventor: Krishnaswamy NAGARAJ
  • Patent number: 9762259
    Abstract: A notch filter in a sigma-delta modulator loop filter increases SNR by limiting in-band quantization noise around a frequency to which the notch filter is precisely tuned. A tuning mode controller isolates the notch filter from other loop filter stages. A bias voltage is applied to the notch filter, causing it to resonate. Tuning mode switches insert the notch filter into a frequency-locked loop (“FLL”) circuit as a variable frequency oscillator component of the FLL. An ADC operational mode input signal is applied to the FLL as a reference signal. A tuning control component of the FLL adjusts a tunable feedback element in the notch filter to drive the FLL error signal to zero in order to precisely tune the notch filter to the center frequency of the ADC input signal. Tuning inputs to the tunable feedback element are then latched prior to re-inserting the notch filter into the modulator.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: September 12, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiao Pu, Krishnaswamy Nagaraj, Peng Cao
  • Patent number: 9692445
    Abstract: A system includes a storage device containing machine instructions and a plurality of digital values of an oversampled sinuisoidal signal. The system also includes a core coupled to the storage. The core is configured to execute the machine instructions, wherein, when executed, the machine instructions cause the core to implement a sigma-delta modulator that retrieves the plurality of digital values from the storage device as input to the modulator. The sigma-delta modulator is configured compute an output bit stream. The system further includes an analog filter configured to receive the output bit stream from the core and to low-pass filter the output bit stream to produce a sinusoidal output signal.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: June 27, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Brent Peterson, Joonsung Park, Krishnaswamy Nagaraj, Tyler Witt
  • Publication number: 20160301418
    Abstract: A phase-locked loop (PLL) includes a state machine programmed to automatically produce a set of control signals to select a charge-pump current and integrating capacitance value to automatically adjust a loop bandwidth of the PLL. A charge-pump DAC generates a charge-pump current of magnitude controlled by the state machine control signals. An integrator integrates the charge-pump output current to produce an integrated charge-pump output signal. The integrator has a plurality of capacitors switchably selected by control signals from the state machine to produce an integrating capacitance value. A voltage controlled oscillator (VCO) produces a PLL output frequency in response to the integrated charge-pump output signal.
    Type: Application
    Filed: June 21, 2016
    Publication date: October 13, 2016
    Inventors: Ajay Kumar, Krishnaswamy Nagaraj, Joonsung Park
  • Patent number: 9438266
    Abstract: A direct current (“DC”) calibration reference voltage is applied at an input terminal of an N-level sigma-delta analog-to-digital converter (“ADC”). The ADC includes a current-mode DAC (“I-DAC”) operating as a feedback element. A count of logical 1s associated with each of N output levels is taken at outputs of a modulator portion of the ADC during a first mismatch measurement interval. Mismatch measurement logic subsequently transposes pairs of current sources between level selection switch matrices. Doing so causes modulator output error components resulting from mismatches between I-DAC current sources (“delta”) to appear as differential level-specific output counts. The mismatch measurement logic compares the differential counts to determine values of delta. The ADC then factors decimated modulator output counts by values of delta in order to correct for the I-DAC current source mismatch(es).
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: September 6, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishnaswamy Nagaraj, Manish Goel, Xiao Pu, Hun-Seok Kim
  • Patent number: 9401722
    Abstract: A phase-locked loop (PLL) includes a state machine programmed to automatically produce a set of control signals to select a charge-pump current and integrating capacitance value to automatically adjust a loop bandwidth of the PLL. A charge-pump DAC generates a charge-pump current of magnitude controlled by the state machine control signals. An integrator integrates the charge-pump output current to produce an integrated charge-pump output signal. The integrator has a plurality of capacitors switchably selected by control signals from the state machine to produce an integrating capacitance value. A voltage controlled oscillator (VCO) produces a PLL output frequency in response to the integrated charge-pump output signal.
    Type: Grant
    Filed: June 16, 2012
    Date of Patent: July 26, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ajay kumar, Krishnaswamy Nagaraj, Joonsung Park
  • Patent number: 9395253
    Abstract: A temperature sensor uses a semiconductor device that has a known voltage drop characteristic that is proportional to absolute temperature (PTAT). A controllable current source is coupled to the semiconductor device and is operable to sequentially inject a bias current having a value I(bias) and fixed ratio N of I(bias) into the semiconductor device. A delta sigma analog to digital converter (ADC) has an input coupled to the semiconductor device. The delta sigma ADC is configured to sample and integrate a sequence of voltages pairs produced across the semiconductor device by repeatedly injecting an ordered sequence of selected bias currents into the semiconductor device. The ordered sequence of selected bias currents comprises M repetitions of (N×I(bias); I(bias)) and one repetition of (M×I(bias); M×N×I(bias)).
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: July 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mikel K. Ash, Xiao Pu, Joonsung Park, Krishnaswamy Nagaraj
  • Patent number: 9335223
    Abstract: Methods and circuits for measuring the temperature of a transistor are disclosed. An embodiment of the method includes, providing a current into a circuit, wherein the circuit is connected to the transistor. A variable resistance is connected between the base and collector of the transistor. The circuit has a first mode and a second mode, wherein the current in the first mode flows into the base of the transistor and through the resistance and the current in the second mode flows into the emitter of the transistor. Voltages in both the first mode and the second mode are measured using different resistance settings. The temperature of the transistor is calculated based on the difference between the different voltages.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: May 10, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mikel K. Ash, Krishnaswamy Nagaraj, Paul Kimelman, Steve Vu
  • Patent number: 9310823
    Abstract: A voltage reference circuit includes a bipolar transistor and a circuit configured to measure the ratio of emitter current to base current of the bipolar transistor. The output voltage of the voltage reference circuit is compensated as a function of the measured ratio.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: April 12, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiao Pu, Krishnaswamy Nagaraj, Yue Hu
  • Publication number: 20160056831
    Abstract: An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC), a comparator and enhanced resolution SAR control logic. The DAC includes analog circuitry that is configured to convert an M-bit digital input to an analog output. The comparator includes a plurality of coupling capacitors. The enhanced resolution SAR control logic is configured to generate an M-bit approximation of an input voltage and to store a residue voltage in at least one of the coupling capacitors. The residue voltage represents a difference between the input voltage and the M-bit approximation of the input voltage. The enhanced resolution SAR control logic is further configured to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M.
    Type: Application
    Filed: August 19, 2014
    Publication date: February 25, 2016
    Inventors: Joonsung Park, Krishnaswamy Nagaraj, Mikel Ash
  • Patent number: 9252800
    Abstract: An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC), a comparator and enhanced resolution SAR control logic. The DAC includes analog circuitry that is configured to convert an M-bit digital input to an analog output. The comparator includes a plurality of coupling capacitors. The enhanced resolution SAR control logic is configured to generate an M-bit approximation of an input voltage and to store a residue voltage in at least one of the coupling capacitors. The residue voltage represents a difference between the input voltage and the M-bit approximation of the input voltage. The enhanced resolution SAR control logic is further configured to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: February 2, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Joonsung Park, Krishnaswamy Nagaraj, Mikel Ash
  • Patent number: 9197238
    Abstract: An analog-to-digital conversion system and method includes, for example, a comparator for sampling an analogy quantity during a sampling period and for performing a series of bit-wise conversions on the sampled analog sample during a conversion period, where each bit-wise conversion occurs during a respective bit-wise conversion cycle in which successive bits of a sample are successively determined during a respective bit conversion cycle and in which a predetermined number of bit-wise conversions are to be performed. A clock generator is arranged for generating a clock signal for clocking the converter during the conversion period, wherein each bit conversion cycle includes a reset period having a first length and an amplification period having a second length, wherein one of the first and second lengths is dynamically selected.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: November 24, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishnaswamy Nagaraj, Joonsung Park, Ajay Kumar
  • Publication number: 20150309525
    Abstract: A voltage reference circuit includes a bipolar transistor and a circuit configured to measure the ratio of emitter current to base current of the bipolar transistor. The output voltage of the voltage reference circuit is compensated as a function of the measured ratio.
    Type: Application
    Filed: April 28, 2014
    Publication date: October 29, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Xiao Pu, Krishnaswamy Nagaraj, Yue Hu
  • Publication number: 20150003490
    Abstract: A temperature sensor uses a semiconductor device that has a known voltage drop characteristic that is proportional to absolute temperature (PTAT). A controllable current source is coupled to the semiconductor device and is operable to sequentially inject a bias current having a value I(bias) and fixed ratio N of I(bias) into the semiconductor device. A delta sigma analog to digital converter (ADC) has an input coupled to the semiconductor device. The delta sigma ADC is configured to sample and integrate a sequence of voltages pairs produced across the semiconductor device by repeatedly injecting an ordered sequence of selected bias currents into the semiconductor device. The ordered sequence of selected bias currents comprises M repetitions of (N×I(bias); I(bias)) and one repetition of (M×I(bias); M×N×I(bias)).
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Mikel K. Ash, Xiao Pu, Joonsung Park, Krishnaswamy Nagaraj
  • Publication number: 20140314124
    Abstract: Methods and circuits for measuring the temperature of a transistor are disclosed. An embodiment of the method includes, providing a current into a circuit, wherein the circuit is connected to the transistor. A variable resistance is connected between the base and collector of the transistor. The circuit has a first mode and a second mode, wherein the current in the first mode flows into the base of the transistor and through the resistance and the current in the second mode flows into the emitter of the transistor. Voltages in both the first mode and the second mode are measured using different resistance settings. The temperature of the transistor is calculated based on the difference between the different voltages.
    Type: Application
    Filed: April 19, 2013
    Publication date: October 23, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Mikel K. Ash, Krishnaswamy Nagaraj, Paul Kimelman, Steve Vu