MULTI-LEVEL BUCK CONVERTER AND ASSOCIATE CONTROL CIRCUIT THEREOF
A control circuit for controlling multi-level buck converter. The multi-level buck converter has N pairs of switches, and N is an integer equal to or greater than 2. The control circuit has a comparing circuit comparing a voltage feedback signal with a reference signal to generate a comparing signal, a selecting circuit receiving the comparing signal to generate N set signals, and N COT controllers. The N set signals take turns to change from inactive state to active state at each rising edge of the comparing signal. Each of the N COT controllers receives output voltage signal, input voltage signal and one corresponding set signal of N set signals to generate a corresponding control signal to control the corresponding pair of switches to perform a complementary on and off switching.
The present invention relates to electrical circuit, more particularly but not exclusively relates to multi-level buck converter.
BACKGROUNDAs compared to a conventional buck (single-phase) converter, a multi-level buck converter has several advantages. For instance, the switching stresses of those switches of multi-level buck converters are lower than those of conventional buck converters. Moreover, the ripple in multi-buck converters could remarkably be reduced as compared to the ripple at the same switching speed for the conventional buck converter.
For example, as shown in
Therefore, switching state 00 indicates switch transistors M1a and M2a are off while switch transistors M1b and M2b are on such that an inductor current flowing through the inductor LOUT is freewheeling through switch transistors M1b and M2b. In switching state 01, switch transistors M1a and M2b are off while switch transistors M1b and M2a are on such that the first flying capacitor voltage C1 is discharged to drive a switch node voltage signal VSW at one-half of an input voltage signal VIN of the three-level buck converter. In switching state 10, switch transistors M1a and M2b are on while switch transistors M1b and M2a are off such that the first flying capacitor voltage C1 is charged by the input voltage signal VIN to drive the switch node voltage signal VSW at ½ VIN. In switching state 11, switch transistors M1a and M2a are on while switch transistors M1b and M2b are off such that the switch node voltage signal VSW is equal to the input voltage signal VIN. The switching states of the three-level buck converter are summarized in the following Table 1:
Furthermore, Table 2 illustrates a potential of the switch node voltage signal VSW, a potential of the first terminal of the first flying capacitor C1+ and a potential of the second terminal of the first flying capacitor C1− for different switching states.
From Table 2, it could be found that the potential of the switch node voltage signal VSW is switched among a potential of a logic ground (labeled as 0V), one-half of a potential of the input voltage signal VIN (labeled as VIN), and the potential of the input voltage signal VIN (labeled as ½VIN). As compared to a conventional buck converter, the root-mean-square (RMS) of the switch node voltage signal VSW of the three-level buck converter may be reduced by 50%. This reduction of the switch node voltage signal VSW also reduces the switching voltage stresses on the switching transistors. Given the reduced voltage stress, the breakdown voltage ratings for the switching transistors may also be reduced as compared to these of the conventional buck converter. Multi-level buck converters thus offer reduced conduction losses for its switch transistors.
Although the multi-level buck converters offer advantageous properties over conventional buck converters, these advantages come at the cost of increased regulation complexity. Besides increased regulation complexity, the multi-level buck converter creates a number of control stability issues that are not appeared in conventional buck converters, especially when the multi-level buck converter transits from one operation state to another operation state. It is thus conventional to limit multi-level buck converter to work in one of the operation states, which may limit a range of duty cycle which is defined as the ratio of an output voltage signal VOUT to the input voltage signal VIN of the multi-level buck converter. Therefore, it is desired to have an improved control solution for multi-level buck converter with a wide range of duty cycle and good stability.
SUMMARYIn accomplishing the above and other objects, there has been provided, in accordance with an embodiment of the present invention, a control circuit for controlling a multi-level buck converter having N pairs of switches serially connected between an input terminal and a logic ground, and wherein N is an integer equal to or greater than 2. The control circuit comprises a comparing circuit, a selecting circuit and N COT controllers. The comparing circuit is configured to receive a reference signal and a voltage feedback signal indicative of an output voltage signal of the multi-level buck converter, and further configured to compare the voltage feedback signal with the reference signal to generate a comparing signal. The selecting circuit is configured to receive the comparing signal, and further configured to generate N set signals based on the comparing signal. For each i=1, 2, . . . , N, the ith COT controller is configured to receive the corresponding ith set signal, the output voltage signal and an input voltage signal of the multi-level buck converter, and further configured to generate an ith control signal to control the ith pair of switches to perform a complementary on and off switching based on the corresponding ith set signal, the output voltage signal and the input voltage signal.
In accordance with an embodiment of the present invention, there has been provided a multi-level buck converter comprising N pairs of switches, comparing circuit, a selecting circuit and N COT controllers. The N pairs of switches are serially connected between an input terminal and a logic ground, wherein N is an integer equal to or greater than 2. The comparing circuit is configured to receive a reference signal and a voltage feedback signal indicative of an output voltage signal of the multi-level buck converter, and further configured to compare the voltage feedback signal with the reference signal to generate a comparing signal. The selecting circuit is configured to receive the comparing signal, and further configured to generate N set signals based on the comparing signal. For each i=1, 2, . . . , N, the ith COT controller is configured to receive the corresponding ith set signal, the output voltage signal and an input voltage signal of the multi-level buck converter, and further configured to generate an ith control signal to control the ith pair of switches to perform a complementary on and off switching based on the corresponding ith set signal, the output voltage signal and the input voltage signal.
In accordance with an embodiment of the present invention, there has been provided an multi-level buck converter comprising two pairs of switches serially connected between an input terminal and a logic ground, a comparing circuit, a selecting circuit, a first COT controller and a second COT controller. The comparing circuit is configured to compare a voltage feedback signal indicative of an output voltage signal of the multi-level buck converter with a reference signal to generate a comparing signal. The selecting circuit is configured to receive the comparing signal, and further configured to generate a first set signal and a second set signal based on the comparing signal. The first COT controller is configured to receive the first set signal, the output voltage signal and an input voltage signal of the multi-level buck converter, and further configured to generate a first control signal to control the first pair of switches to perform a complementary on and off switching based on the first set signal, the output voltage signal and the input voltage signal. The second COT controller is configured to receive the second set signal, the output voltage signal and the input voltage signal, and further configured to generate a second control signal to control the second pair of switches to perform a complementary on and off switching based on the second set signal, the output voltage signal and the input voltage signal.
Non-limiting and non-exhaustive embodiments are described with reference to the following drawings.
The use of the same reference label in different drawings indicates the same or like components.
In the present application, numerous specific details are provided, such as examples of circuits, components, and methods, to provide a thorough understanding of embodiments of the invention. These embodiments are exemplary, not to confine the scope of the invention. Persons of ordinary skill in the art will recognize, however, that the invention can be practiced without one or more of the specific details. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention. Some phrases are used in some exemplary embodiments. However, the usage of these phrases is not confined to these embodiments.
Several embodiments of the present invention are described below with reference to battery charge and discharge circuit and associated control circuit.
Note that the switch node voltage signal VSW at the switching node SW may comprise four voltage potentials: one-third of the potential of the input voltage signal VIN (labeled as ⅓VIN), two-third of the potential of the input voltage signal VIN (labeled as ½VIN), the potential of the input voltage signal VIN (labeled as VIN) and the potential of the logic ground (labeled as 0 V). Given these four possible potentials, the multi-level buck converter illustrated in
In the exemplary embodiment of
In the exemplary embodiment of
In the exemplary embodiment of
The first COT controller 301 may be configured to receive the output voltage signal VOUT, the input voltage signal VIN and the first set signal CA1. When the first set signal CA1 is in the active state, the first COT controller 301 may be configured to generate a first control signal PWM1 in accordance with the output voltage signal VOUT, the input voltage signal VIN and the first set signal CA1 to control the first pair of switching transistors M1a and M1b. In an embodiment, when the first set signal CA1 is in the active state, the first control signal PWM1 is configured to turn the first high side switch transistor M1a on and turn the first low side switch transistor M1b off.
The second COT controller 302 may be configured to receive the output voltage signal VOUT, the input voltage signal VIN and the second set signal CA2. When the second set signal CA2 is in the active state, the second COT controller 302 may be configured to generate a second control signal PWM2 in accordance with the output voltage signal VOUT, the input voltage signal VIN and the second set signal CA2 to control the second pair of switching transistors M2a and M2b. In an embodiment, when the second set signal CA2 is in the active state, the second control signal PWM2 is configured to turn the second high side switch transistor M2a on and turn the second low side switch transistor M2b off.
The third COT controller 303 may be configured to receive the output voltage signal VOUT, the input voltage signal VIN and the third set signal CA3. When the third set signal CA3 is in the active state, the third COT controller 303 may be configured to generate a third control signal PWM3 in accordance with the output voltage signal VOUT, the input voltage signal VIN and the third set signal CA3 to control the third pair of switching transistors M3a and M3b. In an embodiment, when the third set signal CA3 is in the active state, the third control signal PWM3 is configured to turn the third high side switch transistor M3a on and turn the third low side switch transistor M3b off.
In an embodiment, each of the first, the second and the third control signal PWM1-PWM3 may comprise a high side control signal and a low side control signal to respectively control the corresponding pair of switching transistors. For example, the first control signal PWM1 may comprise a first high side control signal PWM1a (as illustrated in the following
In the exemplary embodiment of
As shown in
In switching state 100, switch transistors M1a, M2b and M3b are on while switch transistors M1b, M2a and M3a are off such that the first flying capacitor voltage C1 is charged by the input voltage signal VIN to drive the switch node voltage signal VSW at ⅓VIN. Meanwhile, the second flying capacitor C2 is floating during switching state 100.
In switching state 010, switch transistors M1a, M2b and M3a are off while switch transistors M1b, M2a and M3b are on such that the first flying capacitor voltage C1 is discharged and the second flying capacitor C2 is charged to drive the switch node voltage signal VSW at ⅓VIN.
In switching state 001, switch transistors M1a, M2a and M3b are off while switch transistors M1b, M2b and M3a are on such that the second flying capacitor C2 is discharged to drive the switch node voltage signal VSW at ⅓VIN. Meanwhile, the first flying capacitor C1 is floating during switching state 001.
In switching state 110, switch transistors M1a, M2a and M3b are on while switch transistors M1b, M2b and M3a are off such that the second flying capacitor C2 is charged by the input voltage signal VIN to drive the switch node voltage signal VSW at ⅔VIN. Meanwhile, the first flying capacitor C1 is floating during switching state 110.
In switching state 011, switch transistors M1a, M2b and M3b are off while switch transistors M1b, M2a and M3a are on such that the first flying capacitor voltage C1 is discharged to drive the switch node voltage signal VSW at ⅔VIN. Meanwhile, the second flying capacitor C2 is floating during switching state 011.
In switching state 101, switch transistors M1a, M2b and M3a are on while M1b, M2a and M3b are off such that the first flying capacitor voltage C1 is charged and the second flying capacitor C2 is discharged to drive the switch node voltage signal VSW at ⅔VIN.
In switching state 111, switch transistors M1a, M2a and M3a are on while M1b, M2b and M3b are off such that the switch node voltage signal VSW is charged to be equal to the input voltage signal VIN.
The switching states of the four-level buck converter 100 are summarized in the following Table 3:
Furthermore, Table 4 illustrates a potential of the switch node voltage signal VSW, a potential of the first terminal of the first flying capacitor C1+, a potential of the second terminal of the first flying capacitor C1−, a potential of the first terminal of the second flying capacitor C2+, and a potential of the second terminal of the second flying capacitor C2− for different switching states.
As compared to a conventional buck converter, the root-mean-square (RMS) of the switch node voltage signal VSW of the four-level buck converter 100 is reduced by ⅔. From Table 4, it could be found that the potential of the switch node voltage signal VSW is switched among a potential of the logic ground (labeled as 0V), one-third of the potential of the input voltage signal VIN (labeled as ⅓VIN), two-third of the potential of the input voltage signal VIN (labeled as ⅔VIN), and the potential of the input voltage signal VIN (labeled as VIN). Meanwhile, the four-level buck converter has a first, a second, and a third operation states by controlling the set of six switch transistors operating and transiting in the eight switching states. Specifically, in the first operation state, the switch node voltage signal VSW is switched between 0V and ⅓VIN if the output voltage signal VOUT is smaller than one-third of the input voltage signal VIN. In the second operation state, the potential of the switch node voltage signal VSW is switched between ⅓VIN and ⅔VIN if the output voltage signal VOUT is greater than one-third of the input voltage signal VIN and smaller than two-third of the input voltage signal VIN. In the third operation state, the potential of the switch node voltage signal VSW is switched between ⅔VIN and VIN if the output voltage signal VOUT is greater than two-third of the input voltage signal VIN and smaller than the input voltage signal VIN.
As shown in
As shown in
The first AND logic gate 201 is configured to receive the comparing signal CA and the first enable signal EN1, and further configured to conduct a logic AND operation of the comparing signal CA and the first enable signal EN1 to generate the first set signal CA1.
The second AND logic gate 202 is configured to receive the comparing signal CA and the second enable signal EN2, and further configured to conduct a logic AND operation of the comparing signal CA and the second enable signal EN2 to generate the second set signal CA2.
The first AND logic gate 201 is configured to receive the comparing signal CA and the third enable signal EN3, and further configured to conduct a logic AND operation of the comparing signal CA and the third enable signal EN3 to generate the third set signal CA3.
As can be appreciated,
The error amplifier 102 may have a first input terminal configured to receive the voltage feedback signal VFB, a second input terminal configured to receive the reference signal VREF, and an output terminal. The error amplifier 102 may be configured to compare the voltage feedback signal VFB with the reference signal VREF to generate an error signal EA at its output terminal, wherein the error signal EA is indicative of the difference of the voltage feedback signal VFB and the reference signal VREF.
The ramp generator 103 may be configured to receive the first control signal PWM1, and start to generate a ramp signal Ramp1 at the moment once the first high side switch transistor M1a is turned on, e.g., the first control signal PWM1 is changed from the inactive stage to the active state, in each switching period T.
The ramp generator 104 may be configured to receive the second control signal PWM2, and start to generate a ramp signal Ramp2 at the moment once the second high side switch transistor M2a is turned on, e.g., the second control signal PWM2 is changed from the inactive stage to the active state, in each switching period T.
The ramp generator 105 may be configured to receive the third control signal PWM3, and start to generate a ramp signal Ramp3 at the moment once the third high side switch transistor M3a is turned on, e.g., the third control signal PWM3 is changed from the inactive stage to the active state, in each switching period T.
The adder 106 may be configured to receive the voltage feedback signal VFB, the ramp signal Ramp1, the ramp signal Ramp2, and the ramp signal Ramp3, and further configured to conduct an add operation of the voltage feedback signal VFB, the ramp signal Ramp1, the ramp signal Ramp2 and the ramp signal Ramp3 to generate a sum signal Ramp_sum.
The voltage comparator 107 may have a first input terminal configured to receive the error signal EA, a second input terminal configured to receive the sum signal Ramp_sum, and an output terminal. The voltage comparator 107 may be configured to compare the error signal EA with the sum signal Ramp_sum to generate the comparing signal CA at its output terminal. In an embodiment, the comparing circuit 10 of
The current limiting circuit 40 may be configured to determine whether these current sense signals (CS1, CS2, and CS3) are larger than a current limit value ILIM, and further configured to generate an over current instruction signal OC at the output terminal of the current limiting circuit 40. The over current instruction signal OC may be a logic signal having an active state and an inactive state. In an embodiment, the over current instruction signal OC is in the active state (e.g., the logic low state) if any one of the current sense signal CS1, the current sense signal CS2 and the current sense signal CS3 is larger than the current limit value ILIM, otherwise the over current instruction signal OC is in the inactive state (e.g., the logic high state).
In the exemplary embodiment of
In the exemplary embodiment of
the four-level buck converter 500 may have no ripples to sense so that the four-level buck converter 500 may have stability issues, wherein k is a proportional coefficient may be varied in different systems. That is to say, if the output voltage signal VOUT falls in a range from
or in a range from
the four-level buck converter 100 may have stability issues. In an embodiment, the proportional coefficient k is smaller than 10, e.g., 5. Comparing with the four-level buck converter 500 of
The delay circuit 50 may be configured to receive the input voltage signal VIN, the output voltage signal VOUT, and three set signals (CA1, CA2, and CA3), and further configured to generate three delay set signals (CA1-dly, CA2-dly, and CA3-dly) based on the input voltage signal VIN, the output voltage signal VOUT and the three set signals (CA1, CA2, and CA3). In a four-level buck converter, only one of the set signals (CA1, CA2, or CA3) is delayed to generate a corresponding delay set signal when the output voltage signal VOUT is close to ⅓VIN or ⅔VIN. Meanwhile, the remaining set signals are unchanged. For instance, as shown in
In the exemplary embodiment of
The voltage divider 501 is configured to receive the input voltage signal VIN to generate a dividing voltage signal having a potential of ⅓VIN and a dividing voltage signal having a potential of ⅔VIN.
The hysteresis comparator 5021 may be configured to receive the output voltage signal VOUT and the dividing voltage signal having the potential of ⅓VIN, and further configured to compare the output voltage signal VOUT with the dividing voltage signal having the potential of ⅓VIN to generate a first determining signal DET1. In an embodiment, the hysteresis comparator 5021 predetermines the proportional coefficient k. When the output voltage signal VOUT is larger than
while smaller than
the first determining signal DET1 is in an active state (e.g., the logic high state).
The hysteresis comparator 5022 may be configured to receive the output voltage signal VOUT and the dividing voltage signal having the potential of ⅔VIN, and further configured to compare the output voltage signal VOUT and the dividing voltage signal having the potential of ⅔VIN to generate a second determining signal DET2. In an embodiment, the hysteresis comparator 5022 predetermines the proportional coefficient k. When the output voltage signal VOUT is larger than
while smaller than
the second determining signal DET2 is in an active state (e.g., the logic high state).
The OR logic gate 503 is configured to receive the first determining signal DET1 and the second determining signal DET2, and configured to conduct a logic operation of the first determining signal DET1 and the second determining signal DET2 to generate a delay enable signal EN-dly. The delay enable signal EN-dly may be a logic signal having an active state and an inactive state. In an embodiment, the delay enable signal EN-dly is in the active state (e.g., the logic high state) if one of the first determining signal DET1 and the second determining signal DET2 is in the active state, otherwise the delay enable signal EN-dly is in the inactive state (e.g., the logic low state).
The delay module 504 may be configured to delay the first set signal CA1 to generate a delay set signal CA1-dly when the delay enable signal EN-dly is in the active state.
Similarly as the four-level buck converter 600, the multi-level buck converter 700 may further comprise a control circuit which comprises the comparing circuit 10, the selecting circuit 20, the current limiting circuit 40, the delay circuit 50 and N COT controllers (301, 302, . . . , 30N).
In the exemplary embodiment of
The current limiting circuit 40 may be configured to determine whether any one of the N current sense signals (CS1, CS2, . . . , CSN) is larger than a current limit value ILIM, and further configured to generate the over current instruction signal OC based on the N current sense signals (CS1, CS2, . . . , CSN). If any one of the N current sense signals (CS1, CS2, . . . , CSN) is larger than the current limit value ILIM, the over current instruction signal OC is in the active state.
The delay circuit 50 may be configured to receive the input voltage signal VIN, the output voltage signal VOUT, and the N set signals (CA1, CA2, . . . , CAN), and further configured to generate N delay set signals
(CA1-dly, CA2-dly, . . . , CAN-dly) when the output voltage signal VOUT is close to
i.e., the output voltage signal VOUT falls in
Herein, k is a proportional coefficient may be varied in different systems.
In an embodiment, when N is an odd number, there are (N−1)/2 set signals may be delayed. For each i=1, . . . , N−1)/2, the delay circuit is configured to delay the (2i−1)th set signal CA(2i−1) to generate the (2i−1)th delay set signal CA(2i−1)-dly once the output voltage signal VOUT falls in
Meanwhile, the delay circuit 50 may be configured to keep the remaining (N+1)/2 set signals unchanged.
In an embodiment, when N is an odd number, there are (N−1)/2 set signals may be delayed. For each i=1, . . . , (N−1)/2, the delay circuit is configured to delay the (2i+1)th set signal CA(2i+1) to generate the (2i+1)th delay set signal CA(2i+1)-dly once the output voltage signal VOUT falls in
Meanwhile, the delay circuit 50 may be configured to keep the remaining (N+1)/2 set signals unchanged.
In an embodiment, when N is an odd number, there are (N−1)/2 set signals may be delayed. For each i=1, . . . , (N−1)/2, the delay circuit is configured to delay the (2i)th set signal CA(2i) to generate the (2i)th delay set signal CA(2i)-dly once the output voltage signal VOUT falls in
Meanwhile, the delay circuit 50 may be configured to keep the remaining (N+1)/2 set signals unchanged.
In an embodiment, when N is an even number, there are N/2 set signals may be delayed. For each i=1, . . . , N/2, the delay circuit is configured to delay the (2i−1)th set signal CA(2i−1) to generate the (2i−1)th delay set signal CA(2i−1)-dly once the output voltage signal VOUT falls in
Meanwhile, the delay circuit 50 may be configured to keep the remaining N/2 set signals unchanged.
In an embodiment, when N is an even number, there are N/2 set signals may be delayed. For each i=1, . . . , N/2, the delay circuit is configured to delay the (2i)th set signal CA(2i) to generate the (2i)th delay set signal CA(2i)-dly once the output voltage signal VOUT falls in
Meanwhile, the delay circuit 50 may be configured to keep the remaining N/2 set signals unchanged.
In the exemplary embodiment of
The voltage divider 501 is configured to receive the input voltage signal VIN to generate a plurality of dividing voltage signals.
For each i=1, . . . , N−1, the hysteresis comparator 502i may be configured to receive the output voltage signal VOUT and the corresponding dividing voltage signal having a potential of
and further configured to compare the output voltage signal VOUT with the dividing voltage signal having the potential of
to generate a corresponding determining signal DETi. In an embodiment, the hysteresis comparator 502i predetermines the proportional coefficient k. When the output voltage signal VOUT is larger than
while smaller than
the ith determining signal DETi is in an active state (e.g., the logic high state).
The OR logic gate 503 is configured to receive the N−1 determining signals (DET1, . . . , DET(N−1)), and configured to conduct a logic operation of the N−1 determining signals (DET1, . . . , DET(N−1)) to generate the delay enable signal EN-dly. In an embodiment, the delay enable signal EN-dly is in the active state (e.g., the logic high state) if any one of the N−1 determining signals (DET1, . . . , DET(N−1)) DETi is in the active state. Otherwise, the delay enable signal EN-dly is in the inactive state (e.g., the logic low state).
Each of the plurality of delay modules is configured to delay one corresponding set signal to generate a corresponding delay set signal when the delay enable signal EN-dly is in the active state.
In an embodiment, when N is an odd number, there are (N−1)/2 delay module. For each i=1, . . . , (N−1)/2, the delay module 504-i is configured to delay the (2i−1)th set signal CA(2i−1) to generate the (2i−1)th delay set signal CA(2i−1)-dly once the delay enable signal EN-dly is in the active state.
In an embodiment, when N is an odd number, there are (N−1)/2 delay module. For each i=1, . . . , (N−1)/2, the delay module 504-i is configured to delay the (2i+1)th set signal CA(2i+1) to generate the (2i+1)th delay set signal CA(2i+1)-dly once the delay enable signal EN-dly is in the active state.
In an embodiment, when N is an odd number, there are (N−1)/2 delay module. For each i=1, . . . , (N−1)/2, the delay module 504-i is configured to delay the (2i)th set signal CA(2i) to generate the (2i)th delay set signal CA(2i)-dly once the delay enable signal EN-dly is in the active state.
In an embodiment, when N is an even number, there are N/2 delay module. For each i=1, . . . , N/2, the delay module 504-i is configured to delay the (2i−1)th set signal CA(2i−1) to generate the (2i−1)th delay set signal CA(2i−1)-dly once the delay enable signal EN-dly is in the active state.
In an embodiment, when N is an even number, there are N/2 delay module. For each i=1, . . . , N/2, the delay module 504-i is configured to delay the (2i)th set signal CA(2i) to generate the (2i)th delay set signal CA(2i)-dly once the delay enable signal EN-dly is in the active state.
Obviously many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. It should be understood, of course, the foregoing invention relates only to a preferred embodiment (or embodiments) of the invention and that numerous modifications may be made therein without departing from the spirit and the scope of the invention as set forth in the appended claims. Various modifications are contemplated and they obviously will be resorted to by those skilled in the art without departing from the spirit and the scope of the invention as hereinafter defined by the appended claims as only a preferred embodiment(s) thereof has been disclosed.
Claims
1. A control circuit for controlling a multi-level buck converter having N pairs of switches serially connected between an input terminal and a logic ground, and wherein N is an integer equal to or greater than 2, the control circuit comprising:
- a comparing circuit, configured to receive a reference signal and a voltage feedback signal indicative of an output voltage signal of the multi-level buck converter, and further configured to compare the voltage feedback signal with the reference signal to generate a comparing signal;
- a selecting circuit, configured to receive the comparing signal, and further configured to generate N set signals based on the comparing signal; and
- N COT controllers, wherein for each i=1, 2,..., N, the ith COT controller is configured to receive a corresponding ith set signal of the N set signals, the output voltage signal and an input voltage signal of the multi-level buck converter, and further configured to generate an ith control signal to control a corresponding ith pair of switches of the N pairs of switches to perform a complementary on and off switching based on the corresponding ith set signal, the output voltage signal and the input voltage signal.
2. The control circuit of claim 1, wherein the comparing circuit comprises:
- an error amplifier, configured to receive the reference signal with the voltage feedback signal, and further configured to compare the reference signal with the voltage feedback signal to generate an error signal, wherein the error signal is indicative of the difference of the voltage feedback signal and the reference signal;
- N ramp generators, configured to generate N ramp signals, wherein for each i=1, 2,..., N, the ith ramp generator is configured to receive the ith control signal, and further configured to generate a corresponding ith ramp signal of the N ramp signals based on the ith control signal;
- an adder, configured to conduct an add operation of the voltage feedback signal and the N ramp signals to generate a sum signal; and
- a voltage comparator, configured to compare the sum signal with the error signal to generate the comparing signal.
3. The control circuit of claim 1, wherein the control circuit further comprises a delay circuit; and wherein
- the delay circuit is configured to receive the input voltage signal, the output voltage signal and the N set signals, and further configured to generate N delay set signals based on the input voltage signal, the output voltage signal and the N set signals; and wherein
- for each i=1, 2,..., N, the ith COT controller is configured to receive a corresponding ith delay set signal of the N delay set signals, the output voltage signal and the input voltage signal, and further configured to generate the ith control signal based on the corresponding ith delay set signal, the output voltage signal and the input voltage signal.
4. The control circuit of claim 3, wherein when N is an odd number, (N−1)/2 set signals are delayed, and wherein ( 1 ± k % ) × 1 N of the input voltage signal, ( 1 ± k % ) × 2 N of the input voltage signal,..., or ( 1 ± k % ) × N - 1 N of the input voltage signal, wherein k is a proportional coefficient.
- for each i=1,..., (N−1)/2, the delay circuit is configured to delay a corresponding (2i−1)th set signal of the N set signals to generate a corresponding (2i−1)th delay set signal of the N delay set signals once the output voltage signal falls in
5. The control circuit of claim 3, wherein when N is an odd number, (N−1)/2 set signals are delayed, and wherein ( 1 ± k % ) × 1 N of the input voltage signal, ( 1 ± k % ) × 2 N of the input voltage signal,..., or ( 1 ± k % ) × N - 1 N of the input voltage signal, wherein k is a proportional coefficient.
- for each i=1,..., (N−1)/2, the delay circuit is configured to delay a corresponding (2i+1)th set signal of the N set signals to generate a corresponding (2i+1)th delay set signal of the N delay set signals once the output voltage signal falls in
6. The control circuit of claim 3, wherein when N is an odd number, (N−1)/2 set signals are delayed, and wherein ( 1 ± k % ) × 1 N of the input voltage signal, ( 1 ± k % ) × 2 N of the input voltage signal,..., or ( 1 ± k % ) × N - 1 N of the input voltage signal, wherein k is a proportional coefficient.
- for each i=1,..., (N−1)/2, the delay circuit is configured to delay a corresponding (2i)th set signal of the N set signals to generate a corresponding (2i)th delay set signal of the N delay set signals once the output voltage signal falls in
7. The control circuit of claim 3, wherein when N is an even number, N/2 set signals are delayed, and wherein ( 1 ± k % ) × 1 N of the input voltage signal,..., or ( 1 ± k % ) × N - 1 N of the input voltage signal, wherein k is a proportional coefficient.
- for each i=1,..., N/2, the delay circuit is configured to delay a corresponding (2i−1)th set signal of the N set signals to generate a corresponding (2i−1)th delay set signal of the N delay set signals once the output voltage signal falls in
8. The control circuit of claim 3, wherein when N is an even number, N/2 set signals are delayed, and wherein ( 1 ± k % ) × 1 N of the input voltage signal,..., or ( 1 ± k % ) × N - 1 N of the input voltage signal, wherein k is a proportional coefficient.
- for each i=1,..., N/2, the delay circuit is configured to delay a corresponding (2i)th set signal of the N set signals to generate a corresponding (2i)th delay set signal of the N delay set signals once the output voltage signal falls in
9. The control circuit of claim 3, wherein the delay circuit comprises:
- a voltage divider, configured to receive the input voltage signal to generate N−1 dividing voltage signals, wherein for each i=1,..., N−1, a corresponding ith dividing voltage signal of the N−1 dividing voltage signals is equal to i/N of the input voltage signal;
- N−1 hysteresis comparators, configured to generate N−1 determining signals, wherein for each i=1,..., N−1, the ith hysteresis comparator is configured to receive the output voltage signal and the corresponding ith dividing voltage signal, and further configured to compare the output voltage signal with the corresponding ith dividing voltage signal to generate a corresponding ith determining signal of the N−1 determining signal;
- an OR logic gate, configured to receive the N−1 determining signals, and configured to conduct a logic OR operation of the N−1 determining signals to generate a delay enable signal; and
- a plurality of delay modules, wherein each of the plurality of delay modules is configured to receive the delay enable signal and one corresponding set signal of the N set signals, and further configured to generate one corresponding delay set signal based on the delay enable signal and the one corresponding set signal.
10. The control circuit of claim 9, wherein when N is an odd number, the quantity of the delay modules is equal to (N−1)/2, and wherein when N is an even number, the quantity of the delay modules is equal to N/2.
11. The control circuit of claim 1, wherein for each i=1, 2,..., N, the ith COT controller comprises:
- an ON time generator, configured to receive the corresponding ith set signal, the input voltage signal and the output voltage signal, and further configured to generate an on time signal based on the corresponding ith set signal, the input voltage signal and the output voltage signal; and
- a logic circuit, configured to receive the corresponding ith set signal and the on time signal, and further configured to conduct a logic operation of the corresponding ith set signal and the on time signal to generate the ith control signal.
12. The control circuit of claim 11, wherein the ON time generator comprises:
- a controlled current generator, having a first terminal configured to receive the input voltage signal and a second terminal, wherein the controlled current generator is configured to generate a controlled current signal at its second terminal based on the input voltage signal;
- a capacitor, connected between the second terminal of the controlled current generator and the logic ground;
- a controlled voltage generator, having a first terminal configured to receive the output voltage signal and a second terminal, wherein the controlled voltage generator is configured to generate a controlled voltage signal at its second terminal based on the output voltage signal;
- a charge comparator, having a first input terminal configured to receive the controlled voltage signal, a second input terminal configured to receive a voltage across the capacitor, and an output terminal, wherein the charge comparator is configured to compare the controlled voltage signal with the voltage across the capacitor to generate the on time signal at its output terminal; and
- a reset switch, having a first terminal coupled to the second terminal of the controlled current generator, a second terminal connected to the logic ground, and a control terminal receive the corresponding ith set signal.
13. The control circuit of claim 1, wherein the selecting circuit comprises:
- an enable circuit, configured to receive the comparing signal, and further configured to generate N enable signals based on the comparing signal, wherein the N enable signals take turns to change from an inactive state to an active state; and
- N AND logic gates, for each i=1, 2,..., N, the ith AND logic gate is configured to receive a corresponding ith enable signal of the N enable signals and the comparing signal, and further configured to conduct a logic AND operation of the corresponding ith enable signal of the N enable signals and the comparing signal to generate the corresponding ith set signal.
14. The control circuit of claim 1, wherein each of the N pair of switches comprises a high side switch and a low side switch; and wherein
- the control circuit further comprises a current limiting circuit configured to receive N current sense signals, and wherein for each i=1, 2,..., N, the ith current sense signal is indicative of a current flowing through the low side switch of the corresponding ith pair of switches; and wherein
- the current limiting circuit is further configured to respectively compare each of the N current sense signals with a current limit value to generate an over-current instruction signal; and wherein
- if any of the N current sense signals is larger than the current limit value, the over-current instruction signal is configured to turn all of the high side switches of the N pair of switches off.
15. The control circuit of claim 14, wherein the current limiting circuit comprises:
- N current comparators, for each i=1, 2,..., N, the ith current comparator has a first input terminal configured to receive the current limit value, a second input terminal configured to receive the ith current sense signal, and an output terminal, and wherein the ith current comparator is configured to compare the ith current sense signal with the current limit value to generate an ith instruction signal at its output terminal; and
- a current limiting AND logic gate, configured to receive N instruction signals, and further configured to conduct a logic AND operation of the N instruction signals to generate the over-current instruction signal.
16. The control circuit of claim 1, wherein the N set signals take turns to change from an inactive state to an active state at each rising edge of the comparing signal.
17. A multi-level buck converter, comprising:
- N pairs of switches, serially connected between an input terminal and a logic ground, wherein N is an integer equal to or greater than 2;
- a comparing circuit, configured to receive a reference signal and a voltage feedback signal indicative of an output voltage signal of the multi-level buck converter, and further configured to compare the voltage feedback signal with the reference signal to generate a comparing signal;
- a selecting circuit, configured to receive the comparing signal, and further configured to generate N set signals based on the comparing signal; and
- N COT controllers, wherein for each i=1, 2,..., N, the ith COT controller is configured to receive a corresponding ith set signal of the N set signals, the output voltage signal and an input voltage signal of the multi-level buck converter, and further configured to generate an ith control signal to control a corresponding ith pair of switches of the N pair of switches to perform a complementary on and off switching based on the corresponding ith set signal, the output voltage signal and the input voltage signal.
18. A multi-level buck converter, comprising:
- two pairs of switches, serially connected between an input terminal and a logic ground;
- a comparing circuit, configured to compare a voltage feedback signal indicative of an output voltage signal of the multi-level buck converter with a reference signal to generate a comparing signal;
- a selecting circuit, configured to receive the comparing signal, and further configured to generate a first set signal and a second set signal based on the comparing signal;
- a first COT controller, configured to receive the first set signal, the output voltage signal and an input voltage signal of the multi-level buck converter, and further configured to generate a first control signal to control the first pair of switches to perform a complementary on and off switching based on the first set signal, the output voltage signal and the input voltage signal; and
- a second COT controller, configured to receive the second set signal, the output voltage signal and the input voltage signal, and further configured to generate a second control signal to control the second pair of switches to perform a complementary on and off switching based on the second set signal, the output voltage signal and the input voltage signal.
19. The multi-level buck converter of claim 18, wherein the comparing circuit further comprises:
- an error amplifier, configured to receive the reference signal and the voltage feedback signal, and further configured to compare the reference signal with the voltage feedback signal to generate an error signal, wherein the error signal is indicative of the difference of the voltage feedback signal and the reference signal;
- a first ramp generator, configured to receive the first control signal, and further configured to generate a first ramp signal based on the first control signal;
- a second ramp generator, configured to receive the second control signal, and further configured to generate a second ramp signal based on the second control signal;
- an adder, configured to conduct an add operation of the voltage feedback signal, the first ramp signal and the second ramp signal to generate a sum signal; and
- a voltage comparator, configured to compare the error signal with the sum signal to generate the comparing signal.
20. The multi-level buck converter of claim 18, wherein the control circuit further comprises a delay circuit, and wherein the delay circuit is configured to receive the input voltage signal, the output voltage signal, the first set signal and the second set signal, and further configured to delay one of the first set signal and the second set signal to generate a delay set signal when the output voltage signal falls in 1 2 × ( 1 ± k % ) of the input voltage signal, and wherein k is a proportional coefficient.
Type: Application
Filed: May 26, 2021
Publication Date: Dec 8, 2022
Inventors: Di Han (San Jose, CA), Jian Jiang (Los Gatos, CA)
Application Number: 17/330,584