HYBRID POLYSILICON HETEROJUNCTION BACK CONTACT CELL
A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.
This application is a divisional of U.S. Pat. Application No. 16/983,770, filed on Aug. 3, 2020, which is a continuation of U.S. Pat. Application No. 15/269,727, filed on Sep. 19, 2016, which is a divisional of U.S. Pat. Application No. 14/614,355, filed on Feb. 4, 2015, now U.S. Pat. No. 9,466,750, issued on Oct. 11, 2016, which is a continuation of U.S. Pat. Application No. 14/083,141, filed on Nov. 18, 2013, now U.S. Pat. No. 8,962,373, issued on Feb. 24, 2015, which is a continuation of U.S. Pat. Application No. 13/333,904, filed on Dec. 21, 2011, now U.S. Pat. No. 8,597,970, issued Dec. 3, 2013, the entire contents of which are hereby incorporated by reference herein.
TECHNICAL FIELDEmbodiments of the subject matter described herein relate generally to solar cell manufacture. More particularly, embodiments of the subject matter relate to thin silicon solar cells and techniques for manufacture.
BACKGROUNDSolar cells are well known devices for converting solar radiation to electrical energy. They can be fabricated on a semiconductor wafer using semiconductor processing technology. A solar cell includes P-type and N-type diffusion regions. Solar radiation impinging on the solar cell creates electrons and holes that migrate to the diffusion regions, thereby creating voltage differentials between the diffusion regions. In a backside contact solar cell, both the diffusion regions and the metal contact fingers coupled to them are on the backside of the solar cell. The contact fingers allow an external electrical circuit to be coupled to and be powered by the solar cell.
Efficiency is an important characteristic of a solar cell as it is directly related to the solar cell’s capability to generate power. Accordingly, techniques for improving the fabrication process, reducing the cost of manufacturing and increasing the efficiency of solar cells are generally desirable. Such techniques include forming polysilicon and heterojunction layers on silicon substrates through thermal processes wherein the present invention allows for increased solar cell efficiency. These or other similar embodiments form the background of the current invention.
A more complete understanding of the subject matter can be derived by referring to the detailed description and claims when considered in conjunction with the following figures, wherein like reference numbers refer to similar elements throughout the figures.
The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.
A method of manufacturing solar cells is disclosed. The method comprises providing a silicon substrate having a thin dielectric layer on the back side, and a deposited silicon layer over the thin dielectric layer, forming a layer of doping material over the a deposited silicon layer, forming an oxide layer over the layer of doping material, partially removing the oxide layer, the layer of doping material and the deposited silicon layer in an interdigitated pattern, growing an oxide layer while simultaneously raising the temperature to drive the dopants from the layer of doping material into the deposited silicon layer, doping the deposited silicon layer with dopants from the layer of doping material to form a crystallized doped polysilicon layer, depositing a wide band gap doped semiconductor and an anti-reflective coating on the back side of the solar cell, and depositing a wide band gap doped semiconductor and anti-reflective coating on the front side of the solar cell.
Another method of manufacturing solar cells is disclosed. The method comprises providing a silicon substrate having a thin dielectric layer on the back side, and a deposited silicon layer over the thin dielectric layer, forming a layer of doping material over the deposited silicon layer, forming an oxide layer over the layer of doping material, partially removing the oxide layer, the layer of doping material and the deposited silicon layer in an interdigitated pattern, etching the exposed silicon substrate to form a texturized silicon region, growing an oxide layer while simultaneously raising the temperature to drive the dopants from the layer of doping material into the deposited silicon layer, doping the deposited silicon layer with dopants from the layer of doping material to form a doped polysilicon layer, covering a first thick layer of wide band gap doped amorphous silicon and anti-reflective coating on the back side of the solar cell, covering an second thin layer of wide band gap doped amorphous silicon and anti-reflective coating on the front side of the solar cell and wherein the thin layer is less than 10% to 30% of the thickness of the thick layer.
Still another method of manufacturing solar cells is disclosed. The method comprises providing a silicon substrate having a thin dielectric layer on the back side, and a doped silicon layer over the thin dielectric layer, forming an oxide layer over the doped silicon layer, partially removing the oxide layer and doped silicon layer in an interdigitated pattern, growing a silicon oxide layer over the back side of the solar cell by heating the silicon substrate in an oxygenated environment, wherein the silicon layer is crystallized to form a doped polysilicon layer, depositing a wide band gap doped semiconductor on the back side of the solar cell, and depositing a wide band gap doped semiconductor and anti-reflective coating on the front side of the solar cell.
Still another method of manufacturing solar cells is disclosed. The method comprises providing a silicon substrate having a thin dielectric layer on the back side, and a doped silicon layer over the thin dielectric layer, forming an oxide layer over the doped silicon layer, partially removing the oxide layer and doped silicon layer in an interdigitated pattern, etching the exposed silicon substrate to form a texturized silicon region, growing a silicon oxide layer over the back side of the solar cell by heating the silicon substrate in an oxygenated environment, wherein the silicon layer is crystallized to form a doped polysilicon layer, depositing a wide band gap doped amorphous silicon and an anti-reflective coating on the back side of the solar cell, and depositing a wide band gap doped amorphous silicon and anti-reflective coating on the front side of the solar cell.
Yet another embodiment for a method of manufacturing solar cells is disclosed. The method comprises providing a silicon substrate having a thin dielectric layer on the back side, and a doped silicon layer over the thin dielectric layer, forming an oxide layer over the doped silicon layer, partially removing the oxide layer and doped silicon layer in an interdigitated pattern, etching the exposed silicon substrate to form a texturized silicon region, growing a silicon oxide layer over the back side of the solar cell by heating the silicon substrate in an oxygenated environment, wherein the silicon layer is crystallized to form a doped polysilicon layer, simultaneously depositing a wide band gap doped amorphous silicon and an anti-reflective coating over the front side and back side of the solar cell, partially removing the wide band gap doped semiconductor and oxide layer to form a series of contact openings, and simultaneously forming a first metal grid being electrically coupled to the doped polysilicon layer and a second metal grid being electrically coupled to an emitter region on the back side of the solar cell.
An improved technique for manufacturing solar cells is to provide a thin dielectric layer and a deposited silicon layer on the back side of a silicon substrate. Regions of doped polysilicon can be formed by dopant driving into deposited silicon layers, or by in-situ formation of doped polysilicon regions. An oxide layer and a layer of a wide band gap doped semiconductor can then be formed on the front and back sides of the solar cell. One variant involves texturizing the front and back surfaces prior to formation of the oxide and wide band gap doped semiconductor formation. Contact holes can then be formed through the upper layers to expose the doped polysilicon regions. A metallization process then can be performed to form contacts onto the doped polysilicon layer. A second group of contacts can also be formed by directly connecting metal to emitter regions on the silicon substrate formed by the wide band gap semiconductor layer positioned between regions of the doped polysilicon on the back side of the solar cell.
The various tasks performed in connection with manufacturing processes are shown in
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The solar cell 200 can be further processed by partially removing first oxide layer 210, the doped polysilicon layer 250 and dielectric layer 206 to reveal an exposed region of silicon substrate 220 in an interdigitated pattern using conventional masking and etching processes. In the case of using conventional masking and etching processes, an ablation process can be used. If an ablation process is used, the first oxide layer 210 can be left partially intact over the doped polysilicon layer 250 as illustrated in
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The first wide band gap doped semiconductor layer 260 can be 10% to 30% thicker than the second wide band gap doped semiconductor layer 262. In other embodiments, the thickness can vary below 10% or greater than 30% without deviating from the techniques described herein. Both the wide band gap doped semiconductor layers 260, 262 can be positively-doped semiconductor, although in other embodiments with different substrate and polysilicon doped polarities, negatively-doped wide band gap semiconductor layers can also be used. Subsequently an anti-reflective coating (ARC) 270 can be deposited over the second wide band gap doped semiconductor 262. In one embodiment, the anti-reflective coating 270 can be comprised of silicon nitride. In some embodiments, the ARC can be deposited over the first wide band gap doped semiconductor layer 260 as well.
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While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope defined by the claims, which includes known equivalents and foreseeable equivalents at the time of filing this patent application.
Claims
1. A solar cell, comprising:
- a silicon substrate, wherein the silicon substrate has a first surface opposite a second surface;
- a thin oxide layer disposed on a first portion of the first surface of the silicon substrate;
- a thin dielectric layer disposed on a second portion of the first surface of the silicon substrate, wherein a portion of the thin oxide layer is in contact with and disposed over the thin dielectric layer;
- a first wide band gap doped semiconductor of a first conductivity type disposed on the thin oxide layer;
- a crystalline doped silicon of a second conductivity type disposed on the thin dielectric layer, wherein a portion of the first wide band gap doped semiconductor is disposed over the crystalline doped silicon and the thin dielectric layer;
- a doping material disposed on the crystalline doped silicon;
- a first contact disposed directly on the first wide band gap doped semiconductor; and
- a second contact disposed on the crystalline doped silicon, wherein the second contact is disposed over and through the doping material, first wide band gap doped semiconductor and the thin oxide layer.
2. The solar cell of claim 1, wherein the silicon substrate is an N-type bulk silicon.
3. The solar cell of claim 1, further comprising:
- a second wide band gap doped semiconductor disposed proximate to the second surface of the silicon substrate.
4. The solar cell of claim 3, further comprising:
- an anti-reflective coating disposed on the second wide band gap doped semiconductor.
5. The solar cell of claim 1, wherein the first wide band gap doped semiconductor has a band gap greater than 1.05 electron-Volts.
6. The solar cell of claim 1, wherein the first wide band gap doped semiconductor has a resistivity of greater than 10 ohm-cm.
7. The solar cell of claim 1, wherein the second surface of the silicon substrate comprises a texturized surface, and wherein the second wide band gap doped semiconductor is conformal to the texturized surface.
8. The solar cell of claim 1, wherein the first portion of the first surface of the silicon substrate comprises a texturized surface.
9. The solar cell of claim 8, wherein a portion of the first wide band gap doped semiconductor and a portion of the thin oxide layer are conformal to the texturized surface of the first surface.
10. The solar cell of claim 1, wherein the doping material comprises a positive-type doping material.
11. A method of fabricating a solar cell, the method comprising:
- forming a thin oxide layer on a first portion of a first surface of a silicon substrate, the first surface opposite a second surface;
- forming a thin dielectric layer on a second portion of the first surface of the silicon substrate, wherein a portion of the thin oxide layer is in contact with and over the thin dielectric layer;
- forming a first wide band gap doped semiconductor of a first conductivity type on the thin oxide layer;
- forming a crystalline doped silicon of a second conductivity type on the thin dielectric layer, wherein a portion of the first wide band gap doped semiconductor is over the crystalline doped silicon and the thin dielectric layer;
- forming a doping material on the crystalline doped silicon;
- forming a first contact directly on the first wide band gap doped semiconductor; and
- forming a second contact on the crystalline doped silicon, wherein the second contact is over and through the doping material, first wide band gap doped semiconductor and the thin oxide layer.
12. The method of claim 11, wherein the silicon substrate is an N-type bulk silicon.
13. The method of claim 11, further comprising:
- forming a second wide band gap doped semiconductor proximate to the second surface of the silicon substrate.
14. The method of claim 13, further comprising:
- forming an anti-reflective coating on the second wide band gap doped semiconductor.
15. The method of claim 11, wherein the first wide band gap doped semiconductor has a band gap greater than 1.05 electron-Volts.
16. The method of claim 11, wherein the first wide band gap doped semiconductor has a resistivity of greater than 10 ohm-cm.
17. The method of claim 11, wherein the second surface of the silicon substrate comprises a texturized surface, and wherein the second wide band gap doped semiconductor is conformal to the texturized surface.
18. The method of claim 11, wherein the first portion of the first surface of the silicon substrate comprises a texturized surface.
19. The method of claim 18, wherein a portion of the first wide band gap doped semiconductor and a portion of the thin oxide layer are conformal to the texturized surface of the first surface.
20. The method of claim 11, wherein the doping material comprises a positive-type doping material.
Type: Application
Filed: Mar 24, 2023
Publication Date: Jul 27, 2023
Inventors: Peter J. Cousins (Los Altos, CA), David D. Smith (Campbell, CA), Seung Bum Rim (Palo Alto, CA)
Application Number: 18/126,277