Patents by Inventor Seung Bum Rim
Seung Bum Rim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145604Abstract: Methods of fabricating a solar cell including metallization techniques and resulting solar cells, are described. In an example, forming a first semiconductor region and a second semiconductor region on the back side of a substrate. A first conductive busbar can be formed above the first semiconductor region. A first portion of a second conductive busbar can be formed above the second semiconductor region. A second portion of the second conductive busbar can be formed above the second semiconductor region, where a separation region separates the second portion and the first portion of the second conductive busbar. A third conductive busbar can be formed above the first semiconductor region. A first conductive bridge can be formed above the separation region, where the first conductive bridge electrically connects the first conductive busbar to the third conductive busbar.Type: ApplicationFiled: January 12, 2024Publication date: May 2, 2024Inventors: Matthieu Reich, SEUNG BUM RIM
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Patent number: 11967655Abstract: A bypass diode can include a first conductive region of a first conductivity type disposed above a substrate of a solar cell and a second conductive region of a second conductivity type disposed above the first conductive region. The bypass diode can include a thin dielectric region disposed directly between the first and second conductive regions.Type: GrantFiled: July 1, 2020Date of Patent: April 23, 2024Assignee: Maxeon Solar Pte. Ltd.Inventors: Seung Bum Rim, David D. Smith
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Patent number: 11908958Abstract: Methods of fabricating a solar cell including metallization techniques and resulting solar cells, are described. In an example, forming a first semiconductor region and a second semiconductor region on the back side of a substrate. A first conductive busbar can be formed above the first semiconductor region. A first portion of a second conductive busbar can be formed above the second semiconductor region. A second portion of the second conductive busbar can be formed above the second semiconductor region, where a separation region separates the second portion and the first portion of the second conductive busbar. A third conductive busbar can be formed above the first semiconductor region. A first conductive bridge can be formed above the separation region, where the first conductive bridge electrically connects the first conductive busbar to the third conductive busbar.Type: GrantFiled: December 30, 2016Date of Patent: February 20, 2024Inventors: Matthieu Minault Reich, Seung Bum Rim
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Publication number: 20240030864Abstract: A photovoltaic module can include a high voltage photovoltaic laminate that include a plurality of high voltage photovoltaic cells with each of the high voltage photovoltaic cells including a plurality of sub-cells. A boost-less conversion device can be configured to convert a first voltage from the high voltage photovoltaic laminate to a second voltage.Type: ApplicationFiled: September 29, 2023Publication date: January 25, 2024Inventors: GOPAL KRISHAN GARG, SEUNG BUM RIM, PETER JOHN COUSINS
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Patent number: 11869992Abstract: A solar cell can include a built-in bypass diode. In one embodiment, the solar cell can include an active region disposed in or above a first portion of a substrate and a bypass diode disposed in or above a second portion of the substrate. The first and second portions of the substrate can be physically separated with a groove. A metallization structure can couple the active region to the bypass diode.Type: GrantFiled: October 21, 2022Date of Patent: January 9, 2024Assignee: Maxeon Solar Pte. Ltd.Inventors: Seung Bum Rim, Gabriel Harley
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Publication number: 20230420582Abstract: Methods of fabricating conductive contacts for polycrystalline silicon features of solar cells, and the resulting solar cells, are described. In an example, a method of fabricating a solar cell includes providing a substrate having a polycrystalline silicon feature. The method also includes forming a conductive paste directly on the polycrystalline silicon feature. The method also includes firing the conductive paste at a temperature above approximately 700 degrees Celsius to form a conductive contact for the polycrystalline silicon feature. The method also includes, subsequent to firing the conductive paste, forming an anti-reflective coating (ARC) layer on the polycrystalline silicon feature and the conductive contact. The method also includes forming a conductive structure in an opening through the ARC layer and electrically contacting the conductive contact.Type: ApplicationFiled: September 8, 2023Publication date: December 28, 2023Inventor: Seung Bum Rim
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Publication number: 20230378378Abstract: Methods of fabricating a solar cell including metallization techniques and resulting solar cells, are described. In an example, forming a first semiconductor region and a second semiconductor region on the back side of a substrate. A first conductive busbar can be formed above the first semiconductor region. A first portion of a second conductive busbar can be formed above the second semiconductor region. A second portion of the second conductive busbar can be formed above the second semiconductor region, where a separation region separates the second portion and the first portion of the second conductive busbar. A third conductive busbar can be formed above the first semiconductor region. A first conductive bridge can be formed above the separation region, where the first conductive bridge electrically connects the first conductive busbar to the third conductive busbar.Type: ApplicationFiled: August 4, 2023Publication date: November 23, 2023Inventors: Matthieu Reich, SEUNG BUM RIM
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Patent number: 11824130Abstract: Methods of fabricating solar cells having a plurality of sub-cells coupled by cell level interconnection, and the resulting solar cells, are described herein. In an example, a solar cell includes a plurality of sub-cells. Each of the plurality of sub-cells includes a singulated and physically separated semiconductor substrate portion. Each of the plurality of sub-cells includes an on-sub-cell metallization structure interconnecting emitter regions of the sub-cell. An inter-sub-cell metallization structure couples adjacent ones of the plurality of sub-cells. The inter-sub-cell metallization structure is different in composition from the on-sub-cell metallization structure.Type: GrantFiled: October 14, 2022Date of Patent: November 21, 2023Assignee: Maxeon Solar Pte. Ltd.Inventors: Seung Bum Rim, Hung-Ming Wang, David Okawa, Lewis Abra
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Patent number: 11811360Abstract: A photovoltaic module can include a high voltage photovoltaic laminate that include a plurality of high voltage photovoltaic cells with each of the high voltage photovoltaic cells including a plurality of sub-cells. A boost-less conversion device can be configured to convert a first voltage from the high voltage photovoltaic laminate to a second voltage.Type: GrantFiled: March 28, 2014Date of Patent: November 7, 2023Assignee: Maxeon Solar Pte. Ltd.Inventors: Gopal Krishan Garg, Seung Bum Rim, Peter John Cousins
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Patent number: 11804558Abstract: Methods of fabricating conductive contacts for polycrystalline silicon features of solar cells, and the resulting solar cells, are described. In an example, a method of fabricating a solar cell includes providing a substrate having a polycrystalline silicon feature. The method also includes forming a conductive paste directly on the polycrystalline silicon feature. The method also includes firing the conductive paste at a temperature above approximately 700 degrees Celsius to form a conductive contact for the polycrystalline silicon feature. The method also includes, subsequent to firing the conductive paste, forming an anti-reflective coating (ARC) layer on the polycrystalline silicon feature and the conductive contact. The method also includes forming a conductive structure in an opening through the ARC layer and electrically contacting the conductive contact.Type: GrantFiled: December 29, 2017Date of Patent: October 31, 2023Assignee: Maxeon Solar Pte. Ltd.Inventor: Seung Bum Rim
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Publication number: 20230238471Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.Type: ApplicationFiled: March 24, 2023Publication date: July 27, 2023Inventors: Peter J. Cousins, David D. Smith, Seung Bum Rim
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Publication number: 20230155039Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a solar cell can include a substrate having a light-receiving surface and a back surface. A first doped region of a first conductivity type, wherein the first doped region is disposed in a first portion of the back surface. A first thin dielectric layer disposed over the back surface of the substrate, where a portion of the first thin dielectric layer is disposed over the first doped region of the first conductivity type. A first semiconductor layer disposed over the first thin dielectric layer. A second doped region of a second conductivity type in the first semiconductor layer, where the second doped region is disposed over a second portion of the back surface. A first conductive contact disposed over the first doped region and a second conductive contact disposed over the second doped region.Type: ApplicationFiled: January 20, 2023Publication date: May 18, 2023Inventors: SEUNG BUM RIM, MICHAEL C. JOHNSON
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Patent number: 11637213Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.Type: GrantFiled: August 3, 2020Date of Patent: April 25, 2023Assignee: Maxeon Solar Pte. Ltd.Inventors: Peter J. Cousins, David D. Smith, Seung Bum Rim
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Patent number: 11594648Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a solar cell can include a substrate having a light-receiving surface and a back surface. A first doped region of a first conductivity type, wherein the first doped region is disposed in a first portion of the back surface. A first thin dielectric layer disposed over the back surface of the substrate, where a portion of the first thin dielectric layer is disposed over the first doped region of the first conductivity type. A first semiconductor layer disposed over the first thin dielectric layer. A second doped region of a second conductivity type in the first semiconductor layer, where the second doped region is disposed over a second portion of the back surface. A first conductive contact disposed over the first doped region and a second conductive contact disposed over the second doped region.Type: GrantFiled: April 20, 2020Date of Patent: February 28, 2023Assignee: SunPower CorporationInventors: Seung Bum Rim, Michael C. Johnson
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Publication number: 20230038148Abstract: A solar cell can include a built-in bypass diode. In one embodiment, the solar cell can include an active region disposed in or above a first portion of a substrate and a bypass diode disposed in or above a second portion of the substrate. The first and second portions of the substrate can be physically separated with a groove. A metallization structure can couple the active region to the bypass diode.Type: ApplicationFiled: October 21, 2022Publication date: February 9, 2023Inventors: Seung Bum Rim, Gabriel Harley
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Publication number: 20230033252Abstract: Methods of fabricating solar cells having a plurality of sub-cells coupled by cell level interconnection, and the resulting solar cells, are described herein. In an example, a solar cell includes a plurality of sub-cells. Each of the plurality of sub-cells includes a singulated and physically separated semiconductor substrate portion. Each of the plurality of sub-cells includes an on-sub-cell metallization structure interconnecting emitter regions of the sub-cell. An inter-sub-cell metallization structure couples adjacent ones of the plurality of sub-cells. The inter-sub-cell metallization structure is different in composition from the on-sub-cell metallization structure.Type: ApplicationFiled: October 14, 2022Publication date: February 2, 2023Inventors: Seung Bum Rim, Hung-Ming Wang, David Okawa, Lewis Abra
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Patent number: 11508860Abstract: A solar cell can include a built-in bypass diode. In one embodiment, the solar cell can include an active region disposed in or above a first portion of a substrate and a bypass diode disposed in or above a second portion of the substrate. The first and second portions of the substrate can be physically separated with a groove. A metallization structure can couple the active region to the bypass diode.Type: GrantFiled: May 22, 2020Date of Patent: November 22, 2022Assignee: SunPower CorporationInventors: Seung Bum Rim, Gabriel Harley
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Patent number: 11502213Abstract: Methods of fabricating solar cells having a plurality of sub-cells coupled by cell level interconnection, and the resulting solar cells, are described herein. In an example, a solar cell includes a plurality of sub-cells. Each of the plurality of sub-cells includes a singulated and physically separated semiconductor substrate portion. Each of the plurality of sub-cells includes an on-sub-cell metallization structure interconnecting emitter regions of the sub-cell. An inter-sub-cell metallization structure couples adjacent ones of the plurality of sub-cells. The inter-sub-cell metallization structure is different in composition from the on-sub-cell metallization structure.Type: GrantFiled: December 30, 2016Date of Patent: November 15, 2022Assignee: SunPower CorporationInventors: Seung Bum Rim, Hung-Ming Wang, David Okawa, Lewis Abra
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Patent number: 11502208Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.Type: GrantFiled: November 8, 2019Date of Patent: November 15, 2022Assignee: SunPower CorporationInventors: Seung Bum Rim, David D. Smith, Taiqing Qiu, Staffan Westerberg, Kieran Mark Tracy, Venkatasubramani Balu
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Publication number: 20220293801Abstract: Methods of fabricating solar cells using UV-curing of light-receiving surfaces of the solar cells, and the resulting solar cells, are described herein. In an example, a method of fabricating a solar cell includes forming a passivating dielectric layer on a light-receiving surface of a silicon substrate. The method also includes forming an anti-reflective coating (ARC) layer below the passivating dielectric layer. The method also includes exposing the ARC layer to ultra-violet (UV) radiation. The method also includes, subsequent to exposing the ARC layer to ultra-violet (UV) radiation, thermally annealing the ARC layer.Type: ApplicationFiled: May 31, 2022Publication date: September 15, 2022Inventors: Yu-Chen Shen, Perine Jaffrennou, Gilles Olav Tanguy Sylvain Poulain, Michael C. Johnson, Seung Bum Rim