SEMICONDUCTOR MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A semiconductor memory structure and a method of manufacturing a semiconductor memory structure are provided. The semiconductor memory structure includes alternatively arranged stacking portions and cell regions. Each cell region includes two ferroelectric layers formed along the adjacent stacking portions; and at least one central portion disposed between the ferroelectric layers and includes a first conductive structure and a second conductive structure separated by a channel isolation structure as well as two semiconductor layers formed along the ferroelectric layers. The first conductive structure includes a contact portion and an extension portion. The contact portion is disposed between the semiconductor layers. The extension portion extends from the contact portion to the channel isolation structure and is separated from the semiconductor layers through dielectric layers.
This application is a divisional application of U.S. patent application Ser. No. 17/141,915 filed on Jan. 5, 2021, entitled of “SEMICONDUCTOR MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME”; this application is incorporated herein by reference in their entireties.
BACKGROUNDMany modern-day electronic devices include non-volatile memory. Non-volatile memory is electronic memory that is able to store data in the absence of power. A promising candidate for the next generation of non-volatile memory is ferroelectric random-access memory (FeRAM). FeRAM has a relatively simple structure and is compatible with complementary metal-oxide-semiconductor (CMOS) logic fabrication processes.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying Figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 100 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As used herein, the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, but these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.
Many modern day electronic devices contain electronic memory configured to store data. Electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data when power is on, while non-volatile memory (NVM) is able to store data when power is off. For example, ferroelectric random-access memory (FeRAM) devices are one promising candidate for a next generation NVM technology. This is because FeRAM devices provide many advantages, including fast write time, high endurance, low power consumption, and low susceptibility to damage from radiation. NVM technology uses memory cells that are located within a back-end-of-the-line (BEOL) of an integrated chip (e.g., located between metal interconnect layers overlying a semiconductor substrate). The memory cells are stacked into multiple layers to create a three-dimensional (3D) structure.
For the FeRAM, an electric field is required to switch the polarization between positive and negative voltages to store information. In some embodiments, a source line (SL) and a bit line (BL) are formed on a channel stack in one memory cell. The channel stack comprises a word line (WL), a ferroelectric layer and a channel layer and the SL and BL are formed on the channel layer. To retain low resistance, the contact area (so called “channel lens”) between the SL and the channel layer as well as the contact area between the BL and the channel layer are small, so the SL and BL are usually formed on the channel layer symmetrically and separated from each other with a considerable distance. The polarization may not be switched unless a sufficiently large field (voltage) is applied at the word line. For example, a negative polarization (due to most negative voltage drop in the channel layer) may not be switched back to a positive polarization.
The present disclosure relates to a design of 3D non-volatile memory structures for enhancing the switching performance and read speed. In some embodiments, the provided structure can be applied to FeRAM and extendable to other memories such as flash, resistive random access memory (RRAM), magnetic random access memory (MRAM) with decent process and structure modifications. Accordingly, a stable type of 3D stackable nonvolatile memory devices can be formed, so that the device property can be enhanced.
In some embodiments, as shown in
In some embodiments, the stacking portion 210 can be formed on the substrate 101 and includes a plurality of insulating layers 211 and a plurality of first conductive layers 212 stacking along a first direction D1. Further, the insulating layers 211 and the first conductive layers 212 are alternately arranged and are configured in a staircase structure (as shown in
In some embodiments, each first conductive layer 212 may be divided to two sublayers by glue layers 213. Each glue layer 213 partially surrounds one sublayer so as to not only separate two adjacent sublayers from each other, but also separate the first conductive layer 212 from the adjacent insulating layers 211. Each glue layer 213 may have a U shape, V shape, W shape and so on, but the disclosure is not limited thereto. In some embodiments, the glue layer 213 may include oxides, such as Al2O3. The glue layer 213 can be used to improve adhesion of the metal portion in the stacking portion 210.
Each cell region 220 in the cell array region 200 can be formed over the substrate 101 and extend along a second direction D2 and can be sandwiched by the stacking portions 210, so that the cell regions 220 and the stacking portions 210 are alternately arranged along a third direction D3. In some embodiments, each cell region 220 comprises a plurality of unit cells A. In some embodiments, each cell region 220 comprises at least one central portion 221 extending through the cell array region 200 along the first direction D1, cell isolation structures 222 separating two or more central portions 221 from each other, and at least one ferroelectric layer 223 formed along sidewalls of the cell region 220 and besides the stacking portion 210.
In some embodiments, the central portion 221 comprises a first conductive structure 224, a second conductive structure 225, a channel isolation structure 226 separating the first conductive structure 224 from the second conductive structure 225, and two semiconductor layers 227 formed along the ferroelectric layers 223, so that the first conductive structure 224, the second conductive structure 225 and the channel isolation structure 226 are separated from the ferroelectric layers 223 through the semiconductor layer 227.
In some embodiments, the first conductive structure 224 and the second conductive structure 225 independently penetrate through the cell array region 200 along the first direction D1 to contact the substrate 101. The first conductive structure 224 and the second conductive structure 225 are formed in a column shape, e.g., flat column or rectangular column shape, extending in the cell array region 200 along the first direction D1. In some embodiments, the first conductive structure 224 corresponds to source lines and the second conductive structure 225 corresponds to bit lines. In some embodiments, the first conductive structure 224 corresponds to bit lines and the second conductive structure 225 corresponds to source lines. In some embodiments, the bit lines and the source lines can independently include various conductive materials, e.g., metal such as aluminum (Al), titanium (Ti), cobalt (Co), silver (Ag), gold (Au), copper (Cu), nickel (Ni), chromium (Cr), hafnium (Hf), rhodium (Ru), tungsten (W), platinum (Pt) and/or alloys thereof, or a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or the like, but the disclosure is not limited thereto.
In some embodiments, the first conductive structures 224 correspond to source lines and the second conductive structures 225 correspond to bit lines. The first conductive structure 224 presents a T-shape from the top view and comprises a contact portion 2241 and an extension portion 2242 as shown in
From the top view of the first conductive structure 224 as shown in
An asymmetric structure can be obtained by the extension of first conductive structure 224 (i.e. the source line). In some embodiments, a contact area between the first conductive structure 224 and the semiconductor layer 227 is similar to a contact area between the second conductive structure and the semiconductor layer 227; therefore the asymmetric first conductive structure 224 renders less impact to electrical resistances of the source line and the bit line and the read speed. Further, the extension portion 2242 helps to enhance electric field, and thus, switching speed can be accelerated.
The channel isolation structure 226 may be disposed between the semiconductor layers 227 and electrically isolates the first conductive structure 224 and the second conductive structure 225. From the top view as shown in
In some embodiments, the semiconductor layers 227 may include a semiconductor material. In some embodiments, the semiconductor layers 227 may include various materials, such as an amorphous silicon (a-Si) material, a polycrystalline silicon (poly-Si) material, an oxide semiconductor material (e.g., indium zinc oxide (IZO), indium-gallium-zinc oxide (IGZO), indium tungsten oxide (IWO), indium tin oxide (ITO), zinc oxide (ZnO), stannous oxide (SnO), and copper oxide (CuO)), or the like, but the disclosure is not limited to the above-mentioned materials. In some embodiments, the semiconductor layers 227 may serve as channel. From the cross-sectional side view as shown in
The cell isolation structures 222 separate the central portions 221 from each other when there are two or more central portions 221 in one cell region 220. In some embodiments, the cell isolation structures 222 are arranged in an array configuration or a staggered array configuration. In some embodiments, the cell isolation structures 222 penetrate through the cell array region 200 and contact the substrate 101. In some embodiments, the cell isolation structures 222 may include dielectric materials, including oxides, nitrides and the like, such as silicon oxide, silicon nitride, SiCN, Al2O3, HfO2, SiON, and La2O3, but the disclosure is not limited to the above-mentioned materials.
The ferroelectric layer 223 can be formed besides the stacking portion 210 and thus can be sandwiched by the stacking portion 210 and the central portion 221 and also sandwiched by the stacking portion 210 and the cell isolation structures 222. In some embodiments, the ferroelectric layer 223 penetrates through the cell array region 200 along the first direction D1 and is in contact with the substrate 101. As mentioned above, the first conductive layers 212 may correspond to word lines. In some embodiments, the ferroelectric layers 223 are disposed between the first conductive layer 212 (i.e. word line) and the first conductive structure 224 (i.e. source line) or between the first conductive layer 212 (i.e. word line) and the second conductive structure 225 (i.e. bit line). In some embodiments, the first conductive layers 212 (i.e. word lines) can control the adjacent unit cell A in the same level as shown in
With reference to
Method 400 begins at operation 401 by forming a stack 210a of alternating insulating layers 211 and first sacrificial layers 214 over a substrate 101, as shown in
Referring to
Referring to
At operation 402 with reference to
At operation 403, the first sacrificial layers 214 can be replaced by metal to form first conductive layers 212 (i.e. word lines). As shown in
With further reference to
In some embodiments, before forming the first conductive layers 212 in the first recesses 511, glue layers 213 may be formed along the sidewall of the first recesses 511, so that the shape of glue layers 213 corresponds to the sidewall of the first recesses 511. For example, each glue layer 213 may have a U shape, V shape, W shape and so on, depending on the shape of the sidewalls of the recesses 511, but the disclosure is not limited thereto. The glue layers 213 may be formed by using ALD, CVD, physical vapor deposition (PVD) or other methods. Each glue layer 213 partially surrounds the corresponding first conductive layer 212, so that the first conductive layer 212 can be exposed from the first trench 510 but not contact the adjacent insulating layers 211 and/or dielectric structure 310. The glue layer 213 can improve adhesion of the first conductive layer 212 with adjacent insulating layers 211 and/or dielectric structure 310.
Operation 404 includes filling each of the first trenches 510 with a multi-layered structure. The multi-layered structure can be formed by any suitable methods that are known in the art. In some embodiments, referring to
In some embodiments, with reference to
Referring to
Operations 402 to 404 may be performed twice or more times.
At operation 405, with reference to
At operation 406, with reference to
Referring to
At operation 407, with reference to
In some embodiments, a method of manufacturing a semiconductor memory structure comprises: forming a stack of alternating insulating layers and sacrificial layers over a substrate; forming a plurality of trenches in the stack; replacing the sacrificial layers with first conductive layers; filling each of the plurality of trenches with a multi-layered structure including a ferroelectric layer, a semiconductor layer, and a dielectric layer; removing portions of the multi-layered structure to leave remaining portions, so that the remaining portion is disposed between two semiconductor layers of two adjacent multi-layered structures of the multi-layered structures and comprises two dielectric layers formed separately along the two semiconductor layers; forming cell isolation structures between the ferroelectric layers of each two adjacent multi-layered structures of the multi-layered structures and forming channel isolation structures between the semiconductor layers of each two adjacent multi-layered structures of the multi-layered structures; and forming first conductive structures and second conductive structures, wherein each of the first conductive structures is disposed between one of the cell isolation structures and an adjacent channel isolation structure of the channel isolation structures, and each of the second conductive structures is disposed between one of the cell isolation structures and the other adjacent channel isolation structure of the channel isolation structures, wherein the first conductive structures partially contact the semiconductor layers and partially contact the dielectric layers.
In some embodiments, a method of manufacturing a semiconductor memory structure comprises: forming a stack of alternating insulating layers and sacrificial layers over a substrate; forming a plurality of first trenches in the stack; replacing the sacrificial layers with conductive layers; sequentially depositing a ferroelectric layer, a semiconductor layer and a dielectric layer along sidewalls and a bottom of each of the plurality of first trenches; removing portions of the dielectric layer, portions of the semiconductor layer and portions of the ferroelectric layer to expose the substrate from the plurality of first trenches; filling the plurality of first trenches with a first sacrificial material; forming a plurality of second trenches in the stack, wherein the plurality of second trenches and the plurality of first trench are arranged alternately; sequentially depositing a ferroelectric layer, a semiconductor layer and a dielectric layer along sidewalls and a bottom of each of the plurality of second trenches; removing portions of the dielectric layer, portions of the semiconductor layer and portions of the ferroelectric layer to expose the substrate from the second trench; filling each of the plurality of second trench with a second sacrificial material; removing portions of the first sacrificial material, portions of the second sacrificial material, and portions of the dielectric layer to form a plurality of third trenches and a plurality of remaining portions, wherein the plurality of third trenches and the plurality of remaining portions are arranged alternately, and wherein the each of the plurality of remaining portion is disposed between two semiconductor layers and comprises the dielectric layers formed separately along the two semiconductor layers; filling the plurality of third trenches with a third sacrificial material; removing portions of the third sacrificial material to form a plurality of channel isolation trenches so that one side of each of the plurality of remaining portions and the two semiconductor layers are exposed from the plurality of channel isolation trenches; filling the plurality of channel isolation trenches with isolation materials to form channel isolation structures; removing portions of the third sacrificial materials and the semiconductor layers to form cell isolation trenches so that the third sacrificial materials is divided into two parts, wherein one part of the third sacrificial materials next to the remaining portion is replaced with conductive materials to form a contact portion, and the other part of the third sacrificial materials next to the channel isolation structure is replaced with conductive materials to form a conductive structure; filling the cell isolation trenches with isolation materials to form cell isolation structure; and replacing the first and second sacrificial materials in the remaining portions with conductive materials to form an extension portion.
In some embodiments, a method of manufacturing a semiconductor memory structure comprises: forming a stack of alternating insulating layers and conductive layers over a substrate, wherein the stack has a plurality of first trenches; filling each of the plurality of first trenches with a multi-layered structure including a ferroelectric layer, a semiconductor layer, a dielectric layer, and first sacrificial materials; removing portions of the multi-layered structure to form a plurality of second trenches and a plurality of remaining portions, wherein the remaining portion is disposed between two semiconductor layers of two adjacent multi-layered structures of the multi-layered structures and comprises two dielectric layers formed separately along the two semiconductor layers; filling the plurality of second trenches with second sacrificial materials; forming cell isolation structures and channel isolation structures by removing portions of the second sacrificial materials, wherein the cell isolation structures are positioned between the ferroelectric layers of each two adjacent multi-layered structures of the multi-layered structures and the channel isolation structures are positioned between the semiconductor layers of each two adjacent multi-layered structures of the multi-layered structures; forming first conductive structures and second conductive structures by replacing the second sacrificial materials in the remaining portions and in the plurality of second trenches with conductive materials, wherein each of the first conductive structures is disposed between one of the cell isolation structures and an adjacent channel isolation structure of the channel isolation structures, and each of the second conductive structures is disposed between one of the cell isolation structures and the other adjacent channel isolation structure of the channel isolation structures.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A method of manufacturing a semiconductor memory structure, the method comprising:
- forming a stack of alternating insulating layers and sacrificial layers over a substrate;
- forming a plurality of trenches in the stack;
- replacing the sacrificial layers with first conductive layers;
- filling each of the plurality of trenches with a multi-layered structure including a ferroelectric layer, a semiconductor layer, and a dielectric layer;
- removing portions of the multi-layered structure to leave remaining portions, so that the remaining portion is disposed between two semiconductor layers of two adjacent multi-layered structures of the multi-layered structures and comprises two dielectric layers formed separately along the two semiconductor layers;
- forming cell isolation structures between the ferroelectric layers of each two adjacent multi-layered structures of the multi-layered structures and forming channel isolation structures between the semiconductor layers of each two adjacent multi-layered structures of the multi-layered structures; and
- forming first conductive structures and second conductive structures, wherein each of the first conductive structures is disposed between one of the cell isolation structures and an adjacent channel isolation structure of the channel isolation structures, and each of the second conductive structures is disposed between one of the cell isolation structures and the other adjacent channel isolation structure of the channel isolation structures,
- wherein the first conductive structures partially contact the semiconductor layers and partially contact the dielectric layers.
2. The method of claim 1, wherein replacing the sacrificial layers with first conductive layers comprises:
- replacing materials disposed between the dielectric layers in the remaining portions with conductive materials to form extension portions of the first conductive structures; and
- replacing materials disposed between the remaining portions and the cell isolation structures with the conductive materials to form contact portions, wherein the extension portion extends from one of the contact portion to one of the channel isolation structures and is separated from the semiconductor layers through the dielectric layers.
3. The method of claim 1, wherein each of the contact portions of the first conductive structures has a contact area contacting the semiconductor layers, each of the second conductive structures has a contact area contacting the semiconductor layers, and the contact area of the contact portion of the first conductive structure and the contact area of the second conductive structure are similar.
4. The method of claim 1, wherein after the remaining portions are formed, portions of the ferroelectric layer and portions of the semiconductor layer are removed from bottoms of the plurality of trenches to expose the substrate from the plurality of trenches.
5. The method of claim 4, wherein both of ferroelectric layer and semiconductor layer have an L-shaped vertical cross section formed along sidewalls of the plurality of trenches and partially covering the bottoms of the plurality of trenches whereby the substrate exposes from the plurality of trenches.
6. The method of claim 1, wherein replacing the sacrificial layers with first conductive layers through the plurality of trenches further comprises:
- forming a plurality first recesses by partially removing the sacrificial layers; and
- forming glue layers along sidewalls of the plurality first recesses before forming the first conductive layers.
7. The method of claim 6, wherein the glue layers comprise oxides.
8. A method of manufacturing a semiconductor memory structure, the method comprising:
- forming a stack of alternating insulating layers and sacrificial layers over a substrate;
- forming a plurality of first trenches in the stack;
- replacing the sacrificial layers with conductive layers;
- sequentially depositing a ferroelectric layer, a semiconductor layer and a dielectric layer along sidewalls and a bottom of each of the plurality of first trenches;
- removing portions of the dielectric layer, portions of the semiconductor layer and portions of the ferroelectric layer to expose the substrate from the plurality of first trenches;
- filling the plurality of first trenches with a first sacrificial material;
- forming a plurality of second trenches in the stack, wherein the plurality of second trenches and the plurality of first trench are arranged alternately;
- sequentially depositing a ferroelectric layer, a semiconductor layer and a dielectric layer along sidewalls and a bottom of each of the plurality of second trenches;
- removing portions of the dielectric layer, portions of the semiconductor layer and portions of the ferroelectric layer to expose the substrate from the second trench; filling each of the plurality of second trench with a second sacrificial material; removing portions of the first sacrificial material, portions of the second sacrificial material, and portions of the dielectric layer to form a plurality of third trenches and a plurality of remaining portions, wherein the plurality of third trenches and the plurality of remaining portions are arranged alternately, and wherein the each of the plurality of remaining portion is disposed between two semiconductor layers and comprises the dielectric layers formed separately along the two semiconductor layers;
- filling the plurality of third trenches with a third sacrificial material;
- removing portions of the third sacrificial material to form a plurality of channel isolation trenches so that one side of each of the plurality of remaining portions and the two semiconductor layers are exposed from the plurality of channel isolation trenches;
- filling the plurality of channel isolation trenches with isolation materials to form channel isolation structures;
- removing portions of the third sacrificial materials and the semiconductor layers to form cell isolation trenches so that the third sacrificial materials is divided into two parts, wherein one part of the third sacrificial materials next to the remaining portion is replaced with conductive materials to form a contact portion, and the other part of the third sacrificial materials next to the channel isolation structure is replaced with conductive materials to form a conductive structure;
- filling the cell isolation trenches with isolation materials to form cell isolation structure; and
- replacing the first and second sacrificial materials in the remaining portions with conductive materials to form an extension portion.
9. The method of claim 8, wherein the extension portion extends from the contact portion to the channel isolation structure and is separated from the two semiconductor layers through the dielectric layers.
10. The method of claim 9, wherein the channel isolation structure has a length equal to or less than a length of the extension portion.
11. The method of claim 9, wherein the contact portion has a contact area contacting the two semiconductor layers, the second conductive structure has a contact area contacting the two semiconductor layers, and the contact area of the contact portion and the contact area of the conductive structure are similar.
12. The method of claim 9, wherein the extension portion has a length from the contact portion to the channel isolation structure, which is 10% to 90% of a length of each of the two semiconductor layers.
13. The method of claim 9, wherein the contact portion and the extension portion present a T-shape top view.
14. The method of claim 8, wherein each of the ferroelectric layers has an L-shaped vertical cross section.
15. The method of claim 8, wherein each of the two semiconductor layers has an L-shaped vertical cross section.
16. A method of manufacturing a semiconductor memory structure, the method comprising:
- forming a stack of alternating insulating layers and conductive layers over a substrate, wherein the stack has a plurality of first trenches;
- filling each of the plurality of first trenches with a multi-layered structure including a ferroelectric layer, a semiconductor layer, a dielectric layer, and first sacrificial materials;
- removing portions of the multi-layered structure to form a plurality of second trenches and a plurality of remaining portions, wherein the remaining portion is disposed between two semiconductor layers of two adjacent multi-layered structures of the multi-layered structures and comprises two dielectric layers formed separately along the two semiconductor layers;
- filling the plurality of second trenches with second sacrificial materials;
- forming cell isolation structures and channel isolation structures by removing portions of the second sacrificial materials, wherein the cell isolation structures are positioned between the ferroelectric layers of each two adjacent multi-layered structures of the multi-layered structures and the channel isolation structures are positioned between the semiconductor layers of each two adjacent multi-layered structures of the multi-layered structures;
- forming first conductive structures and second conductive structures by replacing the second sacrificial materials in the remaining portions and in the plurality of second trenches with conductive materials, wherein each of the first conductive structures is disposed between one of the cell isolation structures and an adjacent channel isolation structure of the channel isolation structures, and each of the second conductive structures is disposed between one of the cell isolation structures and the other adjacent channel isolation structure of the channel isolation structures.
17. The method of claim 16, wherein forming the first conductive structures comprises:
- replacing the second sacrificial materials disposed between the dielectric layers in the remaining portions with conductive materials to form extension portions of the first conductive structures; and
- replacing the second sacrificial materials disposed between the remaining portions and the cell isolation structures with the conductive materials to form contact portions, wherein the extension portion extends from one of the contact portion to one of the channel isolation structures and is separated from the semiconductor layers through the dielectric layers.
18. The method of claim 17, wherein the channel isolation structure has a length equal to or less than a length of the extension portion; and the extension portion has a length from the contact portion to the channel isolation structure, which is 10% to 90% of a length of each of the two semiconductor layers.
19. The method of claim 16, wherein each of the conductive layer comprises two sublayers and a glue layer; and the glue layer is disposed between the conductive layer and an adjacent insulating layer of the insulating layers.
20. The method of claim 19, wherein the glue layer comprises oxides.
Type: Application
Filed: May 5, 2023
Publication Date: Aug 31, 2023
Inventors: MENG-HAN LIN (HSINCHU), CHIA-EN HUANG (HSINCHU COUNTY)
Application Number: 18/312,766