METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Abstract

A method of manufacturing a semiconductor device is provided. The method of manufacturing a semiconductor device includes forming a first electrode layer on a substrate, and then forming a stack structure on the first electrode layer, wherein the stack structure comprises a first insulating layer, a gate electrode layer, and a second insulating layer. An opening is formed in the stack structure. A gate dielectric layer is formed on a sidewall of the opening of the stack structure, and an oxide semiconductor layer is formed in the opening, wherein the gate dielectric layer is sandwiched between the oxide semiconductor layer and the gate electrode layer. A second electrode layer is then formed on the stack structure to be in direct contact with the oxide semiconductor layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of and claims the priority benefit of U.S. patent application Ser. No. 17/386,565, filed on Jul. 28, 2021, now allowed. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Technical Field

The invention relates to a semiconductor manufacture technique, and particularly relates to a semiconductor device and a method of manufacturing the same.

Description of Related Art

The semiconductor device such as transistor has been developed for a long time. The transistor includes plane device and vertical device. The plane device is, for example, a thin film transistor, wherein a source electrode and a drain electrode are over a gate electrode, and the channel length (Lg) is defined by the spacing between the source electrode and the drain electrode. However, the channel length is desired to be smaller with the miniaturization of the device size, and thus the Lg of the plane device can not meet the requirement due to the resolution limitation of photolithography.

The vertical device is, for example, a 3D transistor, wherein a vertical channel formed on the substrate, a source electrode and a drain electrode are disposed at two ends of the vertical channel, and the Lg of the vertical device is defined by the thickness of a gate electrode. Therefore, the Lg of vertical device can be made smaller. However, the process of the vertical device is more complicated than the plane device, and it is difficult in the formation and the contact for drain/source/body.

SUMMARY

The invention provides a method of manufacturing a semiconductor device to obtain the semiconductor device having fine channel length.

The method of manufacturing a semiconductor device of one embodiment of the invention includes forming a first electrode layer on a substrate, and then forming a stack structure on the first electrode layer, wherein the stack structure comprises a first insulating layer, a gate electrode layer, and a second insulating layer. An opening is formed in the stack structure. A gate dielectric layer is formed on a sidewall of the opening of the stack structure, and an oxide semiconductor layer is formed in the opening, wherein the gate dielectric layer is sandwiched between the oxide semiconductor layer and the gate electrode layer. A second electrode layer is then formed on the stack structure to be in direct contact with the oxide semiconductor layer.

In one embodiment of the invention, after the step of forming the second electrode layer, the method further comprises patterning the second insulating layer and the gate electrode layer.

In one embodiment of the invention, after the step of forming the second electrode layer, the method further comprises respectively forming electrode contacts connecting to the first electrode layer, the gate electrode layer, and the second electrode layer.

In one embodiment of the invention, the step of forming the gate dielectric layer comprises conformally depositing a dielectric material layer on the stack structure and in the opening, and then etching back the dielectric material layer until the first electrode layer is exposed.

In one embodiment of the invention, the step of forming the stack structure comprises depositing the first insulating layer on the first electrode layer, depositing the gate electrode layer on the first insulating layer, and depositing the second insulating layer on the gate electrode layer.

In one embodiment of the invention, the step of forming the oxide semiconductor layer in the opening comprises blanket depositing an oxide semiconductor material to fill the opening, and then etching back the oxide semiconductor material until the stack structure is exposed.

In one embodiment of the invention, a method of forming the oxide semiconductor layer in the opening comprises a selective deposition process.

In one embodiment of the invention, a material of the oxide semiconductor layer comprises indium-gallium-zinc oxide.

In one embodiment of the invention, the substrate comprises a silicon-on-insulator (SOI) substrate.

Based on the above, since the invention provides a semiconductor device having a planar stack structure containing two source/drain electrodes, a gate electrode layer therebetween, and an oxide semiconductor penetrating through the gate electrode layer, it can realize fine channel length in the semiconductor device by simple process.

To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the invention.

FIG. 2 is a cross-sectional view along line II-IF of FIG. 1.

FIG. 3 is a schematic plan view of a semiconductor device according to a second embodiment of the invention.

FIG. 4 is a cross-sectional view along line IV-IV′ of FIG. 3.

FIG. 5A to FIG. 5I are schematic cross-sectional views of a manufacturing process of a semiconductor device according to a third embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

Referring to the embodiments below and the accompanied drawings for a sufficient understanding of the invention. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. However, the invention may be implemented in many other different forms and should not be limited to the embodiments described hereinafter. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. In the drawings, for clarity, the elements and relative dimensions thereof may not be scaled. For easy understanding, the same elements in the following embodiments will be denoted by the same reference numerals.

FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the invention. FIG. 2 is a cross-sectional view along line II-IF of FIG. 1.

Referring to FIG. 1 and FIG. 2, the semiconductor device of the first embodiment includes a substrate 100, a first electrode layer 102, a gate electrode layer 104, a second electrode layer 106, an oxide semiconductor layer 108, a gate dielectric layer 110, a first insulating layer 112, and a second insulating layer 114. The first electrode layer 102 is disposed on the substrate 100, the gate electrode layer 104 is disposed on the first electrode layer 102, and the second electrode layer 106 is disposed on the gate electrode layer 104. In one embodiment, the substrate 100 may be a silicon-on-insulator (SOI) substrate or other semiconductor substrate. The gate electrode layer 104 may be made of conductive material such as indium oxide-tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium oxide, zinc oxide, or other suitable material. The first electrode layer 102 and the second electrode layer 106 are as a drain and a source of the semiconductor device. For example, the first electrode layer 102 is a drain electrode and the second electrode layer 106 is a source electrode; alternatively, the first electrode layer 102 is a source electrode and the second electrode layer 106 is a drain electrode. In one embodiment, the first electrode layer 102 and the second electrode layer 106 may be a metal film or a metal nitride film, wherein the material of the metal film is selected from Al, Cr, Cu, Ta, Ti, Mo, and W; the material of the metal nitride film is nitride of foregoing metal such as a titanium nitride film, a molybdenum nitride film, a tungsten nitride film), or the like. The oxide semiconductor layer 108 penetrates through the gate electrode layer 104 and is in direct contact with the first electrode layer 102 and the second electrode layer 106, respectively. A material of the oxide semiconductor layer 108 includes, for example, indium-gallium-zinc oxide (IGZO) or other suitable oxide semiconductor material. The gate dielectric layer 110 is disposed between the gate electrode layer 104 and the oxide semiconductor layer 108, the first insulating layer 112 is disposed between the gate electrode layer 104 and the first electrode layer 102, and the second insulating layer 114 is disposed between the gate electrode layer 104 and the second electrode layer 106.

In the first embodiment, the profile of the cross section of the semiconductor device is step-shaped, and thus it is beneficial to interconnection of the semiconductor device. For example, an electrode contact 116 connects to the first electrode layer 102, an electrode contact 118 connects to the gate electrode layer 104, and an electrode contact 120 connects to the second electrode layer 106. Those electrode contacts 116, 118 and 120 can be formed together using the same steps. However, the invention is not limited thereto.

FIG. 3 is a schematic plan view of a semiconductor device according to a second embodiment of the invention, wherein the reference symbols used in the first embodiment are used to equally represent the same or similar components. FIG. 4 is a cross-sectional view along line IV-IV′ of FIG. 3. The description of the same components can be derived from the first embodiment, and will not be repeated here.

Referring to FIG. 3 and FIG. 4, the semiconductor device of the second embodiment also includes a substrate 100, a first electrode layer 102, a gate electrode layer 104, a second electrode layer 106, an oxide semiconductor layer 108, a gate dielectric layer 110, a first insulating layer 112, and a second insulating layer 114. The difference between the second and the first embodiments is that the shapes of the oxide semiconductor layer 108 and the second electrode layer 106 are circular. In another embodiment, the shapes of the oxide semiconductor layer 108 and the second electrode layer 106 in the FIG. 3 may be rectangle, and so on.

FIG. 5A to FIG. 5I are schematic cross-sectional views of a manufacturing process of a semiconductor device according to a third embodiment of the invention.

Referring to FIG. 5A, a first electrode layer 502 is formed on a substrate 500. The substrate 500 may be a SOI substrate or other semiconductor substrate.

Then, referring to FIG. 5B, a stack structure 504 is formed on the first electrode layer 502, wherein the stack structure 504, for example, includes a first insulating layer 506, a gate electrode layer 508, and a second insulating layer 510. In the embodiment, the step of forming the stack structure 504, for example, includes depositing the first insulating layer 506 on the first electrode layer 502, depositing the gate electrode layer 508 on the first insulating layer 506, and depositing the second insulating layer 510 on the gate electrode layer 508.

Thereafter, referring to FIG. 5C, an opening 512 is formed in the stack structure 504. The opening 512 may be, for example, a rectangle groove or a circular hole. To form a gate dielectric layer on a sidewall 512a of the opening 512, it may conformally depositing a dielectric material layer 514 on the stack structure 504 and in the opening 512 first.

After that, referring to FIG. 5D, the dielectric material layer 514 in FIG. 5C is etched back until the first electrode layer 502 is exposed so as to form the gate dielectric layer 514a. However, the invention is not limited thereto.

Then, referring to FIG. 5E, an oxide semiconductor layer 516 is formed in the opening 512, wherein the gate dielectric layer 514a is sandwiched between the oxide semiconductor layer 516 and the gate electrode layer 508. In one embodiment, the step of forming the oxide semiconductor layer 516 in the opening 512 includes blanket depositing an oxide semiconductor material (not shown) to fill the opening 516, and then etching back the oxide semiconductor material until the stack structure 504 is exposed. In another embodiment, a method of forming the oxide semiconductor layer 516 in the opening 512 includes a selective deposition process. A material of the oxide semiconductor layer 516 includes, for example, IGZO or other suitable oxide semiconductor material.

Thereafter, referring to FIG. 5F, a second electrode layer 518 is formed on the stack structure 504 to be in direct contact with the oxide semiconductor layer 516, wherein the method of forming the second electrode layer 518, for example, includes a deposition process. A semiconductor device of the third embodiment has been manufactured in this step.

After the step shown in FIG. 5F, there are some optional steps as follows.

Please referring to FIG. 5G, the second electrode layer 518 is patterned to expose a portion of the stack structure 504.

Then, referring to FIG. 5H, the second insulating layer 510 and the gate electrode layer 508 are patterned, and thus the profile of the cross section of the structure in FIG. 5H is step-shaped for the interconnection. In another embodiment, the first insulating layer 506 and the first electrode layer 502 can be further patterned to expose a portion of the substrate 500 (e.g. the semiconductor device as shown in FIG. 4).

Thereafter, referring to FIG. 5I, electrode contacts 520a, 520b and 520c are formed to connecting to the first electrode layer 502, the gate electrode layer 508, and the second electrode layer 518, respectively.

In summary, the semiconductor device according to the invention comprises a semiconductor device having a planar stack structure containing two source/drain electrodes, a gate electrode layer therebetween, and an oxide semiconductor perpendicularly penetrating through the gate electrode layer, and thus the channel length (Lg) can be defined by the thickness of the gate electrode layer. In other words, according to the invention, fine channel length of the semiconductor device can be accomplished by simple process.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a first electrode layer on a substrate;

forming a stack structure on the first electrode layer, wherein the stack structure comprises a first insulating layer, a gate electrode layer, and a second insulating layer;

forming an opening in the stack structure;

forming a gate dielectric layer on a sidewall of the opening of the stack structure;

forming an oxide semiconductor layer in the opening, wherein the gate dielectric layer is sandwiched between the oxide semiconductor layer and the gate electrode layer; and

forming a second electrode layer on the stack structure to be in direct contact with the oxide semiconductor layer.

2. The method of claim 1, wherein after the step of forming the second electrode layer further comprises: patterning the second insulating layer and the gate electrode layer.

3. The method of claim 1, wherein after the step of forming the second electrode layer further comprises: forming a plurality of electrode contacts connecting to the first electrode layer, the gate electrode layer, and the second electrode layer respectively.

4. The method of claim 1, wherein the step of forming the gate dielectric layer comprises:

conformally depositing a dielectric material layer on the stack structure and in the opening; and

etching back the dielectric material layer until the first electrode layer is exposed.

5. The method of claim 1, wherein the step of forming the stack structure comprises:

depositing the first insulating layer on the first electrode layer;

depositing the gate electrode layer on the first insulating layer; and

depositing the second insulating layer on the gate electrode layer.

6. The method of claim 1, wherein the step of forming the oxide semiconductor layer in the opening comprises:

blanket depositing an oxide semiconductor material to fill the opening; and

etching back the oxide semiconductor material until the stack structure is exposed.

7. The method of claim 1, wherein a method of forming the oxide semiconductor layer in the opening comprises a selective deposition process.

8. The method of claim 1, wherein a material of the oxide semiconductor layer comprises indium-gallium-zinc oxide.

9. The method of claim 1, wherein the substrate comprises a silicon-on-insulator (SOI) substrate.