Analog Hardware Realization of Neural Networks
Systems and methods are provided for analog hardware realization of neural networks. The method incudes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology into an equivalent analog network of analog components. The method also includes computing a weight matrix for the equivalent analog network based on the weights of the trained neural network. Each element of the weight matrix represents a respective connection between analog components of the equivalent analog network. The method also includes generating a schematic model for implementing the equivalent analog network based on the weight matrix, including selecting component parameter values for the analog components.
This application is a continuation of PCT Application PCT/RU2021/000630, filed Dec. 30, 2021, entitled “Transformations, Optimizations, and Interfaces for Analog Hardware Realization of Neural Networks,” which is incorporated by reference herein in its entirety.
This application is related to U.S. application Ser. No. 17/189,109, filed Mar. 1, 2021, entitled “Analog Hardware Realization of Neural Networks,” which is a continuation of PCT Application PCT/RU2020/000306, filed Jun. 25, 2020, entitled “Analog Hardware Realization of Neural Networks,” each of which is incorporated by reference herein in its entirety. U.S. application Ser. No. 17/189,109 is also a continuation-in-part of PCT Application PCT/EP2020/067800, filed Jun. 25, 2020, entitled “Analog Hardware Realization of Neural Networks,” which is incorporated by reference herein in its entirety.
TECHNICAL FIELDThe disclosed implementations relate generally to neural networks, and more specifically to systems and methods for hardware realization of neural networks.
BACKGROUNDConventional hardware has failed to keep pace with innovation in neural networks and the growing popularity of machine learning based applications. Complexity of neural networks continues to outpace CPU and GPU computational power as digital microprocessor advances are plateauing. Neuromorphic processors based on spike neural networks, such as Loihi and True North, are limited in their applications. For GPU-like architectures, power and speed of such architectures are limited by data transmission speed. Data transmission can consume up to 80% of chip power, and can significantly impact speed of calculations. Edge applications demand low power consumption, but there are currently no known performant hardware implementations that consume less than 50 milliwatts of power.
Memristor-based architectures that use cross-bar technology remain impractical for manufacturing recurrent and feed-forward neural networks. For example, memristor-based cross-bars have a number of disadvantages, including high latency and leakage of currents during operation, that make them impractical. Also, there are reliability issues in manufacturing memristor-based cross-bars, especially when neural networks have both negative and positive weights. For large neural networks with many neurons, at high dimensions, memristor-based cross-bars cannot be used for simultaneous propagation of different signals, which in turn complicates summation of signals, when neurons are represented by operational amplifiers. Furthermore, memristor-based analog integrated circuits have a number of limitations, such as a small number of resistive states, first cycle problem when forming memristors, complexity with channel formation when training the memristors, unpredictable dependency on dimensions of the memristors, slow operations of memristors, and drift of state of resistance.
Additionally, the training process required for neural networks presents unique challenges for hardware realization of neural networks. A trained neural network is used for specific inferencing tasks, such as classification. Once a neural network is trained, a hardware equivalent is manufactured. When the neural network is retrained, the hardware manufacturing process is repeated, driving up costs. Although some reconfigurable hardware solutions exist, such hardware cannot be easily mass produced, and cost a lot more (e.g., cost 5 times more) than hardware that is not reconfigurable. Further, edge environments, such as smart-home applications, do not require re-programmability as such. For example, 85% of all applications of neural networks do not require any retraining during operation, so on-chip learning is not that useful. Furthermore, edge applications include noisy environments, that can cause reprogrammable hardware to become unreliable.
SUMMARYAccordingly, there is a need for methods, circuits and/or interfaces that address at least some of the deficiencies identified above. Analog circuits that model trained neural networks and manufactured according to the techniques described herein, can provide improved performance per watt advantages, can be useful in implementing hardware solutions in edge environments, and can tackle a variety of applications, such as drone navigation and autonomous cars. The cost advantages provided by the proposed manufacturing methods and/or analog network architectures are even more pronounced with larger neural networks. Also, analog hardware implementations of neural networks provide improved parallelism and neuromorphism. Moreover, neuromorphic analog components are not sensitive to noise and temperature changes, when compared to digital counterparts.
Chips manufactured according to the techniques described herein provide order of magnitude improvements over conventional systems in size, power, and performance, and are ideal for edge environments, including for retraining purposes. Such analog neuromorphic chips can be used to implement edge computing applications or in Internet-of-Things (IoT) environments. Due to the analog hardware, initial processing (e.g., formation of descriptors for image recognition), that can consume over 80-90% of power, can be moved on chip, thereby decreasing energy consumption and network load that can open new markets for applications.
Various edge applications can benefit from use of such analog hardware. For example, for video processing, the techniques described herein can be used to include direct connection to CMOS sensor without digital interface. Various other video processing applications include road sign recognition for automobiles, camera-based true depth and/or simultaneous localization and mapping for robots, room access control without server connection, and always-on solutions for security and healthcare. Such chips can be used for data processing from radars and lidars, and for low-level data fusion. Such techniques can be used to implement battery management features for large battery packs, sound/voice processing without connection to data centers, voice recognition on mobile devices, wake up speech instructions for IoT sensors, translators that translate one language to another, large sensors arrays of IoT with low signal intensity, and/or configurable process control with hundreds of sensors.
Neuromorphic analog chips can be mass produced after standard software-based neural network simulations/training, according to some implementations. A client's neural network can be easily ported, regardless of the structure of the neural network, with customized chip design and production. Moreover, a library of ready to make on-chip solutions (network emulators) are provided, according to some implementations. Such solutions require only training, one lithographic mask change, following which chips can be mass produced. For example, during chip production, only part of the lithography masks need to be changed.
The techniques described herein can be used to design and/or manufacture an analog neuromorphic integrated circuit that is mathematically equivalent to a trained neural network (either feed-forward or recurrent neural networks). According to some implementations, the process begins with a trained neural network that is first converted into a transformed network comprised of standard elements. Operation of the transformed network are simulated using software with known models representing the standard elements. The software simulation is used to determine the individual resistance values for each of the resistors in the transformed network. Lithography masks are laid out based on the arrangement of the standard elements in the transformed network. Each of the standard elements are laid out in the masks using an existing library of circuits corresponding to the standard elements to simplify and speed up the process. In some implementations, the resistors are laid out in one or more masks separate from the masks including the other elements (e.g., operational amplifiers) in the transformed network. In this manner, if the neural network is retrained, only the masks containing the resistors, or other types of fixed-resistance elements, representing the new weights in the retrained neural network need to be regenerated, which simplifies and speeds up the process. The lithography masks are then sent to a fab for manufacturing the analog neuromorphic integrated circuit.
In one aspect, a method is provided for hardware realization of neural networks, according to some implementations. The method incudes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology to an equivalent analog network of analog components. The method also includes computing a weight matrix for the equivalent analog network based on the weights of the trained neural network. Each element of the weight matrix represents a respective connection between analog components of the equivalent analog network. The method also includes generating a schematic model for implementing the equivalent analog network based on the weight matrix, including selecting component values for the analog components.
In some implementations, generating the schematic model includes generating a resistance matrix for the weight matrix. Each element of the resistance matrix corresponds to a respective weight of the weight matrix and represents a resistance value.
In some implementations, the method further includes obtaining new weights for the trained neural network, computing a new weight matrix for the equivalent analog network based on the new weights, and generating a new resistance matrix for the new weight matrix.
In some implementations, the neural network topology includes one or more layers of neurons, each layer of neurons computing respective outputs based on a respective mathematical function, and transforming the neural network topology to the equivalent analog network of analog components includes: for each layer of the one or more layers of neurons: (i) identifying one or more function blocks, based on the respective mathematical function, for the respective layer. Each function block has a respective schematic implementation with block outputs that conform to outputs of a respective mathematical function; and (ii) generating a respective multilayer network of analog neurons based on arranging the one or more function blocks. Each analog neuron implements a respective function of the one or more function blocks, and each analog neuron of a first layer of the multilayer network is connected to one or more analog neurons of a second layer of the multilayer network.
In some implementations, the one or more function blocks include one or more basic function blocks selected from the group consisting of (i) a weighted summation block with a block output Vout=ReLU(Σwi·Viin+bias). ReLU is Rectified Linear Unit (ReLU) activation function or a similar activation function, Vi represents an i-th input, wi represents a weight corresponding to the i-th input, and bias represents a bias value, and Σ is a summation operator; (ii) a signal multiplier block with a block output Vout=coeff·Vi·Vj. Vi represents an i-th input and Vj represents a j-th input, and coeff is a predetermined coefficient; (iii) a sigmoid activation block with a block output
V represents an input, and A and B are predetermined coefficient values of the sigmoid activation block; (iv) a hyperbolic tangent activation block with a block output Vout=A*tanh (B*Vin). Vin represents an input, and A and B are predetermined coefficient values; and (v) a signal delay block with a block output U(t)=V(t−dt). t represents a current time-period, V(t−dt) represents an output of the signal delay block for a preceding time period t−dt, and dt is a delay value.
In some implementations, identifying the one or more function blocks includes selecting the one or more function blocks based on a type of the respective layer.
In some implementations, the neural network topology includes one or more layers of neurons, each layer of neurons computing respective outputs based on a respective mathematical function, and transforming the neural network topology to the equivalent analog network of analog components includes: (i) decomposing a first layer of the neural network topology to a plurality of sub-layers, including decomposing a mathematical function corresponding to the first layer to obtain one or more intermediate mathematical functions. Each sub-layer implements an intermediate mathematical function; and (ii) for each sub-layer of the first layer of the neural network topology: (a) selecting one or more sub-function blocks, based on a respective intermediate mathematical function, for the respective sub-layer; and (b) generating a respective multilayer analog sub-network of analog neurons based on arranging the one or more sub-function blocks. Each analog neuron implements a respective function of the one or more sub-function blocks, and each analog neuron of a first layer of the multilayer analog sub-network is connected to one or more analog neurons of a second layer of the multilayer analog sub-network.
In some implementations, the mathematical function corresponding to the first layer includes one or more weights, and decomposing the mathematical function includes adjusting the one or more weights such that combining the one or more intermediate functions results in the mathematical function.
In some implementations, the method further includes: (i) generating equivalent digital network of digital components for one or more output layers of the neural network topology; and (ii) connecting output of one or more layers of the equivalent analog network to the equivalent digital network of digital components.
In some implementations, the analog components include a plurality of operational amplifiers and a plurality of resistors, each operational amplifier represents an analog neuron of the equivalent analog network, and each resistor represents a connection between two analog neurons.
In some implementations, selecting component values of the analog components includes performing a gradient descent method to identify possible resistance values for the plurality of resistors.
In some implementations, the neural network topology includes one or more GRU or LSTM neurons, and transforming the neural network topology includes generating one or more signal delay blocks for each recurrent connection of the one or more GRU or LSTM neurons.
In some implementations, the one or more signal delay blocks are activated at a frequency that matches a predetermined input signal frequency for the neural network topology.
In some implementations, the neural network topology includes one or more layers of neurons that perform unlimited activation functions, and transforming the neural network topology includes applying one or more transformations selected from the group consisting of: (i) replacing the unlimited activation functions with limited activation; and (ii) adjusting connections or weights of the equivalent analog network such that, for predetermined one or more inputs, difference in output between the trained neural network and the equivalent analog network is minimized.
In some implementations, the method further includes generating one or more lithographic masks for fabricating a circuit implementing the equivalent analog network of analog components based on the resistance matrix.
In some implementations, the method further includes: (i) obtaining new weights for the trained neural network; (ii) computing a new weight matrix for the equivalent analog network based on the new weights; (iii) generating a new resistance matrix for the new weight matrix; and (iv) generating a new lithographic mask for fabricating the circuit implementing the equivalent analog network of analog components based on the new resistance matrix.
In some implementations, the trained neural network is trained using software simulations to generate the weights.
In another aspect, a method for hardware realization of neural networks is provided, according to some implementations. The method includes obtaining a neural network topology and weights of a trained neural network. The method also includes calculating one or more connection constraints based on analog integrated circuit (IC) design constraints. The method also includes transforming the neural network topology to an equivalent sparsely connected network of analog components satisfying the one or more connection constraints. The method also includes computing a weight matrix for the equivalent sparsely connected network based on the weights of the trained neural network. Each element of the weight matrix represents a respective connection between analog components of the equivalent sparsely connected network.
In some implementations, transforming the neural network topology to the equivalent sparsely connected network of analog components includes deriving a possible input connection degree Ni and output connection degree No, according to the one or more connection constraints.
In some implementations, the neural network topology includes at least one densely connected layer with K inputs and L outputs and a weight matrix U. In such cases, transforming the at least one densely connected layer includes constructing the equivalent sparsely connected network with K inputs, L outputs, and ┌logN
In some implementations, the neural network topology includes at least one densely connected layer with K inputs and L outputs and a weight matrix U. In such cases, transforming the at least one densely connected layer includes constructing the equivalent sparsely connected network with K inputs, L outputs, and M≥max(┌logN
In some implementations, the neural network topology includes a single sparsely connected layer with K inputs and L outputs, a maximum input connection degree of Pi, a maximum output connection degree of Po, and a weight matrix of U, where absent connections are represented with zeros. In such cases, transforming the single sparsely connected layer includes constructing the equivalent sparsely connected network with K inputs, L outputs, M≥max(┌logN
In some implementations, the neural network topology includes a convolutional layer with K inputs and L outputs. In such cases, transforming the neural network topology to the equivalent sparsely connected network of analog components includes decomposing the convolutional layer into a single sparsely connected layer with K inputs, L outputs, a maximum input connection degree of Pi, and a maximum output connection degree of Po. Pi≤Ni and Po≤No.
In some implementations, generating a schematic model for implementing the equivalent sparsely connected network utilizing the weight matrix.
In some implementations, the neural network topology includes a recurrent neural layer. In such cases, transforming the neural network topology to the equivalent sparsely connected network of analog components includes transforming the recurrent neural layer into one or more densely or sparsely connected layers with signal delay connections.
In some implementations, the neural network topology includes a recurrent neural layer. In such cases, transforming the neural network topology to the equivalent sparsely connected network of analog components includes decomposing the recurrent neural layer into several layers, where at least one of the layers is equivalent to a densely or sparsely connected layer with K inputs and L output and a weight matrix U, where absent connections are represented with zeros.
In some implementations, the neural network topology includes K inputs, a weight vector U∈RK, and a single layer perceptron with a calculation neuron with an activation function F. In such cases, transforming the neural network topology to the equivalent sparsely connected network of analog components includes: (i) deriving a connection degree N for the equivalent sparsely connected network according to the one or more connection constraints; (ii) calculating a number of layers m for the equivalent sparsely connected network using the equation m=┌logN K┐; and (iii) constructing the equivalent sparsely connected network with the K inputs, m layers and the connection degree N. The equivalent sparsely connected network includes respective one or more analog neurons in each layer of the m layers, each analog neuron of first m−1 layers implements identity transform, and an analog neuron of last layer implements the activation function F of the calculation neuron of the single layer perceptron. Also, in such cases, computing the weight matrix for the equivalent sparsely connected network includes calculating a weight vector W for connections of the equivalent sparsely connected network by solving a system of equations based on the weight vector U. The system of equations includes K equations with S variables, and S is computed using the equation
In some implementations, the neural network topology includes K inputs, a single layer perceptron with L calculation neurons, and a weight matrix V that includes a row of weights for each calculation neuron of the L calculation neurons. In such cases, transforming the neural network topology to the equivalent sparsely connected network of analog components includes: (i) deriving a connection degree N for the equivalent sparsely connected network according to the one or more connection constraints; (ii) calculating number of layers m for the equivalent sparsely connected network using the equation m=┌logN K┐; (iii) decomposing the single layer perceptron into L single layer perceptron networks. Each single layer perceptron network includes a respective calculation neuron of the L calculation neurons; (iv) for each single layer perceptron network of the L single layer perceptron networks: (a) constructing a respective equivalent pyramid-like sub-network for the respective single layer perceptron network with the K inputs, the m layers and the connection degree N. The equivalent pyramid-like sub-network includes one or more respective analog neurons in each layer of the m layers, each analog neuron of first m−1 layers implements identity transform, and an analog neuron of last layer implements the activation function of the respective calculation neuron corresponding to the respective single layer perceptron; and (b) constructing the equivalent sparsely connected network by concatenating each equivalent pyramid-like sub-network including concatenating an input of each equivalent pyramid-like sub-network for the L single layer perceptron networks to form an input vector with L*K inputs. Also, in such cases, computing the weight matrix for the equivalent sparsely connected network includes, for each single layer perceptron network of the L single layer perceptron networks: (i) setting a weight vector U=Vi, ith row of the weight matrix V corresponding to the respective calculation neuron corresponding to the respective single layer perceptron network; and (ii) calculating a weight vector Wi for connections of the respective equivalent pyramid-like sub-network by solving a system of equations based on the weight vector U. The system of equations includes K equations with S variables, and S is computed using the equation
In some implementations, the neural network topology includes K inputs, a multi-layer perceptron with S layers, each layer i of the S layers includes a corresponding set of calculation neurons Li and corresponding weight matrices V that includes a row of weights for each calculation neuron of the Li calculation neurons. In such cases, transforming the neural network topology to the equivalent sparsely connected network of analog components includes: (i) deriving a connection degree N for the equivalent sparsely connected network according to the one or more connection constraints; (ii) decomposing the multi-layer perceptron into Q=Σi=1,S(Li) single layer perceptron networks. Each single layer perceptron network includes a respective calculation neuron of the Q calculation neurons. Decomposing the multi-layer perceptron includes duplicating one or more input of the K inputs that are shared by the Q calculation neurons; (iii) for each single layer perceptron network of the Q single layer perceptron networks: (a) calculating a number of layers m for a respective equivalent pyramid-like sub-network using the equation m=┌logN Ki,j┐. Ki,j is number of inputs for the respective calculation neuron in the multi-layer perceptron; and (b) constructing the respective equivalent pyramid-like sub-network for the respective single layer perceptron network with Ki,j inputs, the m layers and the connection degree N. The equivalent pyramid-like sub-network includes one or more respective analog neurons in each layer of the m layers, each analog neuron of first m−1 layers implements identity transform, and an analog neuron of last layer implements the activation function of the respective calculation neuron corresponding to the respective single layer perceptron network; and (iv) constructing the equivalent sparsely connected network by concatenating each equivalent pyramid-like sub-network including concatenating input of each equivalent pyramid-like sub-network for the Q single layer perceptron networks to form an input vector with Q*Ki,j inputs. Also, in such cases, computing the weight matrix for the equivalent sparsely connected network includes: for each single layer perceptron network of the Q single layer perceptron networks: (i) setting a weight vector U=Vij, the ith row of the weight matrix V corresponding to the respective calculation neuron corresponding to the respective single layer perceptron network, where j is the corresponding layer of the respective calculation neuron in the multi-layer perceptron; and (ii) calculating a weight vector Wi for connections of the respective equivalent pyramid-like sub-network by solving a system of equations based on the weight vector U. The system of equations includes Ki,j equations with S variables, and S is computed using the equation
In some implementations, the neural network topology includes a Convolutional Neural Network (CNN) with K inputs, S layers, each layer i of the S layers includes a corresponding set of calculation neurons Li and corresponding weight matrices V that includes a row of weights for each calculation neuron of the Li calculation neurons. In such cases, transforming the neural network topology to the equivalent sparsely connected network of analog components includes: (i) deriving a connection degree N for the equivalent sparsely connected network according to the one or more connection constraints; (ii) decomposing the CNN into Q=Σi=1,S(Li) single layer perceptron networks. Each single layer perceptron network includes a respective calculation neuron of the Q calculation neurons. Decomposing the CNN includes duplicating one or more input of the K inputs that are shared by the Q calculation neurons; (iii) for each single layer perceptron network of the Q single layer perceptron networks: (a) calculating number of layers m for a respective equivalent pyramid-like sub-network using the equation m=┌logN Ki,j┐. j is the corresponding layer of the respective calculation neuron in the CNN, and Ki,j is number of inputs for the respective calculation neuron in the CNN; and (b) constructing the respective equivalent pyramid-like sub-network for the respective single layer perceptron network with Ki,j inputs, the m layers and the connection degree N. The equivalent pyramid-like sub-network includes one or more respective analog neurons in each layer of the m layers, each analog neuron of first m−1 layers implements identity transform, and an analog neuron of last layer implements the activation function of the respective calculation neuron corresponding to the respective single layer perceptron network; and (iv) constructing the equivalent sparsely connected network by concatenating each equivalent pyramid-like sub-network including concatenating input of each equivalent pyramid-like sub-network for the Q single layer perceptron networks to form an input vector with Q*Ki,j inputs. Also, in such cases, computing the weight matrix for the equivalent sparsely connected network includes, for each single layer perceptron network of the Q single layer perceptron networks: (i) setting a weight vector U=Vij, the ith row of the weight matrix V corresponding to the respective calculation neuron corresponding to the respective single layer perceptron network, where j is the corresponding layer of the respective calculation neuron in the CNN; and (ii) calculating weight vector Wi for connections of the respective equivalent pyramid-like sub-network by solving a system of equations based on the weight vector U. The system of equations includes Ki,j equations with S variables, and S is computed using the equation
In some implementations, the neural network topology includes K inputs, a layer Lp with K neurons, a layer Ln with L neurons, and a weight matrix W∈RL×K, where R is the set of real numbers, each neuron of the layer Lp is connected to each neuron of the layer Ln, each neuron of the layer Ln performs an activation function F, such that output of the layer Ln is computed using the equation Yo=F(W.x) for an input x. In such cases, transforming the neural network topology to the equivalent sparsely connected network of analog components includes performing a trapezium transformation that includes: (i) deriving a possible input connection degree NI>1 and a possible output connection degree NO>1, according to the one or more connection constraints; (ii) in accordance with a determination that K·L<L·NI+K·NO, constructing a three-layered analog network that includes a layer LAp with K analog neurons performing identity activation function, a layer LAh with
analog neurons performing identity activation function, and a layer LAo with L analog neurons performing the activation function F, such that each analog neuron in the layer LAp has No outputs, each analog neuron in the layer LAh has not more than Ni inputs and No outputs, and each analog neuron in the layer LAo has Ni inputs. Also, in such cases, computing the weight matrix for the equivalent sparsely connected network includes generating a sparse weight matrices Wo and Wh by solving a matrix equation Wo. Wh=W that includes K·L equations in K·NO+L·NI variables, so that the total output of the layer LAo is calculated using the equation Yo=F(Wo·Wh·x). The sparse weight matrix Wo∈RK×M represents connections between the layers LAp and LAh, and the sparse weight matrix Wh∈RM×L represents connections between the layers LAh and LAo.
In some implementations, performing the trapezium transformation further includes: in accordance with a determination that K·L≥L·NI+K·NO: (i) splitting the layer Lp to obtain a sub-layer Lp1 with K′ neurons and a sub-layer Lp2 with (K−K′) neurons such that K′·L≥L·NI+K′·NO; (ii) for the sub-layer Lpj with K′ neurons, performing the constructing, and generating steps; and (iii) for the sub-layer Lp2 with K−K′ neurons, recursively performing the splitting, constructing, and generating steps.
In some implementations, the neural network topology includes a multilayer perceptron network. In such cases, the method further includes, for each pair of consecutive layers of the multilayer perceptron network, iteratively performing the trapezium transformation and computing the weight matrix for the equivalent sparsely connected network.
In some implementations, the neural network topology includes a recurrent neural network (RNN) that includes (i) a calculation of linear combination for two fully connected layers, (ii) element-wise addition, and (iii) a non-linear function calculation. In such cases, the method further includes performing the trapezium transformation and computing the weight matrix for the equivalent sparsely connected network, for (i) the two fully connected layers, and (ii) the non-linear function calculation.
In some implementations, the neural network topology includes a long short-term memory (LSTM) network or a gated recurrent unit (GRU) network that includes (i) a calculation of linear combination for a plurality of fully connected layers, (ii) element-wise addition, (iii) a Hadamard product, and (iv) a plurality of non-linear function calculations. In such cases, the method further includes performing the trapezium transformation and computing the weight matrix for the equivalent sparsely connected network, for (i) the plurality of fully connected layers, and (ii) the plurality of non-linear function calculations.
In some implementations, the neural network topology includes a convolutional neural network (CNN) that includes (i) a plurality of partially connected layers and (ii) one or more fully-connected layers. In such cases, the method further includes: (i) transforming the plurality of partially connected layers to equivalent fully-connected layers by inserting missing connections with zero weights; and (ii) for each pair of consecutive layers of the equivalent fully-connected layers and the one or more fully-connected layers, iteratively performing the trapezium transformation and computing the weight matrix for the equivalent sparsely connected network.
In some implementations, the neural network topology includes K inputs, L output neurons, and a weight matrix U∈RL×K, where R is the set of real numbers, each output neuron performs an activation function F. In such cases, transforming the neural network topology to the equivalent sparsely connected network of analog components includes performing an approximation transformation that includes: (i) deriving a possible input connection degree NI>1 and a possible output connection degree No>1, according to the one or more connection constraints; (ii) selecting a parameter p from the set {0, 1, . . . , ┌logN
for all weights j of the neuron except ki; and (b) setting all other weights of the pyramid neural network to 1; and (ii) generating weights for the trapezium neural network including (a) setting weights of each neuron i of the first layer of the trapezium neural network according to the equation
and (b) setting other weights of the trapezium neural network to 1.
In some implementations, the neural network topology includes a multilayer perceptron with the K inputs, S layers, and Li=1,S calculation neurons in i-th layer, and a weight matrix Ui=1,S∈RL
In another aspect, a method is provided for hardware realization of neural networks, according to some implementations. The method includes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology to an equivalent analog network of analog components including a plurality of operational amplifiers and a plurality of resistors. Each operational amplifier represents an analog neuron of the equivalent analog network, and each resistor represents a connection between two analog neurons. The method also includes computing a weight matrix for the equivalent analog network based on the weights of the trained neural network. Each element of the weight matrix represents a respective connection. The method also includes generating a resistance matrix for the weight matrix. Each element of the resistance matrix corresponds to a respective weight of the weight matrix and represents a resistance value.
In some implementations, generating the resistance matrix for the weight matrix includes: (i) obtaining a predetermined range of possible resistance values {Rmin, Rmax} and selecting an initial base resistance value Rbase within the predetermined range; (ii) selecting a limited length set of resistance values, within the predetermined range, that provide most uniform distribution of possible weight
within the range [−Rbase, Rbase] for all combinations of {Ri, Rj} within the limited length set of resistance values; (iii) selecting a resistance value R+=R−, from the limited length set of resistance values, either for each analog neuron or for each layer of the equivalent analog network, based on maximum weight of incoming connections and bias wmax of each neuron or for each layer of the equivalent analog network, such that R+=R− is the closest resistor set value to Rbase*wmax; and (iv) for each element of the weight matrix, selecting a respective first resistance value R1 and a respective second resistance value R2 that minimizes an error according to equation
for all possible values of R1 and R2 within the predetermined range of possible resistance values. w is the respective element of the weight matrix, and rerr is a predetermined relative tolerance value for resistances.
In some implementations, the predetermined range of possible resistance values includes resistances according to nominal series E24 in the range 100 KΩ to 1 MΩ.
In some implementations, R+ and R− are chosen independently for each layer of the equivalent analog network.
In some implementations, R+ and R− are chosen independently for each analog neuron of the equivalent analog network.
In some implementations, a first one or more weights of the weight matrix and a first one or more inputs represent one or more connections to a first operational amplifier of the equivalent analog network. In such cases, the method further includes, prior to generating the resistance matrix: (i) modifying the first one or more weights by a first value; and (ii) configuring the first operational amplifier to multiply, by the first value, a linear combination of the first one or more weights and the first one or more inputs, before performing an activation function.
In some implementations, the method further includes: (i) obtaining a predetermined range of weights; and (ii) updating the weight matrix according to the predetermined range of weights such that the equivalent analog network produces similar output as the trained neural network for same input.
In some implementations, the trained neural network is trained so that each layer of the neural network topology has quantized weights.
In some implementations, the method further includes retraining the trained neural network to reduce sensitivity to errors in the weights or the resistance values that cause the equivalent analog network to produce different output compared to the trained neural network.
In some implementations, the method further includes retraining the trained neural network so as to minimize weight in any layer that are more than mean absolute weight for that layer by larger than a predetermined threshold.
In another aspect, a method is provided for hardware realization of neural networks, according to some implementations. The method includes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology to an equivalent analog network of analog components including a plurality of operational amplifiers and a plurality of resistors. Each operational amplifier represents an analog neuron of the equivalent analog network, and each resistor represents a connection between two analog neurons. The method also includes computing a weight matrix for the equivalent analog network based on the weights of the trained neural network. Each element of the weight matrix represents a respective connection. The method also includes generating a resistance matrix for the weight matrix. Each element of the resistance matrix corresponds to a respective weight of the weight matrix. The method also includes pruning the equivalent analog network to reduce number of the plurality of operational amplifiers or the plurality of resistors, based on the resistance matrix, to obtain an optimized analog network of analog components.
In some implementations, pruning the equivalent analog network includes substituting, with conductors, resistors corresponding to one or more elements of the resistance matrix that have resistance values below a predetermined minimum threshold resistance value.
In some implementations, pruning the equivalent analog network includes removing one or more connections of the equivalent analog network corresponding to one or more elements of the resistance matrix that are above a predetermined maximum threshold resistance value.
In some implementations, pruning the equivalent analog network includes removing one or more connections of the equivalent analog network corresponding to one or more elements of the weight matrix that are approximately zero.
In some implementations, pruning the equivalent analog network further includes removing one or more analog neurons of the equivalent analog network without any input connections.
In some implementations, pruning the equivalent analog network includes: (i) ranking analog neurons of the equivalent analog network based on detecting use of the analog neurons when making calculations for one or more data sets; (ii) selecting one or more analog neurons of the equivalent analog network based on the ranking; and (iii) removing the one or more analog neurons from the equivalent analog network.
In some implementations, detecting use of the analog neurons includes: (i) building a model of the equivalent analog network using a modelling software; and (ii) measuring propagation of analog signals by using the model to generate calculations for the one or more data sets.
In some implementations, detecting use of the analog neurons includes: (i) building a model of the equivalent analog network using a modelling software; and (ii) measuring output signals of the model by using the model to generate calculations for the one or more data sets.
In some implementations, detecting use of the analog neurons includes: (i) building a model of the equivalent analog network using a modelling software; and (ii) measuring power consumed by the analog neurons by using the model to generate calculations for the one or more data sets.
In some implementations, the method further includes subsequent to pruning the equivalent analog network, and prior to generating one or more lithographic masks for fabricating a circuit implementing the equivalent analog network, recomputing the weight matrix for the equivalent analog network and updating the resistance matrix based on the recomputed weight matrix.
In some implementations, the method further includes, for each analog neuron of the equivalent analog network: (i) computing a respective bias value for the respective analog neuron based on the weights of the trained neural network, while computing the weight matrix; (ii) in accordance with a determination that the respective bias value is above a predetermined maximum bias threshold, removing the respective analog neuron from the equivalent analog network; and (iii) in accordance with a determination that the respective bias value is below a predetermined minimum bias threshold, replacing the respective analog neuron with a linear junction in the equivalent analog network.
In some implementations, the method further includes reducing number of neurons of the equivalent analog network, prior to generating the weight matrix, by increasing number of connections from one or more analog neurons of the equivalent analog network.
In some implementations, the method further includes pruning the trained neural network to update the neural network topology and the weights of the trained neural network, prior to transforming the neural network topology, using pruning techniques for neural networks, so that the equivalent analog network includes less than a predetermined number of analog components.
In some implementations, the pruning is performed iteratively considering accuracy or a level of match in output between the trained neural network and the equivalent analog network.
In some implementations, the method further includes, prior to transforming the neural network topology to the equivalent analog network, performing network knowledge extraction.
In another aspect, an integrated circuit is provided, according to some implementations. The integrated circuit includes an analog network of analog components fabricated by a method that includes: (i) obtaining a neural network topology and weights of a trained neural network; (ii) transforming the neural network topology to an equivalent analog network of analog components including a plurality of operational amplifiers and a plurality of resistors. Each operational amplifier represents a respective analog neuron, and each resistor represents a respective connection between a respective first analog neuron and a respective second analog neuron; (iii) computing a weight matrix for the equivalent analog network based on the weights of the trained neural network. Each element of the weight matrix represents a respective connection; (iv) generating a resistance matrix for the weight matrix. Each element of the resistance matrix corresponds to a respective weight of the weight matrix; (v) generating one or more lithographic masks for fabricating a circuit implementing the equivalent analog network of analog components based on the resistance matrix; and (vi) fabricating the circuit based on the one or more lithographic masks using a lithographic process.
In some implementations, the integrated circuit further includes one or more digital to analog converters configured to generate analog input for the equivalent analog network of analog components based on one or more digital.
In some implementations, the integrated circuit further includes an analog signal sampling module configured to process 1-dimensional or 2-dimensional analog inputs with a sampling frequency based on number of inferences of the integrated circuit.
In some implementations, the integrated circuit further includes a voltage converter module to scale down or scale up analog signals to match operational range of the plurality of operational amplifiers.
In some implementations, the integrated circuit further includes a tact signal processing module configured to process one or more frames obtained from a CCD camera.
In some implementations, the trained neural network is a long short-term memory (LSTM) network. In such cases, the integrated circuit further includes one or more clock modules to synchronize signal tacts and to allow time series processing.
In some implementations, the integrated circuit further includes one or more analog to digital converters configured to generate digital signal based on output of the equivalent analog network of analog components.
In some implementations, the integrated circuit further includes one or more signal processing modules configured to process 1-dimensional or 2-dimensional analog signals obtained from edge applications.
In some implementations, the trained neural network is trained, using training datasets containing signals of arrays of gas sensors on different gas mixture, for selective sensing of different gases in a gas mixture containing predetermined amounts of gases to be detected. In such cases, the neural network topology is a 1-Dimensional Deep Convolutional Neural network (1D-DCNN) designed for detecting 3 binary gas components based on measurements by 16 gas sensors, and includes 16 sensor-wise 1-D convolutional blocks, 3 shared or common 1-D convolutional blocks and 3 dense layers. In such cases, the equivalent analog network includes: (i) a maximum of 100 input and output connections per analog neuron, (ii) delay blocks to produce delay by any number of time steps, (iii) a signal limit of 5, (iv) 15 layers, (v) approximately 100,000 analog neurons, and (vi) approximately 4,900,000 connections.
In some implementations, the trained neural network is trained, using training datasets containing thermal aging time series data for different MOSFETs, for predicting remaining useful life (RUL) of a MOSFET device. In such cases, the neural network topology includes 4 LSTM layers with 64 neurons in each layer, followed by two dense layers with 64 neurons and 1 neuron, respectively. In such cases, the equivalent analog network includes: (i) a maximum of 100 input and output connections per analog neuron, (ii) a signal limit of 5, (iii) 18 layers, (iv) between 3,000 and 3,200 analog neurons, and (v) between 123,000 and 124,000 connections.
In some implementations, the trained neural network is trained, using training datasets containing time series data including discharge and temperature data during continuous usage of different commercially available Li-Ion batteries, for monitoring state of health (SOH) and state of charge (SOC) of Lithium Ion batteries to use in battery management systems (BMS). In such cases, the neural network topology includes an input layer, 2 LSTM layers with 64 neurons in each layer, followed by an output dense layer with 2 neurons for generating SOC and SOH values. In such cases, the equivalent analog network includes: (i) a maximum of 100 input and output connections per analog neuron, (ii) a signal limit of 5, (iii) 9 layers, (iv) between 1,200 and 1,300 analog neurons, and (v) between 51,000 and 52,000 connections.
In some implementations, the trained neural network is trained, using training datasets containing time series data including discharge and temperature data during continuous usage of different commercially available Li-Ion batteries, for monitoring state of health (SOH) of Lithium Ion batteries to use in battery management systems (BMS). In such cases, the neural network topology includes an input layer with 18 neurons, a simple recurrent layer with 100 neurons, and a dense layer with 1 neuron. In such cases, the equivalent analog network includes: (i) a maximum of 100 input and output connections per analog neuron, (ii) a signal limit of 5, (iii) 4 layers, (iv) between 200 and 300 analog neurons, and (v) between 2,200 and 2,400 connections.
In some implementations, the trained neural network is trained, using training datasets containing speech commands, for identifying voice commands. In such cases, the neural network topology is a Depthwise Separable Convolutional Neural Network (DS-CNN) layer with 1 neuron. In such cases, the equivalent analog network includes: (i) a maximum of 100 input and output connections per analog neuron, (ii) a signal limit of 5, (iii) 13 layers, (iv) approximately 72,000 analog neurons, and (v) approximately 2.6 million connections.
In some implementations, the trained neural network is trained, using training datasets containing photoplethysmography (PPG) data, accelerometer data, temperature data, and electrodermal response signal data for different individuals performing various physical activities for a predetermined period of times and reference heart rate data obtained from ECG sensor, for determining pulse rate during physical exercises based on PPG sensor data and 3-axis accelerometer data. In such cases, the neural network topology includes two Conv1D layers each with 16 filters and a kernel of 20, performing time series convolution, two LSTM layers each with 16 neurons, and two dense layers with 16 neurons and 1 neuron, respectively. In such cases, the equivalent analog network includes: (i) delay blocks to produce any number of time steps, (ii) a maximum of 100 input and output connections per analog neuron, (iii) a signal limit of 5, (iv) 16 layers, (v) between 700 and 800 analog neurons, and (vi) between 12,000 and 12,500 connections.
In some implementations, the trained neural network is trained to classify different objects based on pulsed Doppler radar signal. In such cases, the neural network topology includes multi-scale LSTM neural network.
In some implementations, the trained neural network is trained to perform human activity type recognition, based on inertial sensor data. In such cases, the neural network topology includes three channel-wise convolutional networks each with a convolutional layer of 12 filters and a kernel dimension of 64, and each followed by a max pooling layer, and two common dense layers of 1024 neurons and N neurons, respectively, where N is a number of classes. In such cases, the equivalent analog network includes: (i) delay blocks to produce any number of time steps, (ii) a maximum of 100 input and output connections per analog neuron, (iii) an output layer of 10 analog neurons, (iv) signal limit of 5, (v) 10 layers, (vi) between 1,200 and 1,300 analog neurons, and (vi) between 20,000 and 21,000 connections.
In some implementations, the trained neural network is further trained to detect abnormal patterns of human activity based on accelerometer data that is merged with heart rate data using a convolution operation.
In another aspect, a method is provided for generating libraries for hardware realization of neural networks. The method includes obtaining a plurality of neural network topologies, each neural network topology corresponding to a respective neural network. The method also includes transforming each neural network topology to a respective equivalent analog network of analog components. The method also includes generating a plurality of lithographic masks for fabricating a plurality of circuits, each circuit implementing a respective equivalent analog network of analog components.
In some implementations, the method further includes obtaining a new neural network topology and weights of a trained neural network. The method also includes selecting one or more lithographic masks from the plurality of lithographic masks based on comparing the new neural network topology to the plurality of neural network topologies. The method also includes computing a weight matrix for a new equivalent analog network based on the weights. The method also includes generating a resistance matrix for the weight matrix. The method also includes generating anew lithographic mask for fabricating a circuit implementing the new equivalent analog network based on the resistance matrix and the one or more lithographic masks.
In some implementations, the new neural network topology includes a plurality of subnetwork topologies, and selecting the one or more lithographic masks is further based on comparing each subnetwork topology with each network topology of the plurality of network topologies.
In some implementations, one or more subnetwork topologies of the plurality of subnetwork topologies fails to compare with any network topology of the plurality of network topologies. In such cases, the method further includes: (i) transforming each subnetwork topology of the one or more subnetwork topologies to a respective equivalent analog subnetwork of analog components; and (ii) generating one or more lithographic masks for fabricating one or more circuits, each circuit of the one or more circuits implementing a respective equivalent analog subnetwork of analog components.
In some implementations, transforming a respective network topology to a respective equivalent analog network includes: (i) decomposing the respective network topology to a plurality of subnetwork topologies; (ii) transforming each subnetwork topology to a respective equivalent analog subnetwork of analog components; and (iii) composing each equivalent analog subnetwork to obtain the respective equivalent analog network.
In some implementations, decomposing the respective network topology includes identifying one or more layers of the respective network topology as the plurality of subnetwork topologies.
In some implementations, each circuit is obtained by: (i) generating schematics for a respective equivalent analog network of analog components; and (ii) generating a respective circuit layout design based on the schematics.
In some implementations, the method further includes combining one or more circuit layout designs prior to generating the plurality of lithographic masks for fabricating the plurality of circuits.
In another aspect, a method is provided for optimizing energy efficiency of analog neuromorphic circuits, according to some implementations. The method includes obtaining an integrated circuit implementing an analog network of analog components including a plurality of operational amplifiers and a plurality of resistors. The analog network represents a trained neural network, each operational amplifier represents a respective analog neuron, and each resistor represents a respective connection between a respective first analog neuron and a respective second analog neuron. The method also include generating inferences using the integrated circuit for a plurality of test inputs, including simultaneously transferring signals from one layer to a subsequent layer of the analog network. The method also includes, while generating inferences using the integrated circuit: (i) determining if a level of signal output of the plurality of operational amplifiers is equilibrated; and (ii) in accordance with a determination that the level of signal output is equilibrated: (a) determining an active set of analog neurons of the analog network influencing signal formation for propagation of signals; and (turning off power for one or more analog neurons of the analog network, distinct from the active set of analog neurons, for a predetermined period of time.
In some implementations, determining the active set of analog neurons is based on calculating delays of signal propagation through the analog network.
In some implementations, determining the active set of analog neurons is based on detecting the propagation of signals through the analog network.
In some implementations, the trained neural network is a feed-forward neural network, and the active set of analog neurons belong to an active layer of the analog network, and turning off power includes turning off power for one or more layers prior to the active layer of the analog network.
In some implementations, the predetermined period of time is calculated based on simulating propagation of signals through the analog network, accounting for signal delays.
In some implementations, the trained neural network is a recurrent neural network (RNN), and the analog network further includes one or more analog components other than the plurality of operational amplifiers, and the plurality of resistors. In such cases, the method further includes, in accordance with a determination that the level of signal output is equilibrated, turning off power, for the one or more analog components, for the predetermined period of time.
In some implementations, the method further includes turning on power for the one or more analog neurons of the analog network after the predetermined period of time.
In some implementations, determining if the level of signal output of the plurality of operational amplifiers is equilibrated is based on detecting if one or more operational amplifiers of the analog network is outputting more than a predetermined threshold signal level.
In some implementations, the method further includes repeating the turning off for the predetermined period of time and turning on the active set of analog neurons for the predetermined period of time, while generating the inferences.
In some implementations, the method further includes: (i) in accordance with a determination that the level of signal output is equilibrated, for each inference cycle: (a) during a first time interval, determining a first layer of analog neurons of the analog network influencing signal formation for propagation of signals; and (b) turning off power for a first one or more analog neurons of the analog network, prior to the first layer, for the predetermined period of time; and (ii) during a second time interval subsequent to the first time interval, turning off power for a second one or more analog neurons including the first layer of analog neurons and the first one or more analog neurons of the analog network, for the predetermined period.
In some implementations, the one or more analog neurons consist of analog neurons of a first one or more layers of the analog network, and the active set of analog neurons consist of analog neurons of a second layer of the analog network, and the second layer of the analog network is distinct from layers of the first one or more layers.
In another aspect, a method is provided for hardware realization of neural networks. The method includes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology to an equivalent analog network of analog components, including replacing composition or superposition of linear transformations by a single linear transformation. The method also includes computing a weight matrix for the equivalent analog network based on the weights of the trained neural network, wherein each element of the weight matrix represents a respective connection between analog components of the equivalent analog network. The method also includes generating a schematic model for implementing the equivalent analog network based on the weight matrix, including selecting component parameter values for the analog components.
In some implementations, the method further includes, prior to transforming the neural network topology to the equivalent analog network: adding regularizers to the neural network topology to reduce nominal values of the weights or to a respective reduce weight sum for each neuron; and retraining the trained neural network to obtain updated weights for the weight matrix.
In some implementations, the regularizers include a respective predetermined regularizer for each convolution batch normalization ReLU block. Each predetermined regularizer treats each batch normalization layer as a normalization and calculates combined convolution-batch normalization multipliers applied to an input neural network signal in the signal's propagation path, and reduces the absolute value of the combined weights for each neuron.
In some implementations, transforming the neural network topology into the equivalent analog network includes translating weights of each batch normalization layer to weights of its previous layer.
In some implementations, transforming the neural network topology into the equivalent analog network includes merging layers that do not have an activation function.
In some implementations, transforming the neural network topology into the equivalent analog network includes transforming a linear transformation followed by another linear transformation into a single linear transformation.
In some implementations, transforming the neural network topology into the equivalent analog network includes transforming layers with ReLU into ReLU1. In some implementations, transforming layers with ReLU into ReLU1 includes maintaining normal operation of the trained neural network during the transformation by analyzing the passage of signals through the trained neural network and performing weight correction.
In some implementations, performing weight correction includes adjusting weights so as to restrict signals in the neural network below a physical limit. In some implementations, performing weight correction includes: when the weights of a layer N are divided by a factor, adjusting the weights of layer N+1 by multiplying the weights by the factor. In some implementations, performing weight correction includes: adjusting weights and bias of one or more neurons and adjustment of weights of outgoing connections of the one or more neurons. In some implementations, performing weight correction includes: repeating weight correction for the trained neural network until complete compliance is achieved. In some implementations, performing weight correction includes scaling signals on layers with unlimited ReLU so that they do not exceed a physical limitation.
In some implementations, transforming the neural network topology to the equivalent analog network includes introducing additional intermediate layers that limit the number of input or output links of neurons by splitting inputs or outputs of the neurons.
In some implementations, the method further includes pruning at least some of the connections of the neural network topology.
In some implementations, the method further includes quantizing and/or restricting the weights of the neural network topology.
In some implementations, the method further includes identifying non-linear elements in the neural network topology.
In some implementations, the method further includes: (i) calculating a respective range of weights for each layer of the neural network topology and (ii) calculating a respective sum of the weights for each neuron of the neural network topology.
In another aspect, a method is provided for hardware realization of neural networks. The method includes obtaining a neural network topology and weights of a trained neural network. In some implementations, the trained neural network is trained using software simulations to generate the weights. The method transforms the neural network topology into an equivalent analog network of analog components including a plurality of operational amplifiers and a plurality of resistors. Each operational amplifier represents an analog neuron of the equivalent analog network, and each resistor represents a connection between two analog neurons. Transforming the neural network topology includes performing resistor quantization and operational amplifier quantization to obtain a quantized network for the equivalent analog network.
In some implementations, the quantized network is obtained by analyzing output tolerance of the neural network using Monte-Carlo simulation where resistors and operational amplifier parameters are considered having stochastic components caused by temperature shift and manufacturing tolerance.
In some implementations, performing resistor quantization includes converting a vector of weights of the trained neural network to particular resistor values of a single analog neuron. In some implementations, the resistor values are discrete values from a pre-determined resistor set. Each resistor in the resistor set is characterized by a respective resistance value and a respective tolerance value. In some implementations, the resistor values are limited to a continuous range.
In some implementations, performing resistor quantization includes solving a system of equations and/or inequalities connecting weights of the trained neural network and resistor values. The number of resistors is more than twice the number of weights, and the system of equations has a plurality solutions. In some implementations, solving the system of equations includes selecting a solution based on one or more optimization criteria. The criteria include (i) energy consumption (tends to maximize resistor values), (ii) die area (tends to minimize resistor values), and (iii) minimization of one or more error metrics (tends to minimize negative input relative (to feedback) resistors values. Some implementations also consider optimality criteria, such as die size, energy consumption, and/or tolerance, which are partially competing objectives. Some implementations reduce the complexity of the task for specific cases using particular schematic options. In some implementations, the one or more optimization criteria include R-quantization error (EQR), which is the mean error of the equivalent analog network with quantized resistors and perfect operational amplifiers versus a math network on a set of input data. In some implementations, the one or more optimization criteria include RO-quantization error (EQRO), which is the mean error of the equivalent analog network with quantized resistors and imperfect operational amplifiers with a particular pre-defined output model versus the math network on the set of input data. Imperfect operational amplifiers have some design flaws (designed in silicon) and produce slightly different output from perfect operational amplifiers. In some implementations, the one or more optimization criteria include RO-quantization R-randomization error (EQRO-RR), which is the mean error of the equivalent analog network with quantized resistors with random tolerance error and imperfect operational amplifiers with a predefined output model versus the math network on the set of input data. In some implementations, the one or more optimization criteria include RO-quantization RO-randomization error (EQRO-RRO), which is the mean error of a T-network with quantized resistors with random tolerance error and imperfect operational amplifiers with a predetermined output model and random tolerance error. Some implementations use Monte-Carlo methods for this modeling.
In some implementations, performing operational amplifier quantization includes selecting an appropriate operational amplifier model from a set of predetermined operational amplifier models according to a set of predetermined limitations and/or optimality criteria. In some implementations, the set of predetermined limitations and/or optimality criteria includes limitations of operational amplifiers for output currents. In some implementations, the set of predetermined limitations and/or optimality criteria includes neuron or operational amplifier die area limitations or minimization. In some implementations, the set of predetermined limitations and/or optimality criteria includes neuron or operational amplifier energy consumption limitations or minimization. In some implementations, the set of predetermined limitations and/or optimality criteria includes operational amplifier input voltage range limitations. In some implementations, the set of predetermined limitations and/or optimality criteria includes minimization of error metrics for resistor quantization.
The method also includes generating, based on the quantized network, a functional behavioral model, which includes the plurality of operational amplifiers placed in front-end of line layers (FEOL layers) and the plurality of resistances placed in back-end of line layers (BEOL layers).
In another aspect, a system is provided for producing analog neuromorphic computing hardware. The system includes one or more processors, memory, a plurality of library routines stored in the memory. The plurality of library routines includes (i) an input interface library routine configured to convert linear digital signals or consecutive analog signals to an array of parallel analog inputs for analog neural networks, (ii) a power management unit library routine configured to switch on or switch off layers of the analog neural networks, and (iii) an output interface library routine configured to digitize analog output from the analog neural networks. One or more programs are stored in the memory. The one or more programs are configured for execution by the one or more processors and include instructions for: receiving an analog neural network specification; extracting a plurality of parameter values, from the analog neural network specification, corresponding to parameters of the library routines; and generating a chip fabrication specification that includes an analog neural network corresponding to the analog neural network specification, the input interface library routine, the power management unit library routine, and the output interface library routine, using the plurality of parameter values for the library routines.
In some implementations, the input interface library routine includes a specification for one or more digital to analog converters configured to generate analog input for the analog neural core based on one or more digital signals.
In some implementations, the input interface library routine comprises specifications for a plurality of devices selected from the group consisting of samplers, analog-to-digital converters, de-serializers, digital-to-analog converters, FIFO buffers, and hold units.
In some implementations, the output interface library routine comprises a specification for one or more analog to digital converters configured to digitize analog output from the final layers of neurons of the analog neural core.
In some implementations, the input interface library routine and the output interface library routine are configured to interface with the analog neural core representing an arbitrary neural network, based on the number of inputs, the number of outputs, and the type of the analog neural core.
In some implementations, the power management unit library routine is configured to control power supplied to the layers of the analog neural core based on the number of layers of the analog neural core.
In some implementations, the output interface library routine includes specifications for a variable number of comparators, multiplexers and analog-to-digital converters (ADCs) with different resolutions. The number of comparators, the number of multiplexers, and the number of ADCs are determined based on devices necessary for proper quantization of outputs of the analog neural core.
In some implementations, the input interface library routine and the output interface library routine are further configured to sample signals at a frequency determined based on physical activity levels of a user of the apparatus.
In some implementations, the chip fabrication specification further includes specification for a host interface in communications with a host processor that is configured to control the analog neural core.
In some implementations, the chip fabrication specification includes a specification for a reconfiguration unit configured to reconfigure the analog neural core depending on the type of inference application executed on the analog neural core.
In some implementations, the chip fabrication specification includes a specification for a telemetry unit configured to track performance of the analog neural core.
In some implementations, the analog neural core is configured to reset the apparatus initiate an interface for a system host to write a program into a memory of the apparatus using direct memory access (DMA) operations that in turn causes the apparatus to perform initialization steps, begin execution of the analog neural core, and send output to the system host.
In some implementations, the analog neural core is configured to reset a chip fabricated using the specification and to read a program into a memory of the chip from an external non-volatile memory (NVM) that in turn causes the chip to perform initialization steps, begin execution, and send control signals to one or more actuators.
In some implementations, the power management unit is configured to dynamically disable or enable each layer of the analog neural core during signal propagation.
In some implementations, the power management unit is programmed based on transistor-level simulations and/or test chip measurements of the analog neural core, and wherein the power management unit is configured to store enable or disable configurations in an on-chip nonvolatile memory.
In some implementations, a computer system has one or more processors and memory. The one or more programs include instructions for performing any of the methods described herein.
In some implementations, a non-transitory computer readable storage medium stores one or more programs configured for execution by a computer system having one or more processors and memory. The one or more programs include instructions for performing any of the methods described herein.
Thus, methods, systems, and devices are disclosed that are used for hardware realization of trained neural networks.
For a better understanding of the aforementioned systems, methods, and graphical user interfaces, as well as additional systems, methods, and graphical user interfaces that provide data visualization analytics and data preparation, reference should be made to the Description of Implementations below, in conjunction with the following drawings in which like reference numerals refer to corresponding parts throughout the figures.
Reference will now be made to implementations, examples of which are illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without requiring these specific details.
DESCRIPTION OF IMPLEMENTATIONSIn some implementations, components of the system 100 described above are implemented in one or more computing devices or server systems as computing modules.
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- an operating system 216, which includes procedures for handling various basic system services and for performing hardware dependent tasks;
- a communications module 218, which is used for connecting the computing device 200 to other computers and devices via the one or more communication network interfaces 204 (wired or wireless) and one or more communication networks, such as the Internet, other wide area networks, local area networks, metropolitan area networks, and so on;
- trained neural networks 220 that includes weights 222 and neural network topologies 224. Examples of input neural networks are described below in reference to
FIGS. 4A-4C ,FIG. 12 ,FIGS. 13A, and 14A , according to some implementations; - a neural network transformation module 226 that includes transformed analog neural networks 228, mathematical formulations 230, the basic function blocks 232, analog models 234 (sometimes called neuron models), and/or analog integrated circuit (IC) design constraints 236. Example operations of the neural network transformation module 226 are described below in reference to at least
FIGS. 5, 6A-6C, 7, 8, 9, 10, and 11A-11C , and the flowcharts shown inFIGS. 27A-27B ,FIGS. 28A-28C , andFIGS. 29A-29B ; and/or - a weight matrix computation (sometimes called a weight quantization) module 238 that includes weights 272 of transformed networks, and optionally includes resistance calculation module 240, resistance values 242. Example operations of the weight matrix computation module 238 and/or weight quantization are described in reference to at least
FIGS. 17A-17C ,FIGS. 18A and 18B , andFIGS. 29A-29F , according to some implementations.
Some implementations include one or more optional modules 244 as shown in
Some implementations include a lithographic mask generation module 248 that further includes lithographic masks 250 for resistances (corresponding to connections), and/or lithographic masks for analog components (e.g., operational amplifiers, multipliers, delay blocks, etc.) other than the resistances (or connections). In some implementations, lithographic masks are generated based on chip design layout following chip design using Cadence, Synopsys, or Mentor Graphics software packages. Some implementations use a design kit from a silicon wafer manufacturing plant (sometimes called a fab). Lithographic masks are intended to be used in that particular fab that provides the design kit (e.g., TSMC 65 nm design kit). The lithographic mask files that are generated are used to fabricate the chip at the fab. In some implementations, the Cadence, Mentor Graphics, or Synopsys software packages-based chip design is generated semi-automatically from the SPICE or Fast SPICE (Mentor Graphics) software packages. In some implementations, a user with chip design skill drives the conversion from the SPICE or Fast SPICE circuit into Cadence, Mentor Graphics or Synopsis chip design. Some implementations combine Cadence design blocks for single neuron unit, establishing proper interconnects between the blocks.
Some implementations include a library generation module 254 that further includes libraries of lithographic masks 256. Examples of library generation are described below in reference to
Some implementations include Integrated Circuit (IC) fabrication module 258 that further includes Analog-to-Digital Conversion (ADC), Digital-to-Analog Conversion (DAC), or similar other interfaces 260, and/or fabricated ICs or models 262. Example integrated circuits and/or related modules are described below in reference to
Some implementations include an energy efficiency optimization module 264 that further includes an inferencing module 266, a signal monitoring module 268, and/or a power optimization module 270. Examples of energy efficiency optimizations are described below in reference to
Each of the above identified executable modules, applications, or sets of procedures may be stored in one or more of the previously mentioned memory devices, and corresponds to a set of instructions for performing a function described above. The above identified modules or programs (i.e., sets of instructions) need not be implemented as separate software programs, procedures, or modules, and thus various subsets of these modules may be combined or otherwise rearranged in various implementations. In some implementations, the memory 214 stores a subset of the modules and data structures identified above. Furthermore, in some implementations, the memory 214 stores additional modules or data structures not described above.
Although
In the description above and below, a math neuron is a mathematical function which receives one or more weighted inputs and produces a scalar output. In some implementations, a math neuron can have memory (e.g., long short-term memory (LSTM), recurrent neuron). A trivial neuron is a math neuron that performs a function, representing an ‘ideal’ mathematical neuron, Vout=ƒ(Σ(Viin·ωi+bias), where f(x) is an activation function. A SNM is a schematic model with analog components (e.g., operational amplifiers, resistors Ri, . . . , Rn, and other components) representing a specific type of math neuron (for example, trivial neuron) in schematic form. SNM output voltage is represented by a corresponding formula that depends on K input voltages and SNM component values Vout=g(Viin, . . . , VKin, R1 . . . Rn). According to some implementations, with properly selected component values, SNM formula is equivalent to math neuron formula, with a desired weights set. In some implementations, the weights set is fully determined by resistors used in a SNM. A target (analog) neural network 304 (sometimes called a T-network) is a set of math neurons which have defined SNM representation, and weighted connections between them, forming a neural network. A T-network follows several restrictions, such as an inbound limit (a maximum limit of inbound connections for any neuron within the T-network), an outbound limit (a maximum limit of outbound connections for any neuron within the T-network), and a signal range (e.g., all signals should be inside pre-defined signal range). T-transformation (322) is a process of converting some desired neural network, such as MobileNet, to a corresponding T-network. A SPICE model 306 is a SPICE Neural Network model of a T-network 304, where each math neuron is substituted with corresponding one or more SNMs. A Cadence NN model 310 is a Cadence model of the T-network 304, where each math neuron is substituted with a corresponding one or more SNMs. Also, as described herein, two networks L and M have mathematical equivalence, if for all neuron outputs of these networks |ViL−ViM|<eps, where eps is relatively small (e.g., between 0.1-1% of operating voltage range). Also, two networks L and M have functional equivalence, if for a given validation input data set {I1, . . . , In}, the classification results are mostly the same, i.e., P(L(Ik)=M(Ik))=1−eps, where eps is relatively small.
Some implementations store the layout or the organization of the input neural networks including number of neurons in each layer, total number of neurons, operations or activation functions of each neuron, and/or connections between the neurons, in the memory 214, as the neural network topology 224.
Some implementations use Keras learning that converges in approximately 1000 iterations, and results in weights for the connections. In some implementations, the weights are stored in memory 214, as part of the weights 222. In the following example, data format is ‘Neuron [1st link weight, 2nd link weight, bias]’.
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- N1 [−0.9824321, 0.976517, −0.00204677];
- N2 [1.0066702, −1.0101418, −0.00045485];
- N3 [1.0357606, 1.0072469, −0.00483723];
- N4 [−0.07376373, −0.7682612, 0.0]; and
- N5 [1.0029935, −1.1994369, −0.00147767].
Next, to compute resistor values for connections between the neurons, some implementations compute resistor range. Some implementations set resistor nominal values (R+, R−) of 1 MΩ, possible resistor range of 100 KΩ to 1 MΩ and nominal series E24. Some implementations compute w1, w2, wbias resistor values for each connection as follows. For each weight value wi (e.g., the weights 222), some implementations evaluate all possible (Ri−, Ri+) resistor pairs options within the chosen nominal series and choose a resistor pair which produces minimal error value
The following table provides example values for the weights w1, w2, and bias, for each connection, according to some implementations.
Before describing examples of transformation, it is worth noting some of the advantages of the transformed neural networks over conventional architectures. As described herein, the input trained neural networks are transformed to pyramid- or trapezium-shaped analog networks. Some of the advantages of pyramid or trapezium over cross bars include lower latency, simultaneous analog signal propagation, possibility for manufacture using standard integrated circuit (IC) design elements, including resistors and operational amplifiers, high parallelism of computation, high accuracy (e.g., accuracy increases with the number of layers, relative to conventional methods), tolerance towards error(s) in each weight and/or at each connection (e.g., pyramids balance the errors), low RC (low Resistance Capacitance delay related to propagation of signal through network), and/or ability to manipulate biases and functions of each neuron in each layer of the transformed network. Also, pyramids are excellent computation block by itself, since it is a multi-level perceptron, which can model any neural network with one output. Networks with several outputs are implemented using different pyramids or trapezia geometry, according to some implementations. A pyramid can be thought of as a multi-layer perceptron with one output and several layers (e.g., N layers), where each neuron has n inputs and 1 output. Similarly, a trapezium is a multilayer perceptron, where each neuron has n inputs and m outputs. Each trapezium is a pyramid-like network, where each neuron has n inputs and m outputs, where n and m are limited by IC analog chip design limitations, according to some implementations.
Some implementations perform lossless transformation of any trained neural network into subsystems of pyramids or trapezia. Thus, pyramids and trapezia can be used as universal building blocks for transforming any neural networks. An advantage of pyramid- or trapezia-based neural networks is the possibility to realize any neural network using standard IC analog elements (e.g., operational amplifiers, resistors, signal delay lines in case of recurrent neurons) using standard lithography techniques. It is also possible to restrict the weights of transformed networks to some interval. In other words, lossless transformation is performed with weights limited to some predefined range, according to some implementations. Another advantage of using pyramids or trapezia is the high degree of parallelism in signal processing or the simultaneous propagation of analog signals that increases the speed of calculations, providing lower latency. Moreover, many modern neural networks are sparsely connected networks and are much better (e.g., more compact, have low RC values, absence of leakage currents) when transformed into pyramids than into cross-bars, Pyramids and trapezia networks are relatively more compact than cross-bar based memristor networks.
Furthermore, analog neuromorphic trapezia-like chips possess a number of properties, not typical for analog devices. For example, signal to noise ratio is not increasing with the number of cascades in analog chip, the external noise is suppressed, and influence of temperature is greatly reduced. Such properties make trapezia-like analog neuromorphic chips analogous to digital circuits. For example, individual neurons, based on operational amplifier, level the signal and are operated with the frequencies of 20,000-100,000 Hz, and are not influenced by noise or signals with frequency higher than the operational range, according to some implementations. Trapezia-like analog neuromorphic chip also perform filtration of output signal due to peculiarities in how operational amplifiers function. Such trapezia-like analog neuromorphic chip suppresses the synphase noise. Due to low-ohmic outputs of operational amplifiers, the noise is also significantly reduced. Due to the leveling of signal at each operational amplifier output and synchronous work of amplifiers, the drift of parameters, caused by temperature does not influence the signals at final outputs. Trapezia-like analogous neuromorphic circuit is tolerant towards the errors and noise in input signals and is tolerant towards deviation of resistor values, corresponding to weight values in neural network. Trapezia-like analog neuromorphic networks are also tolerant towards any kind of systemic error, like error in resistor value settings, if such error is same for all resistors, due to the very nature of analog neuromorphic trapezia-like circuits, based on operational amplifiers.
Example Lossless Transformation (T-Transformation) of Trained Neural NetworksIn some implementations, the example transformations described herein are performed by the neural network transformation module 226 that transform trained neural networks 220, based on the mathematical formulations 230, the basic function blocks 232, the analog component models 234, and/or the analog design constraints 236, to obtain the transformed neural networks 228.
Example Transformations with Target Neurons with N Inputs and 1 Output
In some implementations, the example transformations described herein are performed by the neural network transformation module 226 that transform trained neural networks 220, based on the mathematical formulations 230, the basic function blocks 232, the analog component models 234, and/or analog design constraints 236, to obtain the transformed neural networks 228.
Single Layer Perceptron with One Output
Suppose a single layer perceptron SLP(K,1) includes K inputs and one output neuron with activation function F. Suppose further U∈RK is a vector of weights for SLP(K,1). The following algorithm Neuron2TNN1 constructs a T-neural network from T-neurons with N inputs and 1 output (referred to as TN(N,1)).
Algorithm Neuron2TNN1
-
- 1. Construct an input layer for T-NN by including all inputs from SLP(K,1).
- 2. If K>N then:
- a. Divide K input neurons into
-
-
- groups such that every group consists of no more than N inputs.
- b. Construct the first hidden layer LTH1 of the T-NN from m1 neurons, each neuron performing an identity activation function.
- c. Connect input neurons from every group to corresponding neuron from the next layer. So every neuron from the LTH1 has no more than N input connections.
- d. Set the weights for the new connections according the following equation:
-
-
- 3. Else (i.e., if K<=N) then):
- a. Construct the output layer with 1 neuron calculating activation function F
- b. Connect input neurons to the single output neuron. It has K≤N connections.
- c. Set the weights of the new connections by means of the following equation:
- 3. Else (i.e., if K<=N) then):
wj1=uj,j=1, . . . ,K
-
-
- d. Terminate the algorithm
- 4. Set l=1
- 5. If ml>N:
- a. Divide ml neurons into
-
-
-
- groups, every group consists of no more than N neurons.
- b. Construct the hidden layer LTHl+1 of the T-NN from ml+1 neurons, every neuron has identity activation function.
- c. Connect input neurons from every group to the corresponded neuron from the next layer.
- d. Set the weights of the new connections according the following equation:
-
-
-
- e. Set l=l+1
- 6. Else (if m>=N):
- a. Construct the output layer with 1 neuron calculating activation function F
- b. Connect all LTHl's neurons to the single output neuron.
- c. Set the weights of the new connections according the following equation:
-
wjl+1=1 a.
-
-
- d. Terminate the algorithm
- 7. Repeat steps 5 and 6.
-
Here ┌x┐—minimum integer number being no less than x. Number of layers in T-NN constructed by means of the algorithm Neuron2TNN1 is h=┌logN K┐. The total number of weights in T-NN is:
-
- Layer 1 (e.g., layer 1002):
-
- Layers i=2, 3, . . . , h (e.g., layers 1004, 1006,1008, and 1010):
Output value of the T-NN is calculated according the following formula:
y=F(WmWm-1 . . . W2W1x)
Output for the first layer is calculated as an output vector according to the following formula:
Multiplying the obtained vector by the weight matrix of the second layer:
Every subsequent layer outputs a vector with components equal to linear combination of some sub-vector of x.
Finally, the T-NN's output is equal to:
This is the same value as the one calculated in SLP(K,1) for the same input vector x. So output values of SLP(K,1) and constructed T-NN are equal.
Single Layer Perceptron with Several Outputs
Suppose there is a single layer perceptron SLP(K, L) with K inputs and L output neurons, each neuron performing an activation function F. Suppose further U∈RL×K is a weight matrix for SLP(K, L). The following algorithm Layer2TNN1 constructs a T-neural network from neurons TN(N, 1).
Algorithm Layer2TNN1
-
- 1. For every output neuron i=1, . . . , L
- a. Apply the algorithm Neuron2TNN1 to SLPi(K, 1) consisting on K inputs, 1 output neuron and weight vector Uij, j=1, 2, . . . , K. A TNNi is constructed as a result.
- 2. Construct PTNN by composing all TNNi into one neural net:
- a. Concatenate input vectors of all TNNi, so the input of PTNN has L groups of K inputs, with each group being a copy of the SLP(K, L)'s input layer.
- 1. For every output neuron i=1, . . . , L
Output of the PTNN is equal to the SLP(K, L)'s output for the same input vector because output of every pair SLPi(K, 1) and TNNi are equal.
Multilayer PerceptronSuppose a multilayer perceptron (MLP) includes K inputs, S layers and Li calculation neurons in i-th layer, represented as MLP(K, S, L1, . . . LS). Suppose Ui∈RL
The following is an example algorithm to construct a T-neural network from neurons TN(N, 1), according to some implementations.
Algorithm MLP2TNN1
-
- 1. For every layer i=1, . . . , S
- a. Apply the algorithm Layer2TNN1 to SLPi(Li-1, Li) consisting of Li-1 inputs, Li output neurons, and a weight matrix Ui, constructing PTNNi as a result.
- 2. Construct MTNN by stacking all PTNNi into one neural net; output of a TNNi-1 is set as input for TNNi.
- 1. For every layer i=1, . . . , S
Output of the MTNN is equal to the MLP(K, S, L1, . . . LS)'s output for the same input vector because output of every pair SLPi(Li-1, Li) and PTNNi are equal.
Example T-Transformations with Target Neurons with NI Inputs and NO Outputs
In some implementations, the example transformations described herein are performed by the neural network transformation module 226 that transform trained neural networks 220, based on the mathematical formulations 230, the basic function blocks 232, the analog component models 234, and/or the analog design constraints 236, to obtain the transformed neural networks 228.
Example Transformation of Single Layer Perceptron with Several Outputs
Suppose a single layer perceptron SLP(K, L) includes K inputs and L output neurons, each neuron performing an activation function F. Suppose further U∈RL×K is a weight matrix for SLP(K,L). The following algorithm constructs a T-neural network from neurons TN(NI, NO), according to some implementations.
Algorithm Layer2TNNX
-
- 1. Construct a PTNN from SLP(K,L) by using the algorithm Layer2TNN1 (see description above). PTNN has an input layer consisting of L groups of K inputs.
- 2. Compose
-
- subsets from L groups. Each subset contains no more than No groups of input vector copies.
- 3. Replace groups in every subset with one copy of input vector.
- 4. Construct PTNNX by rebuild connections in every subset by making No output connections from every input neuron.
According to some implementations, output of the PTNNX is calculated by means of the same formulas as for PTNN (described above), so the outputs are equal.
Suppose a multilayer perceptron (MLP) includes K inputs, S layers and Li calculation neurons in ith layer, represented as MLP(K, S, L1, . . . LS). Suppose Ui∈RL
-
- 1. For every layer i=1, . . . , S:
- a. Apply the algorithm Layer2TNNX to SLPi(Li-1, Li) consisting on Li-1 inputs, Li output neuron and weight matrix Ui. PTNNXi is constructed as a result.
- 2. Construct MTNNX by stacking all PTNNX, into one neural net:
- a. Output of a TNNXi-1 is set as input for TNNXi.
- 1. For every layer i=1, . . . , S:
According to some implementations. output of the MTNNX is equal to the MLP(K, S, L1, . . . LS)'s output for the same input vector, because output of every pair SLPi(Li-1, Li) and PTNNXi are equal.
Example Transformation of Recurrent Neural NetworkA Recurrent Neural Network (RNN) contains backward connection allowing saving information.
Data processing in an RNN is performed by means of the following formula:
ht=ƒ(W(hh)ht-1+W(hx)xt)
In the equation above, xt is a current input vector, and ht-1 is the RNN's output for the previous input vector xt-1. This expression consists of the several operations: calculation of linear combination for two fully connected layers W(hh)ht-1 and W(hx)xt, element-wise addition, and non-linear function calculation (f). The first and third operations can be implemented by trapezium-based network (one fully connected layer is implemented by pyramid-based network, a special case of trapezium networks). The second operation is a common operation that can be implemented in networks of any structure.
In some implementations, the RNN's layer without recurrent connections is transformed by means of Layer2TNNX algorithm described above. After transformation is completed, recurrent links are added between related neurons. Some implementations use delay blocks described below in reference to
A Long Short-Term Memory (LSTM) neural network is a special case of a RNN. A LSTM network's operations are represented by the following equations:
ft=σ(Wf[ht-1,xt]+bf);
it=σ(Wi[ht-1,xt]+bi);
Dt=tanh(WD[ht-1,xt]+bD);
Ct=(ft×Ct-1+it×Dt);
ot=σ(Wo[ht-1,xt]+bo); and
ht=ot×tanh(Ct).
In the equations above, Wf, Wi, WD, and WO are trainable weight matrices, bf, bi, bD, and bO are trainable biases, xt is a current input vector, ht-1 is an internal state of the LSTM calculated for the previous input vector xt-1, and or is output for the current input vector. In the equations, the subscript t denotes a time instance t, and the subscript t−1 denotes a time instance t−1.
There are several types of operations utilized in these expressions: (i) calculation of linear combination for several fully connected layers, (ii) elementwise addition, (iii) Hadamard product, and (iv) non-linear function calculation (e.g., sigmoid (o) and hyperbolic tangent (tanh)). Some implementations implement the (i) and (iv) operations by a trapezium-based network (one fully connected layer is implemented by a pyramid-based network, a special case of trapezium networks). Some implementations use networks of various structures for the (ii) and (iii) operations which are common operations.
The layer in an LSTM layer without recurrent connections is transformed by using the Layer2TNNX algorithm described above, according to some implementations. After transformation is completed, recurrent links are added between related neurons, according to some implementations.
A Gated Recurrent Unit) (GRU) neural network is a special case of RNN. A RNN's operations are represented by the following expressions:
zt=σ(Wzxt+Uzht-1);
rt=σ(Wrxt+Urht-1);
jt=tanh(Wxt+rt×Uht-1);
ht=zt×ht-1+(1−zt)×jt).
In the equations above, xt is a current input vector, and ht-1 is an output calculated for the previous input vector xt-1.
Operation types used in GRU are the same as the operation types for LSTM networks (described above), so GRU is transformed to trapezium-based networks following the principles described above for LSTM (e.g., using the Layer2TNNX algorithm), according to some implementations.
Example Transformation of Convolutional Neural NetworkIn general, Convolutional Neural Networks (CNN) include several basic operations, such as convolution (a set of linear combinations of image's (or internal map's) fragments with a kernel), activation function, and pooling (e.g., max, mean, etc.). Every calculation neuron in a CNN follows the general processing scheme of a neuron in an MLP: linear combination of some inputs with subsequent calculation of activation function. So a CNN is transformed using the MLP2TNNX algorithm described above for multilayer perceptrons, according to some implementations.
Conv1D is a convolution performed over time coordinate.
In some implementations, convolutional layers are represented by trapezia-like neurons and fully connected layer is represented by cross-bar of resistors. Some implementations use cross-bars, and calculate resistance matrix for the cross-bars.
Example Approximation Algorithm for Single Layer Perceptron with Multiple Outputs
In some implementations, the example transformations described herein are performed by the neural network transformation module 226 that transform trained neural networks 220, and/or the analog neural network optimization module 246, based on the mathematical formulations 230, the basic function blocks 232, the analog component models 234, and/or the analog design constraints 236, to obtain the transformed neural networks 228.
Suppose a single layer perceptron SLP(K, L) includes K inputs and L output neurons, each output neuron performing an activation function F. Suppose further that U∈RL×K is a weight matrix for SLP(K, L). The following is an example for constructing a T-neural network from neurons TN(NI, NO) using an approximation algorithm Layer2TNNX Approx, according to some implementations. The algorithm applies Layer2TNN1 algorithm (described above) at the first stage in order to decrease a number of neurons and connections, and subsequently applies Layer2TNNX to process the input of the decreased size. The outputs of the resulted neural net are calculated using shared weights of the layers constructed by the Layer2TNN1 algorithm. The number of these layers is determined by the value p, a parameter of the algorithm. If p is equal to 0 then Layer2TNNX algorithm is applied only and the transformation is equivalent. If p>0, then p layers have shared weights and the transformation is approximate.
Algorithm Layer2TNNX Approx
-
- 1. Set the parameter p with a value from the set {0, 1, . . . , ┌logN
I K┐−1}. - 2. If p>0 apply the algorithm Layer2TNN1 with neuron TN(NI, 1) to the net SLP(K, L) and construct first p layers of the resulted subnet (PNN). The net PNN has
- 1. Set the parameter p with a value from the set {0, 1, . . . , ┌logN
-
- neurons in the output layer.
- 3. Apply the algorithm Layer2TNNX with a neuron TN(NI, NO) and construct a neural subnet TNN with Np inputs and L outputs.
- 4. Set the weights of the PNN net. The weights of every neuron i of the first layer of the PNN are set according to the rule wik
i (1)=C. Here, C is any constant not equal to zero, ki=(i−1)NI+1, and
-
- for all weights j of this neuron except ki. All other weights of the PNN net are set to 1. wik
i (1) represents a weight for the first layer (as denoted by the superscript (1)) for the connection between the neuron i and the neuron ki in the first layer. - 5. Set the weights of the TNN subnet. The weights of every neuron i of the first layer of the TNN (considering the whole net this is (p+1)th layer) are set according to the equation
- for all weights j of this neuron except ki. All other weights of the PNN net are set to 1. wik
All other weights of the TNN are set to 1.
-
- 6. Set activation functions for all neurons of the last layer of the TNN subnet as F. Activation functions of all other neurons are identity.
Approximation Algorithm for Multilayer Perceptron with Several Outputs
Suppose a multilayer perceptron (MLP) includes K inputs, S layers and Li calculation neurons in i-th layer, represented as MLP(K, S, L1, . . . LS). Suppose further Ui∈RL
-
- 1. For every layer i=1, . . . , S:
- a. Apply the algorithm Layer2TNNX Approx (described above) to SLPi(Li-1, Li) consisting of Li-1 inputs, Li output neuron, and weight matrix Ui. If i=1, then L0=K. Suppose this step constructs PTNNXi as a result.
- 2. Construct a MTNNX (a multilayer perceptron) by stacking all PTNNXi into one neural net, where output of a TNNXi-1 is set as input for TNNXi.
- 1. For every layer i=1, . . . , S:
In some implementations, the example transformations described herein are performed by the neural network transformation module 226 that transform trained neural networks 220, and/or the analog neural network optimization module 246, based on the mathematical formulations 230, the basic function blocks 232, the analog component models 234, and/or the analog design constraints 236, to obtain the transformed neural networks 228.
This section describes example methods of compression of transformed neural networks, according to some implementations. Some implementations compress analog pyramid-like neural networks in order to minimize the number of operational amplifiers and resistors, necessary to realize the analog network on chip. In some implementations, the method of compression of analog neural networks is pruning, similar to pruning in software neural networks. There is nevertheless some peculiarities in compression of pyramid-like analog networks, which are realizable as IC analog chip in hardware. Since the number of elements, such as operational amplifiers and resistors, define the weights in analog based neural networks, it is crucial to minimize the number of operational amplifiers and resistors to be placed on chip. This will also help minimize the power consumption of the chip. Modern neural networks, such as convolutional neural networks, can be compressed 5-200 times without significant loss of the accuracy of the networks. Often, whole blocks in modern neural networks can be pruned without significant loss of accuracy. The transformation of dense neural networks into sparsely connected pyramid or trapezia or cross-bar like neural networks presents opportunities to prune the sparsely connected pyramid or trapezia-like analog networks, which are then represented by operational amplifiers and resistors in analog IC chips. In some implementations, such techniques are applied in addition to conventional neural network compression techniques. In some implementations, the compression techniques are applied based on the specific architecture of the input neural network and/or the transformed neural networks (e.g., pyramids versus trapezia versus cross-bars).
For example, since the networks are realized by means of analog elements, such as operational amplifiers, some implementations determine the current which flows through the operational amplifier when the standard training dataset is presented, and thereby determine if a knot (an operational amplifier) is needed for the whole chip or not. Some implementations analyze the SPICE model of the chip and determine the knots and connections, where no current is flowing and no power is consumed. Some implementations determine the current flow through the analog IC network and thus determine the knots and connections, which are then pruned. Besides, some implementations also remove the connections if the weight of connection is too high, and/or substitute resistor to direct connector if the weight of connection is too low. Some implementations prune the knot if all connections leading to this knot have weights that are lower than a predetermined threshold (e.g., close to 0), deleting the connections where an operational amplifier always provides zero at output, and/or changing an operational amplifier to a linear junction if the amplifier gives linear function without amplification.
Some implementations apply compression techniques specific to pyramid, trapezia, or cross-bar types of neural networks. Some implementations generate pyramids or trapezia with larger amount of inputs (than without the compression), thus minimizing the number of layers in pyramid or trapezia. Some implementations generate a more compact trapezia network by maximizing the number of outputs of each neuron.
Example Generation of Optimal Resistor SetIn some implementations, the example computations described herein are performed by the weight matrix computation or weight quantization module 238 (e.g., using the resistance calculation module 240) that compute the weights 272 for connections of the transformed neural networks, and/or corresponding resistance values 242 for the weights 272.
This section describes an example of generating an optimal resistor set for a trained neural network, according to some implementations. An example method is provided for converting connection weights to resistor nominals for implementing the neural network (sometimes called a NN model) on a microchip with possibly less resistor nominals and possibly higher allowed resistor variance.
Suppose a test set ‘Test’ includes around 10,000 values of input vector (x and y coordinates) with both coordinates varying in the range [0;1], with a step of 0.01. Suppose network NN output for given input X is given by Out=NN(X). Suppose further that input value class is found as follows: Class_nn(X)=NN(X)>0.61 ? 1:0.
The following compares a mathematical network model M with a schematic network model S. The schematic network model includes possible resistor variance of rv and processes the ‘Test’ set, each time producing a different vector of output values S(Test)=Out_s. Output error is defined by the following equation:
Classification error is defined by the following equation:
Some implementations set the desired classification error as no more than 1%.
Example Error AnalysisSuppose another network O produces output values with a constant shift versus relevant M output values, there would be classification error between O and M. To keep the classification error below 1%, this shift should be in the range of [−0.045, 0.040]. Thus, possible output error for S is 45 mV.
Possible weight error is determined by analyzing dependency between weight/bias relative error over the whole network and output error. The charts 1710 and 1720 shown in
A resistor set together with a {R+, R−} pair chosen from this set has a value function over the required weight range [−wlim; wlim] with some degree of resistor error r_err. In some implementations, value function of a resistor set is calculated as follows:
-
- Possible weight options array is calculated together with weight average error dependent on resistor error;
- The weight options in the array is limited to the required weight range [−wlim; wlim];
- Values that are worse than neighboring values in terms of weight error are removed;
- An array of distances between neighboring values is calculated; and
- The value function is a composition of square mean or maximum of the distances array.
Some implementations iteratively search for an optimal resistor set by consecutively adjusting each resistor value in the resistor set on a learning rate value. In some implementations, the learning rate changes over time. In some implementations, an initial resistor set is chosen as uniform (e.g., [1; 1; . . . ; 1]), with minimum and maximum resistor values chosen to be within two orders of magnitude range (e.g., [1;100] or [0.1;10]). Some implementation choose R+=R−. In some implementations, the iterative process converges to a local minimum. In one case, the process resulted in the following set: [0.17, 1.036, 0.238, 0.21, 0.362, 1.473, 0.858, 0.69, 5.138, 1.215, 2.083, 0.275]. This is a locally optimal resistor set of 12 resistors for the weight range [−2; 2] with rmin=0.1 (minimum resistance), rmax=10 (maximum resistance), and r_err=0.001 (an estimated error in the resistance). Some implementations do not use the whole available range [rmin; rmax] for finding a good local optimum. Only part of the available range (e.g., in this case [0.17; 5.13]) is used. The resistor set values are relative, not absolute. Is this case, relative value range of 30 is enough for the resistor set.
In one instance, the following resistor set of length 20 is obtained for abovementioned parameters: [0.300, 0.461, 0.519, 0.566, 0.648, 0.655, 0.689, 0.996, 1.006, 1.048, 1.186, 1.222, 1.261, 1.435, 1.488, 1.524, 1.584, 1.763, 1.896, 2.02]. In this example, the value 1.763 is also the R−=R+ value. This set is subsequently used to produce weights for NN, producing corresponding model S. The model S's mean square output error was 11 mV given the relative resistor error is close to zero, so the set of 20 resistors is more than required. Maximum error over a set of input data was calculated to be 33 mV. In one instance, S, DAC, and ADC converters with 256 levels were analyzed as a separate model, and the result showed 14 mV mean square output error and 49 mV max output error. An output error of 45 mV on NN corresponds to a relative recognition error of 1%. The 45 mV output error value also corresponds to 0.01 relative or 0.01 absolute weight error, which is acceptable. Maximum weight modulus in NN is 1.94. In this way, the optimal (or near optimal) resistor set is determined using the iterative process, based on desired weight range [−wlim; wlim], resistors error (relative), and possible resistors range.
Typically, a very broad resistor set is not very beneficial (e.g., between 1-⅕ orders of magnitude is enough) unless different precision is required within different layers or weight spectrum parts. For example, suppose weights are in the range of [0, 1], but most of the weights are in the range of [0, 0.001], then better precision is needed within that range. In the example described above, given the relative resistor error is close to zero, the set of 20 resistors is more than sufficient for quantizing the NN network, with given precision. In one instance, on a set of resistors [0.300, 0.461, 0.519, 0.566, 0.648, 0.655, 0.689, 0.996, 1.006, 1.048, 1.186, 1.222, 1.261, 1.435, 1.488, 1.524, 1.584, 1.763, 1.896, 2.02] (note values are relative), an average S output error of 11 mV was obtained.
Example Process for Quantization of Resistor ValuesIn some implementations, the example computations described herein are performed by the weight matrix computation or weight quantization module 238 (e.g., using the resistance calculation module 240) that compute the weights 272 for connections of the transformed neural networks, and/or corresponding resistance values 242 for the weights 272.
This section describes an example process for quantizing resistor values corresponding to weights of a trained neural network, according to some implementations. The example process substantially simplifies the process of manufacturing chips using analog hardware components for realizing neural networks. As described above, some implementations use resistors to represent neural network weights and/or biases for operational amplifiers that represent analog neurons. The example process described here specifically reduces the complexity in lithographically fabricating sets of resistors for the chip. With the procedure of quantizing the resistor values, only select values of resistances are needed for chip manufacture. In this way, the example process simplifies the overall process of chip manufacture and enables automatic resistor lithographic mask manufacturing on demand.
The following equations determine the weights, based on resistor values:
-
- Voltage at the output of neuron is determined by the following equation:
-
- The weights of each connection are determined by following equation:
The following example optimization procedure quantizes the values of each resistance and minimize the error of neural network output, according to some implementations:
-
- 1. Obtain a set of connection weights and biases {w1, . . . , wn, b}.
- 2. Obtain possible minimum and maximum resistor values {Rmin, Rmax}. These parameters are determined based on the technology used for manufacturing. Some implementations use TaN or Tellurium high resistivity materials. In some implementations, the minimum value of resistor is determined by minimum square that can be formed lithographically. The maximum value is determined by length, allowable for resistors (e.g., resistors made from TaN or Tellurium) to fit to the desired area, which is in turn determined by the area of an operational amplifier square on lithographic mask. In some implementations, the area of arrays of resistors is smaller than the area of one operational amplifier, since the arrays of resistors are stacked (e.g., one in BEOL, another in FEOL).
- 3. Assume that each resistor has r_err relative tolerance value
- 4. The goal is to select a set of resistor values {R1, . . . , Rn} of given length N within the defined [Rmin; Rmax], based on {w1, . . . , wn, b} values. An example search algorithm is provided below to find sub-optimal {R1, . . . , Rn} set based on particular optimality criteria.
- 5. Another algorithm chooses {Rn, Rp, Rni, Rpi} for a network given that {R1 . . . Rn} is determined.
Some implementations use an iterative approach for resistor set search. Some implementations select an initial (random or uniform) set {R1, . . . , Rn} within the defined range. Some implementations select one of the elements of the resistor set as a R−=R+ value. Some implementations alter each resistor within the set by a current learning rate value until such alterations produce ‘better’ set (according to a value function). This process is repeated for all resistors within the set and with several different learning rate values, until no further improvement is possible.
Some implementations define the value function of a resistor set as follows:
-
- Possible weight options are calculated according to the formula (described above):
-
- Expected error value for each weight option is estimated based on potential resistor relative error r_err determined by IC manufacturing technology.
- Weight options list is limited or restricted to [−wlim; wlim] range
- Some values, which have expected error beyond a high threshold (e.g., 10 times r_err), are removed
- Value function is calculated as a square mean of distance between two neighboring weight options. So, value function is minimal when weight options are distributed uniformly within [−wlim; wlim] range
Suppose the required weight range [−wlim; wlim] for a model is set to [−5; 5], and the other parameters include N=20, r_err=0.10%, rmin=100 KΩ, rmax=5 MΩ. Here, rmin and rmax are minimum and maximum values for resistances, respectively.
In one instance, the following resistor set of length 20 was obtained for abovementioned parameters: [0.300, 0.461, 0.519, 0.566, 0.648, 0.655, 0.689, 0.996, 1.006, 1.048, 1.186, 1.222, 1.261, 1.435, 1.488, 1.524, 1.584, 1.763, 1.896, 2.02] MΩ. R−=R+=1.763 MΩ.
Example {Rn, Rp, Rni, Rpi} Search AlgorithmSome implementations determine Rn and Rp using an iterative algorithm such as the algorithm described above. Some implementations set Rp=Rn (the tasks to determine Rn and Rp are symmetrical—the two quantities typically converge to a similar value). Then for each weight wi, some implementations select a pair of resistances {Rni, Rpi} that minimizes the estimated weight error value:
Some implementations subsequently use the {Rni; Rpi; Rn; Rp} values set to implement neural network schematics. In one instance, the schematics produced mean square output error (sometimes called S mean square output error, described above) of 11 mV and max error of 33 mV over a set of 10,000 uniformly distributed input data samples, according to some implementations. In one instance, S model was analyzed along with digital-to-analog converters (DAC), analog-to-digital converters (ADC), with 256 levels as a separate model. The model produced 14 mV mean square output error and 49 mV max output error on the same data set, according to some implementations. DAC and ADC have levels because they convert analog value to bit value and vice-versa. 8 bits of digital value is equal to 256 levels. Precision cannot be better than 1/256 for 8-bit ADC.
Some implementations calculate the resistance values for analog IC chips, when the weights of connections are known, based on Kirchhoff's circuit laws and basic principles of operational amplifiers (described below in reference to
Some implementations manufacture resistors in a lithography layer where resistors are formed as cylindrical holes in the SiO2 matrix and the resistance value is set by the diameter of hole. Some implementations use amorphous TaN, TiN of CrN or Tellurium as the highly resistive material to make high density resistor arrays. Some ratios of Ta to N Ti to N and Cr to N provide high resistance for making ultra-dense high resistivity elements arrays. For example, for TaN, Ta5N6, Ta3N5, the higher the N ratio to Ta, the higher is the resistivity. Some implementations use Ti2N, TiN, CrN, or Cr5N, and determine the ratios accordingly. TaN deposition is a standard procedure used in chip manufacturing and is available at all major Foundries.
Example Operational AmplifierIn some implementations, operational amplifiers such as the example described above are used as the basic element of integrated circuits for hardware realization of neural networks. In some implementations, the operational amplifiers are of the size of 40 square microns and fabricated according to 45 nm node standard.
In some implementations, activation functions, such as ReLU, Hyperbolic Tangent, and Sigmoid functions are represented by operational amplifiers with modified output cascade. For example, RELU, Sigmoid, or Tangent function is realized as an output cascade of an operational amplifier (sometimes called OpAmp) using corresponding well-known analog schematics, according to some implementations.
In the examples described above and below, in some implementations, the operational amplifiers are substituted by inverters, current mirrors, two-quadrant or four quadrant multipliers, and/or other analog functional blocks, that allow weighted summation operation.
Example Scheme of a LSTM Block-
- a “neuron O” assembled on the operational amplifiers U1 20094 and U2 20100, shown in
FIG. 20A . Resistors R_Wo1 20018, R_Wo2 20016, R_Wo3 20012, R_Wo4 20010, R_Uop1 20014, R_Uom1 20020, Rr 20068 and Rf2 20066 set the weights of connections of the single “neuron O”. The “neuron O” uses a sigmoid (module X1 20078,FIG. 20B ) as a nonlinear function; - a “neuron C” assembled on the operational amplifiers U3 20098 (shown in
FIG. 20C ) and U4 20100 (shown inFIG. 20A ). Resistors R_Wc1 20030, R_Wc2 20028, R_Wc3 20024, R_Wc4 20022, R_Ucp1 20026, R_Ucm1 20032, Rr 20122, and Rf2 20120, set the weights of connections of the “neuron C”. The “neuron C” uses a hyperbolic tangent (module X2 22080,FIG. 2B ) as a nonlinear function; - a “neuron I” assembled on the operational amplifiers U5 20102 and U6 20104, shown in
FIG. 20C . Resistors R_Wi1 20042, R_Wi2 20040, R_Wi3 20036, and R_Wi4 20034, R_Uip1 20038, R_Uim1 20044, Rr 20124, and Rf2 20126 set the weights of connections of the “neuron I”. The “neuron I” uses a sigmoid (module X3 20082) as a nonlinear function; and - a “neuron f” assembled on the operational amplifiers U7 20106 and U8 20108, as shown in
FIG. 20D . Resistors R_Wf1 20054, R_Wf2 20052, R_Wf3 20048, R_Wf4 20046, R_Ufp1 20050, R_Ufm1 20056, Rr 20128 and Rf2 20130 set the weights of connections of the “neuron f”. The “neuron I” uses a sigmoid (module X4 20084) as a nonlinear function.
- a “neuron O” assembled on the operational amplifiers U1 20094 and U2 20100, shown in
The outputs of modules X2 20080 (
Referring to
Referring back to
Similar transformations that occur with the signals include:
-
- negB 21012 and V_one 21020 are input to a multiplexer assembled on NMOS transistors M11 21070, M12 2072, M13 2074, M14 21076, and PMOS transistors M15 2078 and M16 21080. The output of this multiplexer is input to the M5 21058 NMOS transistor (shown in
FIG. 21D ); - V_one 21020 and negB 21012 are input to a multiplexer assembled on PMOS transistors M18 21084, M48 21144, M49 21146, and M50 21148, and NMOS transistors M17 21082, M47 21142. The output of this multiplexer is input to the M9 PMOS transistor 21066 (shown in
FIG. 21D ); - negA 21010 and V_two 21008 are input to a multiplexer assembled on PMOS transistors M52 21152, M54 21156, M55 21158, and M56 21160, and NMOS transistors M51 21150, and M53 21154. The output of this multiplexer is input to the M2 NMOS transistor 21054 (shown in
FIG. 21C ); - negB 21012 and V_one 21020 are input to a multiplexer assembled on NMOS transistors M11 21070, M12 21072, M13 21074, and M14 21076, and PMOS transistors M15 21078, and M16 21080. The output of this multiplexer is input to the M10 NMOS transistor 21068 (shown in
FIG. 21D ); - negB 21012 and negA 21010 are input to a multiplexer assembled on NMOS transistors M35 21118, M36 21120, M37 21122, and M38 21124, and PMOS transistors M39 21126, and M40 21128. The output of this multiplexer is input to the M27 PMOS transistor 21102 (shown in
FIG. 21H ); - V_two 21008 and V_one 21020 are input to a multiplexer assembled on NMOS transistors M41 21130, M42 21132, M43 21134, and M44 21136, and PMOS transistors M45 21138, and M46 21140. The output of this multiplexer is input to the M30 NMOS transistor 21108 (shown in
FIG. 21H ); - V_one 21020 and V_two 21008 are input to a multiplexer assembled on PMOS transistors M58 21162, M60 21166, M61 21168, and M62 21170, and NMOS transistors M57 21160, and M59 21164. The output of this multiplexer is input to the M34 PMOS transistor 21116 (shown in
FIG. 21H ); and - negA 21010 and negB 21012 are input to a multiplexer assembled on PMOS transistors M64 21174, M66 21178, M67 21180, and M68 21182, and NMOS transistors M63 21172, and M65 21176. The output of this multiplexer is input to the PMOS transistor M33 21114 (shown in
FIG. 21H ).
- negB 21012 and V_one 21020 are input to a multiplexer assembled on NMOS transistors M11 21070, M12 2072, M13 2074, M14 21076, and PMOS transistors M15 2078 and M16 21080. The output of this multiplexer is input to the M5 21058 NMOS transistor (shown in
The current mirror (transistors M1 21052, M2 21053, M3 21054, and M4 21056) powers the portion of the four quadrant multiplier circuit shown on the left, made with transistors M5 21058, M6 21060, M7 21062, M8 21064, M9 21066, and M10 21068. Current mirrors (on transistors M25 21098, M26 21100, M27 21102, and M28 21104) power supply of the right portion of the four-quadrant multiplier, made with transistors M29 21106, M30 21108, M31 21110, M32 21112, M33 21114, and M34 21116. The multiplication result is taken from the resistor Ro 21022 enabled in parallel to the transistor M3 21054 and the resistor Ro 21188 enabled in parallel to the transistor M28 21104, supplied to the adder on U3 21044. The output of U3 21044 is supplied to an adder with a gain of 7.1, assembled on U5 21048, the second input of which is compensated by the reference voltage set by resistors R1 21024 and R2 21026 and the buffer U4 21046, as shown in
The sigmoid function is formed by adding the corresponding reference voltages on a differential module assembled on the transistors M1 2266 and M2 2268. A current mirror for a differential stage is assembled with active regulation operational amplifier U3 2254, and the NMOS transistor M3 2270. The signal from the differential stage is removed with the NMOS transistor M2 and resistor R5 2220 is input to the adder U2 2252. The output signal sigm_out 2210 is removed from the U2 adder 2252 output.
The weights of the connections of a single neuron (with two inputs and one output) are set by the resistor ratio: w1=(R feedback/R1+)−(R feedback/R1−); w2=(R feedback/R2+)−(R feedback/R2−); wbias=(R feedback/Rbias+)−(R feedback/Rbias−); w1=(Rp*Kamp/R1+)−(Rn*Kamp/R1−); w2=(Rp*Kamp/R2+)−(Rn*Kamp/R2−); wbias=(R p*K amp/Rbias+)−(Rn*K amp/Rbias−), where K amp=R1ReLU/R2ReLU. R feedback=100 k—used only for calculating w1, w2, wbias. According to some implementations, example values include: R feedback=100 k, Rn=Rp=Rcom=10 k, K amp ReLU=1+90 k/10 k=10, w1=(10 k*10/22.1 k)−(10 k*10/21.5 k)=−0.126276, w2=(10 k*10/75 k)−(10 k*10/71.5 k)=−0.065268, wbias=(10 k*10/71.5 k)−(10 k*10/78.7 k)=0.127953.
The input of the negative link adder of the neuron (M1-M17) is received from the positive link adder of the neuron (M17-M32) through the Rcom resistor.
Some implementations perform a two-stage conversion process for optimizing and/or transforming trained neural networks to analog hardware. A first stage (sometimes called T-transformation or T conversion) converts any neural network, existing in digital form in Keras, Tensor flow, or other library, and/or formulated in any form (e.g., software code, algorithms, diagrams, reduced to written instructions, other program code, or hardware in the loop) into a T-Network (examples of which are described above). Each element has an electronic circuit representation. A second stage converts the T-Network into a behavioral model (Netlist), which can be uploaded to modern IC CAD software packages (e.g., Synopsys, Cadence, or Mentor Graphics). In some implementations, both stages or algorithms can be realized as software packages and the function of conversion can be done automatically.
The techniques described herein are related to the class of automated Integration Circuit (IC) design synthesis algorithms. Digital integrated circuits can be synthesized using Register Transfer Language (RTL) code. For example, RISC-V processor cores or any ARM architectures or RAM memory cells or other digital circuits, can be synthesized. It is not obvious, however, that analog integrated circuits can be translated into a mask set, similar to digital integrated circuits. Typically, analog circuit design is node- and process-specific and the placement of analog elements inside the layout is critical. Therefore, the analog circuit design is implemented manually. But if one analog core element is developed, and the neural network integrated circuit consists of identical analog core elements connected in a certain way according to a connection scheme, the design of an analog integrated circuit can be synthesized using standard core elements, based on the connections between standard cells (e.g., Netlist). Conventional systems (e.g., Syntiant) have tried to automate the process of neural network conversion into electronic circuit design layout. But there are no known algorithms that would allow automatic generation of the IC design layout from an initial mathematical neural network. The techniques described herein can be used to fully automate generation of analog integrated circuit design layout for an initial neural network, regardless of the type of the neural network, including feed forward and recurrent neural networks. The algorithms described herein can be be used to automatically generate IC layout, in combination with any relevant CAD software package (e.g., Synopsys, Mentor Graphics, or Cadence).
As used herein, “T-conversion” is a process of transformation of a mathematically formulated neural network, in any form (e.g., software code or algorithms, diagrams, reduced to written instructions, other program code, or hardware in the loop), into another neural network having a direct representation in IC circuit schematics. This means that the resultant neural network consists of elements having an electronic circuit representation. R-quantization is a process of weight quantization of the initial neural network during T-transformation, and includes substituting abstract weights with resistor values. O-quantization is a process of replacing each ideal operational amplifier with the schematic of a certain operational amplifier from a library. R-randomization is a stochastic modeling process that models neural network output for a given set of resistor values. The resistors have random variation and/or tolerance as defined by a manufacturing process. In some implementations, the process includes randomly choosing resistor values from those allowed by a preset variation interval of resistor values. 0-randomization is a process of randomly choosing the parameters of an operational amplifier from the range allowed by process norm variations (e.g., as set by a fab). An SNM model is a Single Neuron Model in mathematical form and in schematics. The term “FEOL” refers to Front End of Line layers of Integration Circuits, and “BEOL” refers to Back End of Line layers of Integration Circuits. This is illustrated below in
T-conversion includes operations shown in
The selected neural network is analyzed (2704) using an SNM model. This step may include searching for non-linear elements in the neural network, calculating the range of weights for each layer as well as the values of the sum of the weights for each neuron, and/or analyzing the architecture from the point of view of compatibility with T-conversion basic concepts. Based on this analysis, the algorithm determines (2706) if the neural network needs to be prepared for T-transformation. If the neural network needs to be prepared for T-transformation, the algorithm performs (2708) architectural refinement which includes changes of the neural network architecture to better suit T-transformation. Architectural refinement is described in more detail below.
Some implementations retrain (2710) the neural network by weights, including introducing additional regularizers to the network. Regularizers are additions to the general training loss function (e.g., penalties depending on the network weights). The regularizers reduce nominal values of neural network weights and reduce weight sums for each neuron. The method includes completing training with the regularizers on the value of each weight, and/or the sum of the weights of the neuron. An example is the Keras 12 regularizer, which reduces absolute weight values. In some implementations, for each Conv-BatchNorm-ReLU block, a complex custom regularizer is used. The custom regularizer treats each BatchNorm layer as a normalization. It also calculates combined Conv-BatchNorm multipliers (i.e., weights) applied to the neural network signals in its propagation path and reduces these combined weights in absolute value for each neuron.
Some implementations prune (2712) the neural network. Pruning can be software pruning or pruning as described above. Subsequently, the prepared neural network is analyzed (2714) for any remaining steps. If there are remaining preparation steps, the preceding steps are repeated. Next, the method performs (2716) T-transformation, which may include applying batch normalization weights to the weights of the previous layer of any BatchNormalization layer (sometimes called a batchNorm layer or a BN layer). During inference, any BatchNormalization layer essentially works as a linear normalization layer, applying additive and multiplicative coefficients to the signal. These coefficients can be calculated for each neuron based on layer weights for this neuron using the following set of equations:
sigma=math.sqrt(moving_variance+epsilon)
k_mult=gamma/sigma
k_add=beta−moving_mean*k_mult
In the equations above, gamma, beta, moving_mean, and moving_variance are trainable weights of a batchNorm layer, and epsilon is a fixed coefficient of the batchNorm layer. As any composition of linear transformations is a linear transformation, a convolution layer (sometimes called Conv, without activation) followed by a BN layer can be interpreted as a single linear transformation of a neural network signal (i.e., a signal layer of a T-network). In some implementations, the T-Transformation step 2716 also includes translation of the neural network into a directed graph structure made from single neurons and weight connections, and a merge of all layers that do not have an activation function. For example, a superposition of linear transformations is a linear transformation. Therefore, if there are three dense layers without activation, for example, the three dense layers are essentially like one dense layer, but with different weights. There is always activation on dense layers, but there are cases when it is not present on convolutions. Further, suppose a linear transformation is x′=Ax+b, and the subsequent linear transformation is x″=A′+b′=A′ (Ax+b)+b′=(A′A)x+(A′b+b′). The subsequent linear transformation can be treated as a single linear transformation in relation to x with weights defined according to the above formula. To illustrate further, suppose there are two sequential dense layers and there is no activation function between them. Suppose further that the first dense layer is described with a weight matrix W1 and a bias b1, and the second dense layer is described with a weight matrix W2 and a bias b2. Then, both layers together produce an output of Xout=W2(W1−X+b1)+b2=(W2·W1)X+W2·b1+b2 which is a single linear transformation with a weight matrix of W2·W1.
Layers with a ReLU in the original neural network become ReLU1, according to some implementations. To maintain the normal operation of the neural network during this transformation, the passage of signals through the neural network is analyzed and weight correction is performed. When the weights of layer N are divided by a factor, the weights of layer N+1 are multiplied by that factor. Such a correction wave is performed through the entire network until it is possible to achieve complete compliance (e.g., all of the weights are within the physical limits). The signals on layers with unlimited ReLU are scaled so that they do not get out of the physical limiter. To illustrate, suppose possible output values for a particular neuron P with ReLU activation lies in the range [0, N], where N>Vfeed (or 1). In order to keep the signal within the required range of [0, Vfeed] (or [0,1]), some implementations reduce weights and bias of the neuron P by a factor of N/Vfeed as follows:
w′=w*Vfeed/N
b′=b*Vfeed/N
The signal on the next layer is scaled by multiplying all weights values for connections originating from neuron P output, by a factor of N/Vfeed as follows:
w″=w*N/Vfeed
If necessary, some implementations introduce additional intermediate layers that limit the number of input and output links of the neuron. In order to reduce the output links of the neuron, some implementations use output splitting. Suppose a neuron P has K outputs leading to neurons {P1, . . . , Pk} with weights {w1, . . . , wk}. Some implementations add neurons Q1, Q2 and an arbitrary index 1<=q<K, and change neuron connections in the following way: P has two outputs leading to neurons {Q1, Q2} with weights {1,1}; Q1 has q outputs leading to neurons {P1, . . . , Pq} with weights {w1, . . . , wq}; Q2 has k-q outputs leading to neurons {Pq+1, . . . , Pk} with weights {wq+1, . . . , wk}. Input splitting is performed similarly for the inputs to the neural network. In this way, a T-converted neural network is obtained, which is fully equivalent to the initial trained neural network, and the representation is generated in electronic schematics, which can be converted to a behavioral model (e.g., aNetlist).
In some implementations, the conversion is preceded by mathematical modeling, which uses (2728) a numerical model of the operational amplifier, and compares the result of the R-quantized and O-quantized network. In some implementations, the conversion is followed by modeling (2730) the netlist in CAD software to make sure that the conversion did not lead to additional discrepancies between the RO-quantized network and the netlist in CAD software. Part of the netlist modeling in CAD software includes supplying the input in constant voltage (dc) mode with a set of analog values corresponding to a specific sample of the dataset control sample used to evaluate the mathematical neural network, and removing the corresponding output voltages.
The conversion is preceded by mathematical modeling, which uses a behavioral model of an op-amp and compares simulated results of the R-quantized and O-quantized network with a respective initial mathematical model. After the conversion is finished, behavioral models of components in the synthesized netlist are changed for actual EDA-based models of the respective electronic components (i.e., opamps and integrated resistors). Such models are available either from the process vendor (a foundry) or designed in-house for the given fabrication process. The final netlist is characterized, and simulation results are then compared with the results taken from behavioral model simulation and with an initial mathematical model. The result of the multistage conversion process is a netlist based on an actual manufacturing process. The netlist represents a ready-to-manufacture integrated circuit IP-block.
Example PPG Sensor-Based Heart Rate EstimationAn example neural network calculates heart rate based on PPG and accelerometer signals. The neural network includes a convolutional network of 10 layers, which accepts raw PPG and accelerometer signals as inputs. The neural network is trained using LOSO validation and mean average error beats per minute (bpm) as the target. Network weights are regularized. Some of the connections and neurons are pruned. The resulting neural network has accuracy of approximately 4.6 bpm on high-intensity data down to approximately 1.7 bpm on low-intensity data. The neural network is T-transformed using the T-converter software module. Example operations are described above according to some implementations. Subsequently, quantization is performed, so that weights are reduced to component values. The T-converted neural network has approximately 43,000 neurons and approximately 1.2 million connections. Randomized tests are carried out, demonstrating that additional network error caused by T-transform, quantization and manufacturing scatter does not exceed 0.5 bpm. The NASP neural network is converted to Netlist plus a principal component model using the Netlist Generation Module. The Netlist passes the test bench, verifying that it produces similar results (within reasonable calculation error of 1.0*10−6) as a digital model on analog input signals, corresponding to dataset samples. True Netlist can be synthesized when a customer choses the technology node and the process design kit (PDK). The IP block GDSII layout is synthesized from true Netlist using standard CAD software. The Netlist contains descriptions of 2.4 million of resistors in BEOL layers and 43,000 Operational Amplifiers placed in FEOL layers.
Example Speech Key Word SpottingA DS CNN convolutional network NASP IP block synthesis is provided as another example. The DS-CNN for spectrogram accepts 49 by 10 input and includes 10 words. The DS CNN includes 5 convolutional layers, 4 depthwise convolutional layers, an average pooling layer, a fully connected layer, and an output layer that includes Softmax of length 12. The DS-CNN has 94.4% accuracy. T-conversion generates a 12 layer T-Network with 72,000 neurons, 2.5 million connections, weights that are quantized and restricted, and RELU restricted to RELU 6. The T-network is transformed to a functional model (Netlist) based on amplifiers and resistors, including 72,000 operational amplifiers, 1,440,000 transistors, and 5 million resistors. Two resistors correspond to one connection. True Netlist is synthesized after a customer chooses the technology node and PDK. The IP block GDSII layout is synthesized from true Netlist using standard CAD software.
Example Optimizations for Analog Hardware Realization of Neural NetworksThe method also includes transforming (2808) the neural network topology into an equivalent analog network of analog components, including replacing composition or superposition of linear transformations by a single linear transformation. This step reduces the number of neurons, thereby reducing die area, energy consumption, and complexity of the following steps.
Referring next to
sigma=tf.sqrt(bn.moving_variance+bn.epsilon)
k_mult=multiplier=bn.gamma/sigma
k_add=bn.beta−bn.moving_mean*k_mult
In the equations above, k_mult and k_add determine coefficients for the linear transformation X_out=k_mult*X_in +k_add. In the equations above, bn.gamma, bn.beta, bn.moving_mean, and bn.moving_variance are trainable weights of a BatchNormalization layer, and epsilon is a fixed coefficient of the BatchNormalization layer.
Referring next to
In some implementations, transforming the neural network topology into the equivalent analog network includes transforming (2828) layers with ReLU into ReLU1. In some implementations, transforming layers with ReLU into ReLU1 includes maintaining (2830) normal operation of the trained neural network during the transformation by analyzing the passage of signals through the trained neural network and performing weight correction. Weight correction is defined as multiplication of weights and bias (if available) of a neuron by a certain coefficient and division of weights of outgoing connections of this neuron by the same coefficient. Some implementations use weight correction in order to achieve maximum compliance between the original network and the transformed network, where compliance is measured as the average distance between both networks' output at different input signals. Weight correction may be performed layer-wise and/or neuron-wise. When weight correction is performed neuron-wise, it includes adjusting weights and bias of one or more neurons and adjustment of weights of outgoing connections of the one or more neurons. Weight correction may be used to keep signals in the network below a physical limit (because in analog, the system cannot produce any signal above the physical limit). So, when performing weight correction, some implementations first analyze the output range for each neuron on a given set of inputs. If the upper bound of the output range exceeds the physical limit, some implementations perform weight correction. In some implementations, performing weight correction includes: (i) when the weights of a layer N are divided by a factor, adjusting (2832) the weights of layer N+1 by multiplying the weights by that factor; and (ii) repeating (2832) the weight correction for the trained neural network until complete compliance is achieved. This step entails applying layer-wise weight correction to layers or neuron-wise weight correction to neurons until complete compliance is achieved. Compliance refers to a state when output signals for each neuron are below feed voltage for layers with unlimited ReLU activation. Possible neuron outputs are calculated for a wide set of network input data (e.g., 1,000 to 10,000 samples). For neuron-wise weight correction, weights and bias of a neuron are divided by factor, and weights of outgoing connections are multiplied by that factor. In some implementations, performing weight correction includes scaling (2834) signals on layers with unlimited ReLU (i.e., layers that do not have a maximum activation value) so that the signals do not get out of the physical limit described above. In some implementations, transforming the neural network topology to the equivalent analog network includes introducing (2836) additional intermediate layers that limit the number of input or output links of neurons by splitting input or output of the neurons. Compliance is a state and weight correction is a method that may be used to achieve the state. In cases where correction is required, it is performed on pairs of layers until all of the layers' outputs are within the physical limits. Weight correction is applied when an activation function is present. Activation is considered to be ReLU. When it is not ReLU, weight correction in the general case is not possible. When there is no activation between layers, the method includes performing superposition of linear transformations.
In some implementations, the method includes pruning at least some of the connections of the neural network topology. In some implementations, the method further includes quantizing and/or restricting the weights of the neural network topology. In some implementations, the method further includes identifying non-linear elements in the neural network topology and replacing them with linear elements. In some implementations, to enable regularization, the method includes: (i) calculating a range of weights for each layer of the neural network topology and (ii) calculating values for the sum of the weights for each neuron of the neural network topology. In some implementations, the method includes determining compatibility of the neutral network topology for conversion to the equivalent analog network. In some instances, network architecture is not suitable for conversion if the architecture contains known elements which cannot be transformed (e.g., non-linear elements). In such cases, the method includes performing architecture refinement of blocks, which contain such elements, according to some implementations.
Referring back to
The method also includes generating (2812) a schematic model for implementing the equivalent analog network based on the weight matrix, including selecting component values for the analog components.
Example Quantization AlgorithmsT-network R-quantization is a conversion algorithm from a vector of weights {right arrow over (w)} to particular resistor values for each neuron, based on limiting the values to discrete values from a particular set. This pre-defined resistor set is specified by a resistor manufacturer and is characterized by resistance values and tolerance. In some cases, the resistor set is not limited to certain discrete values, but is limited to a given continuous range.
For single neuron schemes, the R-quantization includes solving a system of equations and/or inequalities connecting weights and resistor values. The number of resistor parameters is typically more than twice the number of weights of neural networks, so the system of equations normally has a plurality of solutions. A goal of the R-quantization algorithm (sometimes called RQA) is to select one of the solutions from this plurality that best fits certain optimization criteria. Possible optimization criteria depend on the process limitations described below.
R-quantization error (EQR) is the mean error of a T-network with quantized resistors and perfect operational amplifiers versus a math network on a set of input data. RO-quantization error (EQRO) is the mean error of a T-network with quantized resistors and imperfect operational amplifiers with a particular pre-defined output model versus the math network on the set of input data. RO-quantization R-randomization error (EQRO-RR) is the mean error of a T-network with quantized resistors with random tolerance error and imperfect operational amplifiers with a particular pre-defined output model versus the math network on the set of input data. RO-quantization RO-randomization error (EQRO-RRO) is the mean error of a T-network with quantized resistors with random tolerance error and imperfect operational amplifiers with a particular pre-defined output model and random tolerance errors that affects operational amplifiers' shift value, versus the math network on the set of input data. Quantization is performed independently for each of the components.
RQA is an optimization algorithm that uses optimization criteria, including one or more of the following: (i) energy consumption (tends to maximize resistor values), (ii) die area (tends to minimize resistor values), and (iii) minimizing of the error metrics (tends to minimize negative input relative (to feedback) resistors values).
Experimental Data Comparing R-Quantization AlgorithmsFor this experiment, an optimization criteria of EQRO was chosen with an operational amplifier shift value of 1.0*10−5. Resistor sets of [1, . . . , N] with N=30, 50, and 100 were used for this experiment. The exact scaling coefficient is not important, because in EQRO metrics, there are no absolute resistor values. There are only relative values.
The MNIST dataset is a publicly available database of handwritten digits, with each digit classified as “0”, “1”, “2”, . . . , or “9”. The MNIST dataset was reduced to the classes of “4” and “9”. There were 11791 training samples and 1991 testing samples. Forty convolutional networks of the same structure with random initial parameters were trained for 5 epochs each on this dataset. These networks were then T-transformed, having 13 layers, 20,000 neurons, and 940,000 connections after the transformation.
For each of the four algorithms listed above and for each of the 40 networks, the mean EQRO error over the test samples was calculated and compared with the received EQRO values. The EQR value is given for reference. The values are summarized in the table below:
OP1.1 and OP1.2 are models defining schematic architectures. Example OP1.1 schematics are shown in
The method transforms (2908) the neural network topology into an equivalent analog network of analog components including a plurality of operational amplifiers and a plurality of resistors. Each operational amplifier represents an analog neuron of the equivalent analog network, and each resistor represents a connection between two analog neurons. Transforming the neural network topology includes performing resistor quantization and operational amplifier quantization to obtain a quantized network for the equivalent analog network. Each resistor is assigned a resistance value and each operational amplifier is assigned values for one or more functional parameters (e.g., open-loop gain, input impedance, and output impedance). O-quantization includes selecting an operational amplifier model from a set of predefined models (previously developed in silicon) that best meets optimality criteria and restrictions of a neuron. With operational amplifiers, when there is only one model to choose for each neuron, this step can be implemented using a brute force technique for selecting values of a single parameter. The single parameter is an operational amplifier model itself. Some implementations run simulations with one operational amplifier, then with another operational amplifier, and so on. For R-quantization, on the other hand, a brute-force solution is not possible because there are many inter-dependent parameters. These parameters are neuron resistance values. Their number and meaning are defined by a neuron architecture (e.g., OP1.1 shown in
In some implementations, the quantized network is obtained by analyzing (2910) output tolerance of the neural network using Monte-Carlo simulation where resistors and operational amplifier parameters are considered having stochastic components caused by temperature shift and manufacturing tolerance.
In some implementations, performing resistor quantization includes converting (2912) a vector of weights of the trained neural network to particular resistor values of a single analog neuron. In some implementations, the resistor values are discrete values from a pre-determined resistor set. Each resistor in the resistor set is characterized by a respective resistance value and a respective tolerance value. In some implementations, the resistor values are limited to a continuous range.
In some implementations, performing resistor quantization includes solving (2914) a system of equations and/or inequalities connecting weights of the trained neural network and resistor values. The number of resistors is more than twice the number of weights, and the system of equations has a plurality solutions. In some implementations, solving the system of equations includes selecting (2916) a solution based on one or more optimization criteria. The criteria include (i) energy consumption (tends to maximize resistor values), (ii) die area (tends to minimize resistor values), and (iii) minimization of one or more error metrics (tends to minimize negative input relative (to feedback) resistors values). Because the energy consumed is E=U/R2, maximizing resistor values (R) minimizes energy. A resistor's die area is proportional to its resistance value. Resistors should be placed above operational amplifiers, so they are limited by operational amplifier die area. Therefore, the resistor die area should not exceed the operational amplifier die area. This means that resistance values should be limited. The quantization solves a system of X equations (typically, non-linear equations) considering Y resistance values, where X>Y, and the resistances can have values from a predefined set of discrete values. Some implementations also consider optimality criteria, such as die size, energy consumption, and/or tolerance, which are partially competing objectives. Some implementations reduce the complexity of the task for specific cases using particular schematic options. In some implementations, the one or more optimization criteria include R-quantization error (EQR), which is the mean error of the equivalent analog network with quantized resistors and perfect operational amplifiers versus a math network on a set of input data. Perfect operational amplifiers produce an output voltage of max(0, min(x, Vfeed)), where x is a weighted sum of the inputs and Vfeed is the feed voltage. The math network is the original network, which is being converted to analog hardware. It is a network defined in an ML framework. Input data is a set of tensors of data, such as pictures or sounds in the form of analog signals. In some implementations, the one or more optimization criteria include RO-quantization error (EQRO), which is the mean error of the equivalent analog network with quantized resistors and imperfect operational amplifiers with a particular pre-defined output model versus the math network on the set of input data. Imperfect operational amplifiers have some design flaws (designed in silicon) and produce slightly different output from perfect operational amplifiers. In some implementations, the one or more optimization criteria include RO-quantization R-randomization error (EQRO-RR), which is the mean error of the equivalent analog network with quantized resistors with random tolerance error and imperfect operational amplifiers with a predefined output model versus the math network on the set of input data. When operational amplifiers are designed in silicon, they can be described by a model. U=IR is a resistor model. Similarly, operational amplifiers have their models. The models have many parameters and connect output voltage with input voltages and resistor values. In some implementations, the one or more optimization criteria include RO-quantization RO-randomization error (EQRO-RRO), which is the mean error of a T-network with quantized resistors with random tolerance error and imperfect operational amplifiers with a predetermined output model and random tolerance error. The random tolerance error affects the operational amplifier shift value versus the math network on the set of input data. For each of the four types (EQR, EQRO, EQRO-RR, and EQRO-RRO) described above, the error is a “mean error” of the equivalent analog network versus the original math network. A set of sample input data is selected, and the outputs of the two networks are compared. Some implementations compute the error for more than one set of sample inputs. For example, some implementations create 20, 50, or even 100 sample inputs, compute the outputs from both networks, then compute root-mean-square (RMS) error for all of the sample inputs. Some implementations use Monte-Carlo methods for this modeling.
In some implementations, performing operational amplifier quantization includes (2918) selecting an appropriate operational amplifier model from a set of predetermined operational amplifier models according to a set of predetermined limitations and/or optimality criteria. In some implementations, the set of predetermined limitations and/or optimality criteria includes limitations of operational amplifiers for output currents. In some implementations, the set of predetermined limitations and/or optimality criteria includes neuron or operational amplifier die area limitations or minimization. In some implementations, the set of predetermined limitations and/or optimality criteria includes neuron or operational amplifier energy consumption limitations or minimization. In some implementations, the set of predetermined limitations and/or optimality criteria includes operational amplifier input voltage range limitations. In some implementations, the set of predetermined limitations and/or optimality criteria includes minimization of error metrics for resistor quantization.
Referring back to
Described herein is a universal adaptive interface and host controller to drive analog neuromorphic neural networks, according to some implementations. The adaptability of the interface includes the capability to automatically change the number of inputs, outputs and power control parameters depending on architecture (e.g., the number of inputs, the number of outputs, and the number of layers) of an analog neuromorphic neural network. The interface and/or the host controller may be responsible for (i) the dataflow to the inputs of the analog neural network through a deserializer, and/or (ii) control of output signals of the analog neural network. The output signals are converted into digital form and stored in memory, according to some implementations. The signals pass through a serializer and/or a post-processing module, and are accessible through external digital interfaces, such as a serial peripheral interface (SPI), an inter-integrated circuit (I2C), or a controller area network (CAN), which switch a flag at a general purpose input output (GPIO) block of the interface.
In some implementations, the universal adaptive interface includes a host controller and a number of units that provide capabilities for enabling or disabling layer by layer and/or core configuration, enabling or disabling working mode, output mode, data flow control, boot and program execution, internal data postprocessing, system control and non-standard interfaces, subsystem control, standard external interfaces control, external mode setting, sleep mode module, and/or power management.
An output module 3108 includes one or more analog to digital converters, which digitize the analog outputs from last layers of neurons of the analog neuromorphic neural network 3104 and supply digital values to an on-chip memory 3110 and then to an external interfaces block 3112, which opens data to external circuitry according to a general purpose input output (GPIO) block 3114. In some implementations, there is also an always-on circuitry and housekeeping block 3116, which is responsible for driving external mode settings, a sleep mode module, and a power management module. The on-chip memory 3110 may include both SRAM (with DMA) and NVM.
An example control flow and data flow are described herein, according to some implementations. The digital control module 3106 enables or disables (indicated by the arrow labelled ‘1’ in
The universality of the interface arises from the independence of its circuitry to the type and size of the neural core, the number of layers, the number of inputs and the number of outputs. In some implementations, the deserializer is designed to drive any number of parallel analog inputs within the range of up to 5000 parallel inputs and the output block is designed to drive any number of outputs up to 1024 analog outputs, which are converted from analog to digital signals at the ADC block and then arrive at the serializer. The power control unit is designed to switch on and switch off any of neural core layers, depending on a program running in a digital host processor. The external interfaces block 3112 includes standard digital interfaces as well as a sound DAC, according to some implementations. Thus, the described interface can be adapted to any type of neural network, defined by an architecture of a neural core and is universal for any architecture of neural core. The described interface is adaptive. Depending on the programming of the host processor, the interface can drive neural cores of any size with any number of inputs, outputs and/or layers.
Example tasks of the adaptive universal interface include (i) ADC control, including speed variation and/or disabling/enabling. Sampling frequency may be varied, for example, during different physical activities. The aim is to save power during light activity or no activity. The example tasks also include (ii) layer-by-layer (or part-by-part) enable/disable control. A goal is to make the control block generic and applicable to any neural network design. The example tasks also include (iii) communications with a system host (if there is any) and (iv) working as a system host for standalone operations. This includes enforcing proper startup sequences and booting from an external nonvolatile memory (NVM). The example tasks also include (v) controlling external periphery circuits, like LED drivers or other actuators, (vi) partial reconfiguration of the NN core on the fly, and (vii) telemetry tracking and data storing (e.g., for automotive applications).
In a typical usage scenario, according to some implementations, the core keeps the chip in reset, initiates an interface (e.g., SPI or I2C) and then allows the system host to put the program directly into RAM through DMA. When the program is booted, the chip goes through initialization and starts working. The data is sent to the system host via an interface. In another standalone scenario, the core keeps the chip in reset and boots the program from the external NVM chip (currently on-chip NVM is usually economically inefficient). Subsequently, the chip starts. The data is typically used to generate control signals for actuators (e.g., using GPIO pins).
In some implementations, the universal adaptive interface entails a host processor, which is used for (i) supplying data to the analog neuromorphic core, (ii) extracting data from the analog neuromorphic core and (iii) controlling the whole process of inference of the neuromorphic analog core. The neuromorphic analog cores represent the structure of some neural network and is varied, depending on neural network architecture and size. In some implementations, the host processor controls dataflow into and out of neural core, and/or controls or supplies data to external interfaces, and acquires data from digital or analog input. In some implementations, digital output is SPIO or I2C and is supplied to an external circuit after a flag at a GPIO module is switched. In some implementations, the host processor is one of: RISC-V, ARM, ARC, or 8051. In some implementations, the interface is configured to drive a neural core, representing an arbitrary neural network, not depending on the number of inputs, the number of outputs, and/or the number of layers in the neural network core. In some implementations, the input is a digital or analog audio signal and the output is a digital audio signal. In some implementations, the interface can be adopted to any type and/or size of the neural network core by just changing the program of the host controller. In some implementations, the system includes modules for pre-processing the data before it is input into the neural core and post-processing the data after it is output from the neural core. Some implementations include a programmable power control, realized by a host controller, which switches on and switches off certain layers of the neural network core in order to minimize the IC power consumption. In some implementations, the system includes a deserializer, which is realized as a combination of an analog to digital converter, a first-in first-out (FIFO) buffer, and sample and hold units (e.g., 5000 units), supplying (concurrently) up to 5000 analog inputs to the neural core. Some implementations include circuitry of the interface, where on-chip memory includes both SRAM (with DMA) and NVM used for boot and program execution, and internal data post-processing. Some implementations include circuitry for the interface, where preprocessing is implemented using a direct Fourier transformation and post-processing is implemented using an inverse Fourier transformation.
In some implementations, the number of inputs of the neural network is equal to the number of outputs of the deserialiser. A scalable deserialiser is implemented using a configurable IP block of a deserializer, generally similar to memory compilers. Required parameters of the deserialiser can be set during the chip design stage to minimize overhead, or the deserializer may use a fixed block with known maximum input capacity. In the second case, it is possible to configure such a block during execution. In some implementations, similar configuration is implemented for the output interface of the neural network core. It may include a set of analog-to-digital converters and multiplexers. Various combinations of these parts allow adaptation for any number of neural network outputs. Here again, the required options may be chosen during the chip design stage to minimize overhead, or may be implemented using a single configurable block. For adaptability, the interface is adapted to any type and/or size of the neural network core by just changing the program of the host controller. The interface has a configuration register controlling all sub-blocks, so it is possible to reconfigure the interface block by just changing the data in the configuration register. In some implementations, the layer-by-layer disable control strongly depends on data propagation through the specific neural network. The configuration of enable/disable control is unique for each neural network and is determined through a mix of transistor-level simulations and test chip measurements. The configurability of the interface block may be implemented by storing the proper enable or disable configuration into an on-chip nonvolatile memory during pre-production.
In some implementations, the neural network core keeps the chip in reset, initiates an interface (e.g., SPI or I2C), and then allows the system host to put the program directly into RAM through DMA. When the program is booted, the chip goes through initialization and starts working. The data is sent to the system host via an interface. In some implementations, in another standalone scenario, the core keeps the chip in reset and boots the program from the external NVM chip (on-chip NVM is generally economically inefficient). After that, the chip starts. The data generates control signals for actuators (e.g., using GPIO pins). In any case, the data from sensors can be processed by different means, such as by an algorithm running in software on a microcontroller, by a hardware-implemented algorithm, or by a neural network digitally implemented in FPGA. The device that processes the data may be a system host or a device that is controlled by the system host.
Some implementations enable partial reconfiguration of a neural network core during execution. For example, suppose a neural network core works in two modes—a “low power low precision” mode and a “high power high precision” mode. The latter mode uses the whole structure of the former and some additional circuitry. Therefore, the universal interface can get a control signal from the system host and configure the neural network according to the current need of the system. Such an approach is very important for wearable devices and other battery-powered systems.
An example system can be used to produce a specification for analog neuromorphic computing hardware that includes an adaptive universal interface (e.g., the block 3202 described above in reference to
The system also includes one or more programs stored in the memory. The one or more programs are configured for execution by the one or more processors and include instructions for: (i) receiving an analog neural network specification (e.g., a transformed analog neural network 228); (ii) extracting a plurality of parameter values, from the analog neural network specification, corresponding to parameters of the library routines; and (iii) generating a chip fabrication specification that includes an analog neural network corresponding to the analog neural network specification, the input interface library routine, the power management unit library routine, and the output interface library routine, using the plurality of parameter values for the library routines. Examples of parameters are the number of inputs (e.g., 1 to 10,000 inputs), the number of layers (e.g., 3 to 100), and the number of outputs (e.g., 1 to 100). In some implementations, the output of the system is the specification for a chip and files that realize this specification, such as a netlist, layout abstract, or a full layout of the chip.
In some implementations, the input interface library routine includes a specification for one or more digital to analog converters configured to generate analog input for the analog neural core based on one or more digital signals (e.g., signals from one or more CCD/CMOS image sensors).
In some implementations, the input interface library routine includes specifications for a plurality of devices, including one or more of: samplers, analog-to-digital converters, de-serializers, digital-to-analog converters, FIFO buffers, and hold units. For example, for a sensor analog front end, some implementations take digital signals from a FIFO buffer and then deserialize them via DACs and hold units. When working directly with an analog sensor, some implementations digitize the signal, store it in a FIFO buffer, then do the same as in the first example. Some implementations take samples of input analog signals directly into analog hold units corresponding to successive inputs of a neural network.
In some implementations, the output interface library routine includes a specification for one or more analog to digital converters configured to digitize analog output from the final layers of neurons of the analog neural core. For example, the output interface library routine includes a specification for small array of fast DACs in conjunction with more analog hold units, to save area and power. In this way, each DAC is connected to multiple hold units via a multiplexer.
In some implementations, the input interface library routine and the output interface library routine are configured to interface with the analog neural core (representing an arbitrary neural network), based on the number of inputs (e.g., a dozen to a few thousand), the number of outputs (e.g., a dozen to a few hundred), and the type of the analog neural core.
In some implementations, the power management unit library routine is configured to control power supplied to the layers of the analog neural core based on the number of layers (e.g., between five and a hundred layers) of the analog neural core.
In some implementations, the output interface library routine includes specifications for a variable number of comparators, multiplexers, and analog-to-digital converters (ADCs) with different resolutions. The number of comparators, the number of multiplexers, and the number of ADCs are determined based on devices necessary for proper quantization of outputs of the analog neural core. Proper quantization is characterized by having an acceptable error of the neural network output signal. This value is a parameter of a neural network, and is used to create requirements for the specific interface block.
In some implementations, the input interface library routine and the output interface library routine are further configured to sample signals at a frequency determined based on physical activity levels of a user of the system. In some implementations, the sampling frequency is determined based on the physical activity level (e.g., for running, use higher frequency; for low activity, use lower frequency, and so on), using data from accelerometers and/or PPG sensors, to determine the physical activity level. Some implementations disable some parts of the network and continue running at the same frequency.
In some implementations, the chip fabrication specification further includes specification for a host interface in communications with a host processor (e.g., RISC-V, ARM, ARC, or 8051), which is configured to control the analog neural core (e.g., indirectly influence the analog neural core's working modes based on the analog neural core's output).
In some implementations, the chip fabrication specification includes a specification for a reconfiguration unit, which reconfigures the analog neural core depending on the type of inference application is executing in the analog neural core. For example, for a neural network that recognizes the type of human activity, a portion of the network is always working and provides coarse “light/heavy” recognition. If the activity is light, the rest of the network is not turned on and this saves substantial power. If the activity is heavy, the rest of the network is switched on during the next execution and provides detailed recognition (like “running/crossfit/bike” and so on). The whole network keeps working until the activity goes to “light” again. The interface block executes appropriate layer enable control for this process. In some implementations, execution is controlled to occur once in X seconds when the activity is light and once in Y seconds when the activity is heavy. In some implementations, some neurons have two separate enable signals, one controlled by the layer control, and the second controlled by the reconfiguration unit.
In some implementations, the chip fabrication specification includes a specification for a telemetry unit configured to track performance of the analog neural core. Typical performance metrics include power consumption (tracked via current sensors) and propagation delay (tracked via additional telemetry comparators in the output interface or in some layers). In some implementations, the specification includes a specification for fabricating a chip with a sensor, and/or additional telemetry comparators.
In some implementations, the analog neural core is configured to reset the apparatus and initiate an interface (e.g., a serial peripheral interface (SPI), an inter-integrated circuit (I2C), or a controller area network (CAN)) for a system host to write a program into memory (e.g., a RAM) of the apparatus using direct memory access (DMA) operations. These operations in turn cause the apparatus to perform initialization steps, begin execution of the analog neural core, and send output to the system host.
In some implementations, the analog neural core is configured to reset a chip fabricated using the specification and to read a program into a memory (e.g., a RAM) of the chip from an external non-volatile memory (NVM), which in turn causes the chip to perform initialization steps, begin execution, and send control signals to one or more actuators (e.g., using GPIO pins).
In some implementations, the power management unit is configured to dynamically disable or enable each layer of the analog neural core during signal propagation.
In some implementations, the power management unit is programmed based on transistor-level simulations and/or test chip measurements of the analog neural core (the chip-to-chip parameter mismatch affects propagation delay, so it's possible to trim the timing of enabling and disabling individual layers with respect to this mismatch and save power by minimizing enabled time), and the power management unit is configured to store enable or disable configurations in on-chip nonvolatile memory.
The terminology used in the description of the invention herein is for the purpose of describing particular implementations only and is not intended to be limiting of the invention. As used in the description of the invention and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof.
The foregoing description, for purpose of explanation, has been described with reference to specific implementations. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The implementations were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various implementations with various modifications as are suited to the particular use contemplated.
Claims
1. A method for hardware realization of neural networks, comprising:
- obtaining a neural network topology and weights of a trained neural network;
- transforming the neural network topology to an equivalent analog network of analog components, including replacing composition or superposition of linear transformations by a single linear transformation;
- computing a weight matrix for the equivalent analog network based on the weights of the trained neural network, wherein each element of the weight matrix represents a respective connection between analog components of the equivalent analog network; and
- generating a schematic model for implementing the equivalent analog network based on the weight matrix, including selecting component parameter values for the analog components.
2. The method of claim 1, further comprising:
- prior to transforming the neural network topology to the equivalent analog network: adding regularizers to the neural network topology to reduce nominal values of the weights or to a respective reduce weight sum for each neuron; and retraining the trained neural network to obtain updated weights for the weight matrix.
3. The method of claim 2, wherein the regularizers include a respective predetermined regularizer for each convolution batch normalization ReLU block, and wherein each predetermined regularizer treats each batch normalization layer as a normalization and calculates combined convolution-batch normalization multipliers applied to an input neural network signal in the signal's propagation path, and reduces the absolute value of combined weights for each neuron.
4. The method of claim 1, wherein transforming the neural network topology into the equivalent analog network comprises translating weights of each batch normalization layer to weights of its previous layer.
5. The method of claim 1, wherein transforming the neural network topology into the equivalent analog network comprises merging layers that do not have an activation function.
6. The method of claim 1, wherein transforming the neural network topology into the equivalent analog network comprises transforming a linear transformation followed by another linear transformation into a single linear transformation.
7. The method of claim 1, wherein transforming the neural network topology into the equivalent analog network comprises transforming layers with ReLU into ReLU1.
8. The method of claim 7, wherein transforming layers with ReLU into ReLU1 comprises maintaining normal operation of the trained neural network during the transformation by analyzing a passage of signals through the trained neural network and performing weight correction.
9. The method of claim 8, wherein performing weight correction comprises:
- adjusting weights so as to restrict signals in the trained neural network below a physical limit.
10. The method of claim 8, wherein performing weight correction comprises:
- when weights of a layer N are divided by a factor, adjusting weights of layer N+1 by multiplying the weights by the factor.
11. The method of claim 8, wherein performing weight correction comprises:
- adjusting weights and bias of one or more neurons and adjustment of weights of outgoing connections of the one or more neurons.
12. The method of claim 8, wherein performing weight correction comprises:
- repeating weight correction for the trained neural network until complete compliance is achieved.
13. The method of claim 8, wherein performing weight correction comprises scaling signals on layers with unlimited ReLU so that they do not exceed a physical limitation.
14. The method of claim 1, wherein transforming the neural network topology to the equivalent analog network comprises introducing additional intermediate layers that limit a number of input or output links of neurons by splitting inputs or outputs of the neurons.
15. The method of claim 1, further comprising:
- pruning at least some connections of the neural network topology.
16. The method of claim 1, further comprising:
- quantizing and/or restricting the weights of the neural network topology.
17. The method of claim 1, further comprising:
- identifying non-linear elements in the neural network topology.
18. The method of claim 1, further comprising (i) calculating a respective range of weights for each layer of the neural network topology and (ii) calculating a respective sum of the weights for each neuron of the neural network topology.
19. A system for hardware realization of neural networks, comprising:
- one or more processors; and
- memory;
- wherein the memory stores one or more programs configured for execution by the one or more processors, and the one or more programs comprising instructions for:
- obtaining a neural network topology and weights of a trained neural network;
- transforming the neural network topology to an equivalent analog network of analog components, including replacing composition or superposition of linear transformations by a single linear transformation;
- computing a weight matrix for the equivalent analog network based on the weights of the trained neural network, wherein each element of the weight matrix represents a respective connection between analog components of the equivalent analog network; and
- generating a schematic model for implementing the equivalent analog network based on the weight matrix, including selecting component parameter values for the analog components.
20. A non-transitory computer readable storage medium storing one or more programs configured for execution by a computer system having one or more processors, the one or more programs comprising instructions for:
- obtaining a neural network topology and weights of a trained neural network;
- transforming the neural network topology to an equivalent analog network of analog components, including replacing composition or superposition of linear transformations by a single linear transformation;
- computing a weight matrix for the equivalent analog network based on the weights of the trained neural network, wherein each element of the weight matrix represents a respective connection between analog components of the equivalent analog network; and
- generating a schematic model for implementing the equivalent analog network based on the weight matrix, including selecting component parameter values for the analog components.
Type: Application
Filed: Sep 14, 2023
Publication Date: Jan 4, 2024
Inventors: Nikolai Vladimirovich KOVSHOV (Tbilisi), Dmitry Yulievich GODOVSKIY (Bucharest), Aleksandrs TIMOFEJEVS (Riga), Boris MASLOV (Palmetto, FL)
Application Number: 18/467,644
