SLEW RATE CONTROLLABLE SYSTEM FOR POWERING ELECTRIC MACHINE

Abstract

A slew rate controllable system for powering an electric machine. The system may include a plurality of power transistors operable for converting a direct current (DC) input into an alternating current (AC) output suitable for electrically powering the electric machine. The system may further include a gate drive system operable for controlling a slew rate associated with transitioning the power transistors between the opened and closed states.

Description

INTRODUCTION

The present disclosure relates to systems configured for powering an electric machine, such as but not necessarily limited to a slew rate controllable system configured for managing transitions of power switches operating to provide electrical power to a traction motor of an electric vehicle.

In a power inversion process, pulse width modulation, pulse density modulation, delta-sigma modulation, pulse-frequency modulation, or other application-suitable binary (on/off) switching control signals may be employed to facilitate transitioning switches between different states for purposes of powering an electric machine. The control signals, for example, may alternate a conducting state of the switches to generate electrical power having an AC voltage waveform. Some of the more common switches used in higher power applications, such as those used for electrically powering a traction motor of an electric vehicle, may be voltage and/or current controlled between states. A wide bandgap (WBG), GaN, SiC, and other semiconductors, such as metal oxide field-effect transistor (MOSFET) and the insulated-gate bipolar transistor (IGBT) semiconductors may form a class of switches capable of supporting a wide variety of switching events. The rate, speed, timing, etc. of the switching events, or more specifically the transitioning of the switches between on and off or opened and closed states, may be characterized as a slew rate. Depending on a type of electric machine being powered, such as for example when powering a traction motor used for propelling an electric vehicle, an ability to finely select and control the slew rate may be beneficial in minimizing second order effects, such as overvoltage spikes, electromagnetic interference (EMI) bearing current, voltage overshoot, etc.

SUMMARY

One non-limiting aspect of the present disclosure relates to a slew rate controllable system configured for finely selecting and controlling a slew rate for switches used in powering of an electric machine. The slew rate controllable system may be particularly beneficial in accurately controlling the slew rate of power switches, transistors, etc. used in facilitating powering of a traction motor of the type commonly employed for propelling an electric vehicle. The slew rate controllable system may dynamically adjust and precisely control the slew rates according to a wide variety of operating and performance and considerations to provide differing switching speeds capable of balancing high switching slew rates relative to performance benefits and the operating environment.

One non-limiting aspect of the present disclosure relates to a slew rate controllable system for powering an electric machine. The system may include a plurality of power transistors operable for converting a direct current (DC) input into an alternating current (AC) output suitable for electrically powering the electric machine. The power transistors may be operable between an opened state and a closed state to facilitate generating the AC outputs. The system may further include a gate drive system operable for controlling a slew rate associated with transitioning the power transistors between the opened and closed states. The gate drive system may include a plurality of gate drive circuits individually connected to a gate terminal of a corresponding one of the power transistors.

The gate drive system may include a gate driver operable for providing the gate drive circuits with a control signal suitable for optimizing the slew rate of the power transistor associated therewith.

The control signals may be operable for directing the gate drive circuits to control a gate-source voltage (Vgs) between a gate terminal and a source terminal of the power transistor associated therewith such that the Vgs controls the power transistors between the opened and closed states.

The control signals are operable for directing the gate drive circuits to control a gate current (Ig) to a gate terminal of the power transistor associated therewith such that the Ig controls the power transistors between the opened and closed states.

The slew rate controllable system may include a DC link capacitor connected between the power transistors and a DC source providing the DC input, optionally with the control signals optimizing discharge speed of the DC link capacitor to avoid or minimize voltage overshoot of the power transistors when transitioning between the opened and closed states.

The gate driver may be configured for generating the control signals as a function of one or more of a DC voltage of the DC source, a temperature of the DC link capacitor, a current of one or more of the AC outputs and a junction temperature, a maximum discharge time, a drain-source voltage (Vds), a voltage threshold (Vth) of one or more of the power transistors.

The gate drive circuits may include an upper drive switch, an upper resistor, a lower resistor and a lower switch, the upper resistor and the lower resistor connecting in series between the upper drive switch and the lower driver switch, optionally with the gate terminal associated therewith connecting between a lower side of the upper resistor and an upper side of the lower resistor.

The gate drive system may include an upper voltage source and a lower voltage source for each of the gate drive circuits, optionally with the upper voltage source connected to the upper switch and the lower voltage source connected to the lower switch associated therewith.

The gate drive circuits provide a gate voltage to the gate terminal associated therewith, optionally the gate voltage being proportional to a voltage difference between the upper and lower voltage sources and resistances of the upper and lower resistors.

The control signals may be configured to selectively control the upper and lower switches between opened and closed states to set the gate voltages and thereby the slew rate of the power transistor associated therewith.

The control signals may be pulse width modulated (PWM) signals operable between a high voltage and a low voltage, optionally the high voltage transitioning the upper or lower switch in receipt thereof to the opened state and the low voltage transitioning the upper or lower switch in receipt thereof to the closed state.

The gate driver may selectively vary a duty cycle for the PWM signals to control the slew rate of the power transistor associated therewith.

The gate drive circuits may include an upper voltage source, a lower voltage source, an upper switch, a lower switch and an upper resistor, optionally with the upper switch connecting in series with the upper voltage source and to an upper side of the upper resistor, the lower switching connecting in series with the lower voltage source and a lower side of the upper resistor, the gate terminal associated therewith connecting to the lower side of the upper resistor.

The gate drive circuits may include an upper voltage source, a lower voltage source, an upper switch, a lower switch and a lower resistor, optionally with the upper switch connecting in series with the upper voltage source and to an upper side of the lower resistor, the lower switching connecting in series with the lower voltage source and a lower side of the lower resistor, the gate terminal associated therewith connecting to the upper side of the lower resistor.

One non-limiting aspect of the present disclosure relates to a slew rate controllable system for powering a traction motor of a vehicle. The system may include a plurality of power switches operable for converting a direct current (DC) input into an alternating current (AC) output suitable for electrically powering the traction motor. The power switches may be operable between an opened state and a closed state to facilitate generating the AC outputs. The system may further include a gate drive system operable for controlling a slew rate associated with transitioning the power switches between the opened and closed states, optionally with a plurality of gate drive circuits individually connected to a gate terminal of a corresponding one of the power switches and operable for controlling a gate-source voltage (Vgs) between a gate terminal and a source terminal of the power switch associated therewith, with the Vgs controlling the power switches between the opened and closed states.

The gate drive circuits may include an upper voltage source, a lower voltage source, an upper switch, an upper resistor and a lower resistor, the upper switch connecting in series with the upper voltage source, the upper resistor, the lower resistor, and the lower voltage source, optionally with the gate terminal associated therewith connected between a lower side of the upper resistor and an upper side of the lower resistor.

The gate drive system may be configured for generating control signals to set the Vgs of each gate drive circuit by correspondingly controlling the upper and lower switches between opened and closed states.

The gate drive system may be configured to determine the control signals as a function of one or more of a DC voltage of the DC input, a temperature of a DC link capacitor connected across the DC source, a current of one or more of the AC outputs and a junction temperature, a maximum discharge time, a drain-source voltage (Vds) or a voltage threshold (Vth) of one or more of the power switches.

One non-limiting aspect of the present disclosure relates to a slew rate controllable system for powering a traction motor of a vehicle. The system may include a plurality of power switches operable for converting a direct current (DC) input into an alternating current (AC) output suitable for electrically powering the traction motor. The power switches may be operable between an opened state and a closed state to facilitate generating the AC outputs. The system may include a gate drive system operable for controlling a slew rate associated with transitioning the power switches between the opened and closed states, optionally with a plurality of gate drive circuits individually connected to a gate terminal of a corresponding one of the power switches, the gate drive circuits being operable for controlling a gate current (Ig) to a gate terminal of the power switch associated therewith, with the Ig controlling the power switches between the opened and closed states.

The slew rate controllable system may include a DC link capacitor connected between the power switches and a DC source providing the DC input such that the gate drive system is operable for controlling the slew rates of the power switches to optimize discharge speed of the DC link capacitor to avoid or minimize voltage overshoot when transitioning between the opened and closed states.

These features and advantages, along with other features and advantages of the present teachings, may be readily apparent from the following detailed description of the modes for carrying out the present teachings when taken in connection with the accompanying drawings. It should be understood that even though the following figures and embodiments may be separately described, single features thereof may be combined to additional embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which may be incorporated into and constitute a part of this specification, illustrate implementations of the disclosure and together with the description, serve to explain the principles of the disclosure.

FIG. 1 illustrates a partial schematic view of a slew rate controllable system in accordance with one non-limiting aspect of the present disclosure.

FIG. 2 illustrates a partial schematic view of a gate drive circuit in accordance with one non-limiting aspect of the present disclosure.

FIG. 3 illustrates a graph controlled slew rates in accordance with one non-limiting aspect of the present disclosure.

FIG. 4 illustrates a partial schematic view of one of the gate drive circuits omitting the lower resistor in accordance with one non-limiting aspect of the present disclosure.

FIG. 5 illustrates a partial schematic view of one of the gate drive circuits omitting the upper resistor in accordance with one non-limiting aspect of the present disclosure.

DETAILED DESCRIPTION

As required, detailed embodiments of the present disclosure may be disclosed herein; however, it may be understood that the disclosed embodiments may be merely exemplary of the disclosure that may be embodied in various and alternative forms. The figures may not be necessarily to scale; some features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein may need not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present disclosure.

FIG. 1 illustrates a partial schematic view of a slew rate controllable system 10 in accordance with one non-limiting aspect of the present disclosure. The system 10 may include a gate drive system 12 operable for powering an electric machine 14, which for exemplary purposes is predominantly described as an electric motor 14, typically referred to as a traction motor 14. The electric motor 14 may be of the type employed within a vehicle, such as an electric vehicle, to provide mechanical, tractive force operable for propelling the vehicle or otherwise performing work. As described in greater detail below, the gate drive system 12 may be operable for finely selecting and controlling a slew rate for a plurality of power switches, transistors, etc. S1, S2, . . . S6 used as part of a power inverter module (PIM) 16 to facilitate powering the electric machine 14. The system 12 may dynamically adjust and precisely control the slew rates according to a wide variety of operating and performance considerations to provide differing switching speeds capable of balancing high switching slew rates relative to performance benefits and the operating environment. While predominately described with respect to selectively controlling slew rates for switches S1, S2, . . . S6 used in an electric vehicle, one skilled in the art would readily recognize the capabilities of the system 12 being advantageous in facilitating powering other types of electric machines 14 that would similarly benefit from minimizing second order effects, such as overvoltage spikes, electromagnetic interference (EMI) bearing current, voltage overshoot, etc.

The vehicle may include a rechargeable energy storage system (RESS) 20 for storing and supplying electrical power for various systems included onboard the vehicle. The RESS 20 may be a battery or other energy storage device capable of selectively supplying electrical power to and receiving electrical power from the electric machine 14 via the PIM 16. When powering the electric machine 14, the RESS 20 may be configured as a source for providing a direct current (DC) input 22 to the PIM 16. A DC link capacitor 24 may be disposed therebetween to smooth, filter, and otherwise process the DC input 22 for use with the PIM 16. The PIM 16 is shown to include six power transistors/switches S1, S2, . . . S6, each having a gate terminal G, a drain terminal D, and a source terminal S. The gate terminal G of each switch S1, S2, . . . S6 may each be separately and independently connected to one of a plurality of gate drive circuits 26. The switches S1, S2, . . . S6 may corresponding with a broad range of switches S1, S2, . . . S6, including wide bandgap (WBG), GaN, SiC, and other similar semiconductors, such as metal oxide field-effect transistor (MOSFET) and the insulated-gate bipolar transistor (IGBT) semiconductors. The gate drive system 12 may include a gate controller 30 operable for individually and specifically controlling the gate drive circuits 26 to control a rate, speed, timing, etc. of switching events for the switches S1, S2, . . . S6, i.e., to control transitioning of the switches S1, S2, . . . S6 between on and off or opened and closed states. The transitioning of the switches S1, S2, . . . S6 between states may be characterized as a slew rate, with the gate drive circuits 26 being operable to individually select the slew rate for each of the switches S1, S2, . . . S6 according to corresponding control signals 32 provided from the gate controller 30. One non-limiting aspect of the present disclosure contemplates the gate drive circuits 26 being operable for providing a gate voltage and/or a gate current to the gate terminal G associated therewith, with the corresponding gate voltage or gate current being operable to transition the associate switch S1, S2, . . . S6 between opened and closed states, i.e., to control whether the corresponding switch S1, S2, . . . S6 is active or inactive.

The gate controller 30 may include a gate driver 34 configured for individually providing the control signals 32 to each of the gate drive circuits 26. The gate driver 34 may be used in this manner to facilitate switching events for the switches S1, S2, . . . S6 whereby the DC input 22 may be converted to an alternating current (AC) output 38. The AC output 38 may be generated in the illustrated manner to provide a polyphase output having a plurality of AC signals 40, 42, 44 suitable for use in powering the electric machine 14, which are shown for non-limiting purposes to correspond with a three-phase implementation where a three-phase AC output 38 is provided to an AC bus or windings of the electric machine 14, such as via a corresponding input terminal for the associated AC input. As noted above, the use of the gate drive system 12 to facilitate a controllable slew rate based methodology for controlling switching events, and thereby conversion of a DC input 22 to AC outputs 38 suitable for powering the electric machine 14 is presented for non-limiting purposes as the present disclosure fully contemplates the gate drive system 12 being operable in other environments and for other purposes. The present disclosure, as such, fully contemplates use of the gate drive system 12 to control slew rates for switches S1, S2, . . . S6 or other devices in addition to the illustrated use case where the switches S1, S2, . . . S6 may be configured to operate as a unidirectional or bidirectional DC/AC converter.

The gate controller 30 may include a non-transitory computer-readable storage medium having a plurality of non-transitory instructions stored thereon, which when executed with an associated one or more processors, may be operable in accordance with the present disclosure to facilitate generating the control signals 32 in a manner that provides a desirable slew rate while also managing the AC outputs needed for proper powering of the electric machine 14. While not shown in individual detail, a plurality of sensors or other features may be employed to facilitate measuring or otherwise determining a DC voltage of the DC source 20, a temperature of the DC link capacitor 24, a current of one or more of the AC outputs 38, and a junction temperature, a maximum discharge time, a drain-source voltage (Vds), a voltage threshold (Vth) of one or more of the switches/power transistors S1, S2, . . . S6. The gate controller 30 may process the sensor measurements, metrics, etc. to determine a desirable slew rate for each of the switches S1, S2, . . . S6, which may include selecting the control signals 32 to optimize a discharge speed of the DC link capacitor 24 to avoid or minimize voltage overshoot for the switches S1, S2, . . . S6 when transitioning between the opened and closed states. The gate controller 30 may be used in this manner to change slew rates of the switches S1, S2, . . . S6 in real-time, within and between switching events, and optionally in an isolated manner to alter slew rates to be selected based upon operating conditions, desired performance, etc.

FIG. 2 illustrate a partial schematic view of one of the gate drive circuits 26 in accordance with one non-limiting aspect of the present disclosure. While the connection would be repeated separately for each switch S1, S2, . . . S6, the gate drive circuit 26 is shown for exemplary purpose as connected to a gate terminal G of the switch S1. The gate drive circuit 26 is shown in this manner as connectable to the gate terminal G due to the switch S1 being configured as a voltage and/or current controlled type of switch S1 whereby a gate voltage and/or a gate current provided to the gate terminal G may be used to transition the switch S1 between opened and closed states, i.e., to control switching events. In the event the switch S1 employed an alternative configuration, the gate drive circuit 26 may be similarly adapted to provide voltage and/or current to the corresponding terminal. The gate drive circuit 26 may include an upper gate switch 46, an upper resistor 48, a lower resistor 50, and a lower gate switch 52, with the upper gate switch 46 being driven with an upper voltage source 58 and the lower gate switch 52 being driven with a lower voltage source 60. The upper gate switch 46 is shown to be connected in series with the upper voltage source 58, the upper resistor 48, the lower resistor 50, and the lower voltage source 60, with the upper gate switch 46 connected between the upper voltage source 58 and an upper side of the upper resistor 48, the gate terminal G connected between a lower side of the upper resistor 48 and an upper side of the lower resistor the upper side of the lower resistor 50 connected to the lower side of the upper resistor 48, and the lower gate switch 52 connected between the lower voltage source 60 and a lower side of the lower resistor 50.

The gate driver 34 may be configured to generate the control signals 32 with separate control signals 62, 64 suitable for selectively opening and closing the upper and lower gate switches 46, 52, and thereby, controlling the gate voltage and/or current provided to the gate terminal G. The control signals 62, 64 may correspond with pulse width modulated (PWM) signals operable between a high voltage H and a low voltage L to correspondingly control the upper and lower gate switches 46, 52 to a closed state and an opened state. A duty cycle of the control signals 32 may be varied to finely adjust the gate voltage and/or current at precise levels depending on the desired slew rate, e.g., to facilitate adjusting the slew rate in real-time according to desired operation of the electric machine 14. The PWM duty cycle control may be used to change the output current in and out of the switch's gate G (capacitor). The fastest gate speed and slew rates may be preferred for switching due to lag and energy consideration. A method that controls the PWM duty cycle may be based upon the DC bus voltage and current to allow optimal efficiency and reliability. For 400-800V system 12, for example, the present disclosure may be used to adapt the PIM 16 for each bus. In the illustrated configuration, the control signals 62, 64 may be operable for directing the gate drive circuits 26 to control a gate-source voltage (Vgs) between the gate terminal G and the source terminal of the switch S1, with the Vgs controlling the power transistors between the opened and closed states, and/or the control signals 62, 64 may be operable for directing the gate drive circuits 26 to control a gate current (Ig) to the gate terminal G, with the Ig controlling the power transistors between the opened and closed states. The Vgs and Ig provided to the gate terminal G may be proportional to a voltage difference between the upper and lower voltage sources 58, 60 and resistances of the upper and lower resistors 48, 50.

The gate driver 34 may be configured for providing the upper and lower gate switches 46, 52 differing control signals 32, such as in illustrated manner whereby the control signals 32 may have differing duty cycles. This capability for individually varying the duty cycle or other aspects of the control signals 32 used to transition the upper and lower gate switches 46, 52 between states may be beneficial in enabling the gate controller 30 to control Vgs and/or Ig with a very fine and precise level of granularity, with the resulting voltage and current being set according to the upper and lower voltage sources 58, 60 and resistivity of the upper or lower resistors 48, 50. The gate controller 30 may optionally control the voltages provided with each of the upper and lower voltage sources 58, 60 to further enhance its capabilities for finely selecting the voltage and/or the current being provided to the gate terminal G. In some circumstances, for example, the control signals 32 may be used to selectively open or deactivate either one of the upper and lower gate switches 46, 52, optionally in concert with varying the voltages of the upper and lower voltage sources 58, 60, so as to thereby even further add to the specificity in selecting and achieving the desired slew rate.

FIG. 3 illustrates a graph 70 for a method of controlling slew rate in accordance with one non-limiting aspect of the present disclosure. The graph 70 is shown to include a vertical axis 72 for voltage and current and a horizontal axis 74 for time. A first waveform 78 represents voltage between the drain and source terminals (Vds), a second waveform 80 represents current through the drain terminal (Id), a third waveform 82 represents Vgs, and a fourth waveform 84 represents Ig. The graph 70 illustrates an exemplary scenario whereby the slew rate of the switch S1, i.e., dV/dt and/or dI/dt, may be selectively controlled according to transitional properties of the switch S1. The period occurring prior to time T0 may correspond with the switch S1 being off or an active whereafter at time T0 the gate drive circuit 26 begins powering the gate terminal G at an initial slew rate. From time T0 to time T1 the initial slew rate may be maintained while Id increases. At approximately time T1, or slightly thereafter as the slope of Vgs lessens and/or as Vds drops, the D drive circuit may begin powering the gate terminal G at an intermediary slew rate, which may be useful in controlling a slope or a rate at which Vds correspondingly decreases. At approximately time T2, or once Vds reaches or approaches its minimum, a final or greater slew may be implemented. The capability to selectively control Vgs and/or Ig during transitioning of the switch S1 may be beneficial in maximizing performance, or more particular the slew rate, as the switch S1 progresses through various states associated with transitioning from an open state to a closed state. The method may proceed in this manner whereby the slew rate for the drive circuits 26 and the attendant transitioning of the connected to switches S1, S2, . . . S6 may be implemented to control the DC to AC conversion needed for powering the electric machine 14.

FIG. 4 illustrates a partial schematic view of one of the gate drive circuits 26 omitting the lower resistor 50 in accordance with one non-limiting aspect of the present disclosure. FIG. 5 illustrates a partial schematic view of one of the gate drive circuits 26 omitting the upper resistor 48 in accordance with one non-limiting aspect of the present disclosure. These alternative configurations for the gate drive circuits 26 may be illustrative of capabilities for the present disclosure to minimize or reduce the quantity of circuit components while still maintaining desirable levels of slew rate control. While not shown, the present disclosure additionally contemplates similarly omitting the upper and/or lower switches 46, 52. Each of the drive circuits 26 shown in FIGS. 2, 4, and/or 5 may be simultaneously employed, e.g., some of the switches S1, S2, . . . S6 may be connected to one type of drive circuit 26 while one or more the other switches S1, S2, . . . S6 are connected to drive circuits 26 having a differing configuration. This capability may further enhance the beneficial control of slew rates in the manner contemplated herein.

As supported above, the present disclosure relates to a system and method to achieve real-time slew rate (SR) control of power transistors for inverters and converters. It may include minimal amounts of hardware as a voltage/current source and a low-voltage switch, with pulse modulation to control the gate current to realize numerous slew rates. This may equivalently transform the gate drive circuit into a charge pump for the gate capacitor, enabling advantageous methods of control through variable-speed gate drive circuits allowing fine tuning of switching performance to optimize between loss, overshoot, EMI, and bearing current. In this manner, the gate drive circuits may be operable for turning on/off the power switches to converter electrical power between DC and AC, optionally with faster switching, minimal switching loss and improved max power capability, thereby limiting the effects of electrical stress on power switches, ringing, conductive and radiated EMI, and motor terminal voltage overshoot (PDIV) and bearing current. The gate drive system may include the following design features: pulse modulation control to change transistor switching slew rates in real-time, and between and within the switching events; applicability for voltage-source and current-source based or hybrid gate drives; feedforward control using look up tables (LUTs) to alter slew rate based upon operating conditions, i.e. Vdc, current, Vth, and junction temperature; feedback control based upon operation conditions, transistor signal sensing, and part-to-part variation and degradation; tune pulse modulation control at max junction temperature for on transient, and at min junction temperature for off transient; slew rate control to compensate for transistor/switch part-to-part variations, i.e. Vth, gate resistor, stray inductance; class-D topology for the pulse-modulation based gate drive system; modulation control to control slew rate to realize capacitor discharge while managing the I/V overshoots; slew rate control for switching ON/OFF solid-state relay (SSR)/E-fuse to manage the I/V overshoots and protect cap and battery; slew rate control to increase loss for BEV-HEAT and reduce soft turn-off time when switch short circuit; control to regulate dI/dt to prevent secondary effects of changing dV/dt; make EMI frequency feature constant; and/or high-voltage discharge by keeping one side of switches on and PWM the other side of switches on the side (high-side or low-side) with the PWM-based slew rate control to manage voltage overshoot.

The terms “comprising”, “including”, and “having” are inclusive and therefore specify the presence of stated features, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, or components. Orders of steps, processes, and operations may be altered when possible, and additional or alternative steps may be employed. As used in this specification, the term “or” includes any one and all combinations of the associated listed items. The term “any of” is understood to include any possible combination of referenced items, including “any one of” the referenced items. “A”, “an”, “the”, “at least one”, and “one or more” are used interchangeably to indicate that at least one of the items is present. A plurality of such items may be present unless the context clearly indicates otherwise. All values of parameters (e.g., of quantities or conditions), unless otherwise indicated expressly or clearly in view of the context, including the appended claims, are to be understood as being modified in all instances by the term “about” whether or not “about” actually appears before the value. A component that is “configured to” perform a specified function is capable of performing the specified function without alteration, rather than merely having potential to perform the specified function after further modification. In other words, the described hardware, when expressly configured to perform the specified function, is specifically selected, created, implemented, utilized, programmed, and/or designed for the purpose of performing the specified function.

While various embodiments have been described, the description is intended to be exemplary, rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of the embodiments. Any feature of any embodiment may be used in combination with or substituted for any other feature or element in any other embodiment unless specifically restricted. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Also, various modifications and changes may be made within the scope of the attached claims. Although several modes for carrying out the many aspects of the present teachings have been described in detail, those familiar with the art to which these teachings relate will recognize various alternative aspects for practicing the present teachings that are within the scope of the appended claims. It is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and exemplary of the entire range of alternative embodiments that an ordinarily skilled artisan would recognize as implied by, structurally and/or functionally equivalent to, or otherwise rendered obvious based upon the included content, and not as limited solely to those explicitly depicted and/or described embodiments.

Claims

1. A slew rate controllable system for powering an electric machine, comprising:

a plurality of power transistors operable for converting a direct current (DC) input into an alternating current (AC) output suitable for electrically powering the electric machine, the power transistors operable between an opened state and a closed state to facilitate generating the AC output; and

a gate drive system operable for controlling a slew rate associated with transitioning the power transistors between the opened and closed states, the gate drive system including a plurality of gate drive circuits individually connected to a gate terminal of a corresponding one of the power transistors.

2. The slew rate controllable system according to claim 1, wherein:

the gate drive system includes a gate driver operable for providing the gate drive circuits with a control signal suitable for optimizing the slew rate and controlling the power switches to generate the AC output.

3. The slew rate controllable system according to claim 2, wherein:

the control signals are operable for directing the gate drive circuits to control a gate-source voltage (Vgs) between a gate terminal and a source terminal of the power transistor associated therewith, the Vgs controlling the power transistors between the opened and closed states.

4. The slew rate controllable system according to claim 2, wherein:

the control signals are operable for directing the gate drive circuits to control a gate current (Ig) to a gate terminal of the power transistor associated therewith, the Ig controlling the power transistors between the opened and closed states.

5. The slew rate controllable system according to claim 2, further comprising:

a DC link capacitor connected between the power transistors and a DC source providing the DC input, the control signals optimizing discharge speed of the DC link capacitor to avoid or minimize voltage overshoot of the power transistors when transitioning between the opened and closed states.

6. The slew rate controllable system according to claim 5, wherein:

the gate driver is configured for generating the control signals as a function of one or more of a DC voltage of the DC source, a temperature of the DC link capacitor, a current of one or more of the AC output and a junction temperature, a maximum discharge time, a drain-source voltage (Vds), a voltage threshold (Vth) of one or more of the power transistors.

7. The slew rate controllable system according to claim 2, wherein:

the gate drive circuits include an upper drive switch, an upper resistor, a lower resistor and a lower switch, the upper resistor and the lower resistor connecting in series between the upper drive switch and the lower driver switch, with the gate terminal associated therewith connecting between a lower side of the upper resistor and an upper side of the lower resistor.

8. The slew rate controllable system according to claim 7, wherein:

the gate drive system includes an upper voltage source and a lower voltage source for each of the gate drive circuits, with the upper voltage source connected to the upper switch and the lower voltage source connected to the lower switch associated therewith.

9. The slew rate controllable system according to claim 8, wherein:

the gate drive circuits provide a gate voltage to the gate terminal associated therewith, the gate voltage being proportional to a voltage difference between the upper and lower voltage sources and resistances of the upper and lower resistors.

10. The slew rate controllable system according to claim 9, wherein:

the control signals are configured to selectively control the upper and lower switches between opened and closed states to set the gate voltages and thereby the slew rate of the power transistor associated therewith.

11. The slew rate controllable system according to claim 10, wherein:

the control signals are pulse width modulated (PWM) signals operable between a high voltage and a low voltage, the high voltage transitioning the upper or lower switch in receipt thereof to the opened state and the low voltage transitioning the upper or lower switch in receipt thereof to the closed state.

12. The slew rate controllable system according to claim 11, wherein:

the gate driver selectively varies a duty cycle for the PWM signals to control the slew rate of the power transistor associated therewith.

13. The slew rate controllable system according to claim 2, wherein:

the gate drive circuits includes an upper voltage source, a lower voltage source, an upper switch, a lower switch and an upper resistor, the upper switch connecting in series with the upper voltage source and to an upper side of the upper resistor, the lower switching connecting in series with the lower voltage source and a lower side of the upper resistor, the gate terminal associated therewith connecting to the lower side of he upper resistor.

14. The slew rate controllable system according to claim 2, wherein:

the gate drive circuits includes an upper voltage source, a lower voltage source, an upper switch, a lower switch and a lower resistor, the upper switch connecting in series with the upper voltage source and to an upper side of the lower resistor, the lower switching connecting in series with the lower voltage source and a lower side of the lower resistor, the gate terminal associated therewith connecting to the upper side of the lower resistor.

15. A slew rate controllable system for powering a traction motor of a vehicle, comprising:

a plurality of power switches operable for converting a direct current (DC) input into an alternating current (AC) output suitable for electrically powering the traction motor, the power switches operable between an opened state and a closed state to facilitate generating the AC outputs; and

a gate drive system operable for controlling a slew rate associated with transitioning the power switches between the opened and closed states, the gate drive system including a plurality of gate drive circuits individually connected to a gate terminal of a corresponding one of the power switches, the gate drive circuits being operable for controlling a gate-source voltage (Vgs) between a gate terminal and a source terminal of the power switch associated therewith, the Vgs controlling the power switches between the opened and closed states.

16. The slew rate controllable system according to claim 15, wherein:

the gate drive circuits include an upper voltage source, a lower voltage source, an upper switch, an upper resistor and a lower resistor, the upper switch connecting in series with the upper voltage source, the upper resistor, the lower resistor, and the lower voltage source, with the gate terminal associated therewith connected between a lower side of the upper resistor and an upper side of the lower resistor.

17. The slew rate controllable system according to claim 16, wherein:

the gate drive system is configured for generating control signals to set the Vgs of each gate drive circuit by correspondingly controlling the upper and lower switches between opened and closed states.

18. The slew rate controllable system according to claim 17, wherein:

the gate drive system is configured to determine the control signals as a function of one or more of a DC voltage of the DC input, a temperature of a DC link capacitor connected across the DC source, a current of one or more of the AC outputs and a junction temperature, a maximum discharge time, a drain-source voltage (Vds) or a voltage threshold (Vth) of one or more of the power switches.

19. A slew rate controllable system for powering a traction motor of a vehicle, comprising:

a plurality of power switches operable for converting a direct current (DC) input into an alternating current (AC) output suitable for electrically powering the traction motor, the power switches operable between an opened state and a closed state to facilitate generating the AC outputs; and

a gate drive system operable for controlling a slew rate associated with transitioning the power switches between the opened and closed states, the gate drive system including a plurality of gate drive circuits individually connected to a gate terminal of a corresponding one of the power switches, the gate drive circuits being operable for controlling a gate current (Ig) to a gate terminal of the power switch associated therewith, the Ig controlling the power switches between the opened and closed states.

20. The slew rate controllable system according to claim 19, further comprising:

a DC link capacitor connected between the power switches and a DC source providing the DC input, wherein the gate drive system is operable for controlling the slew rates of the power switches to optimize discharge speed of the DC link capacitor to avoid or minimize voltage overshoot when transitioning between the opened and closed states.