DEVICE WITH GATE-TO-DRAIN VIA AND RELATED METHODS
A device includes: a first stack of first semiconductor nanostructures; a second stack of second semiconductor nanostructures on the first stack of semiconductor nanostructures; a third stack of first semiconductor nanostructures adjacent the first stack; a first gate structure wrapping around the first stack and the second stack; a second gate structure wrapping around the third stack; a gate isolation structure between the first gate structure and the second gate structure; a dielectric layer on the second gate structure and laterally abutting the gate isolation structure; and a via. The via includes: a first portion that extends in a first direction, the first portion being on the first gate structure, the gate isolation structure and the dielectric layer; and a second portion that extends in a second direction transverse the first direction.
This application claims the benefit of priority to U.S. Provisional Application Ser. No. 63/413,556, entitled “Semiconductor structure with CFET SRAM and Method for forming the same,” filed on Oct. 5, 2022, which application is incorporated by reference herein in its entirety.
BACKGROUNDThe semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The present disclosure is generally related to semiconductor devices, and more particularly to field-effect transistors (FETs), such as planar FETs, three-dimensional fin-line FETs (FinFETs), or nanostructure devices. Examples of nanostructure devices include gate-all-around (GAA) devices, nanosheet FETs (NSFETs), nanowire FETs (NWFETs), and the like. In advanced technology nodes, with scaling down of integrated circuit (IC) devices, static random-access memory (SRAM) area reduction is increasingly difficult. Complementary (CFET) devices are a promising candidate for advanced logic and memory technology due to high transistor density, which can be achieved by stacking devices in bottom and top layers. In a CFET SRAM, gate-to-drain connections use a large extension due to gate and drain being connected by a lateral via.
Embodiments disclosed herein include an L-shaped middle via for gate-to-drain connection, which reduces SRAM area. Removal of a sacrificial gate and nanostructure channels is followed by formation of a dielectric replacement layer, which is advantageous for disposing the L-shaped middle via to reduce SRAM area. Inclusion of the L-shaped middle via for gate-to-drain connection relaxes gate isolation (CMG) overlay window and source/drain isolation (CMD) overlay window, which is advantageous for reducing SRAM area. The L-shaped middle via may be disposed at a frontside of the IC device or at a backside of the IC device, which increases design flexibility, and may simplify frontside routing when the L-shaped middle via is disposed at the backside.
The memory circuit 180 includes two pull-up transistors 182L, 182R, which are respectively operable to pull up voltages at nodes 190L, 190R to a first voltage level VDD, which may be a high voltage in some embodiments. The pull-up transistors 182L, 182R may be p-type field-effect transistors (PFETs), as shown. In some embodiments, the pull-up transistors 182L, 182R are n-type field-effect transistors (NFETs). Each of the pull-up transistors 182L, 182R has a source electrode coupled to a first supply node, a drain electrode coupled to the respective node 190L, 190R and a gate electrode coupled to the other of the nodes 190L, 190R, as shown.
The memory circuit 180 includes two pull-down transistors 184L, 184R, which are respectively operable to pull down voltages at the nodes 190L, 190R to a second voltage level VSS, which may be a low voltage or ground in some embodiments. The pull-down transistors 184L, 184R may be NFETs, as shown, or may be PFETs. Each of the pull-down transistors 184L, 184R has a source electrode coupled to a second supply node, a drain electrode coupled to the respective node 190L, 190R and a gate electrode coupled to the other of the nodes 190L, 190R, as shown.
The memory circuit 180 includes two pass gate transistors 186L, 186R, which are respectively operable to establish or cut off electrical communication between the nodes 190L, 190R and respective bit lines 192L, 192R. The pass gate transistors 186L, 186R may be NFETs, as shown, or PFETs. Each of the pass gate transistors 186L, 186R has a first source/drain electrode coupled to the respective bit line 192L, 192R, a second source/drain electrode coupled to the respective node 190L, 190R and a gate electrode coupled to a word line 194. The bit line 192L carries a first bit line signal BL, the bit line 192R carries a second bit line signal BLB, and the word line 194 carries a word line signal WL.
The memory circuit 180 includes two gate-to-drain vias 360, which are each connected to a respective pair of drain electrodes and a respective pair of gate electrodes of the transistors 182L, 184L or the transistors 182R, 184R. For example, one of the gate-to-drain vias 360 is connected to the gate electrode of the pull-up transistor 182L and the drain electrode of the pull-up transistor 182R. For example, the other of the gate-to-drain vias 360 is connected to the gate electrode of the pull-up transistor 182R and the drain electrode of the pull-up transistor 182L. The gate-to-drain vias 360 are L-shaped, and may be referred to as “L-shaped middle vias 360,” which will be described in greater detail with reference to
The sacrificial semiconductor layers 152 includes a semiconductor material different than the semiconductor material of the semiconductor layers 150. In particular, the sacrificial semiconductor layers 152 include materials that are selectively etchable with respect to the material of the semiconductor layers 150. As will be described in further detail below, the sacrificial semiconductor layers 152 will eventually be patterned to form sacrificial semiconductor nanostructures. The sacrificial semiconductor nanostructures will eventually be replaced by gate metals positioned between the semiconductor nanostructures 106. In one example, the sacrificial semiconductor layers 152 can include a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InALAs, InGaAs, GaSbP, GaAsSb and InP. In an example process described herein, the sacrificial semiconductor layers 152 include SiGe, while the semiconductor layers 150 include Si. Other materials and configurations can be utilized for the sacrificial semiconductor layers 152 and the semiconductor layers 150 without departing from the scope of the present disclosure.
In some embodiments, each semiconductor layer 150 includes intrinsic silicon and each sacrificial semiconductor layer 152 includes silicon germanium. The sacrificial semiconductor layers may have a relatively low germanium concentration of between 10% and 35%. A concentration in this range can provide sacrificial semiconductor layers 152 that are selectively etchable with respect to the semiconductor layers 150. In some embodiments, the semiconductor layers 150 have a thickness between 2 nm and 5 nm. In some embodiments, the sacrificial semiconductor layers 152 have a thickness between 4 nm and 10 nm. Other materials, concentrations, and thicknesses can be utilized for the semiconductor layers 150 and the sacrificial semiconductor layers 152 without departing from the scope of the present disclosure.
In some embodiments, the multilayer lattice 149 is formed by performing a series of epitaxial growth processes. A first epitaxial growth process grows the lowest sacrificial semiconductor layer 152 on the semiconductor substrate 133. A second epitaxial growth process grows the lowest semiconductor layer 150 on the lowest sacrificial semiconductor layer 152. Alternating epitaxial growth processes are performed to form the four lowest sacrificial semiconductor layers 152 and the three lowest semiconductor layers 150. Depending on the number of semiconductor nanostructures desired for the lower transistor 105 of the CFET 102, more or fewer sacrificial semiconductor layers 152 and semiconductor layers 150 can be formed.
After the semiconductor layers 150 and sacrificial semiconductor layers 152 associated with the lower transistor 105 have been formed, the sacrificial semiconductor layer 167 will be formed. In particular, an epitaxial growth process is performed to form the sacrificial semiconductor layer 167. In one example, the sacrificial semiconductor layer 167 is silicon germanium having a thickness between 1 nm and 25 nm and a length between 15 nm and 30 nm. The thickness of the sacrificial semiconductor layer 167 is greater than the thickness of the sacrificial semiconductor layers 152. The thickness of the sacrificial semiconductor layers 152 is greater than the thickness of the semiconductor layer 150. Other compositions, materials, and thicknesses can be utilized for the sacrificial semiconductor layer 167 without departing from the scope of the present disclosure.
After formation of the sacrificial semiconductor layer 167, the upper sacrificial semiconductor layers 152 and semiconductor layers 150 associated with the upper transistor 104 are formed. The upper sacrificial semiconductor layers 152 and semiconductor layers 150 can be formed with alternating epitaxial growth processes as described in relation to the lower semiconductor layers 150 and sacrificial semiconductor layers 152.
A mask layer 160 is formed and patterned over the multilayer lattice 149. In some embodiments, an optional layer 158 is formed between the multilayer lattice 149 and the mask layer 160, as shown. The optional layer 158 may be, for example, a dielectric layer that includes an oxide of the semiconductor material of the top semiconductor layer 150. The optional layer 158 is omitted from view in
In
The fins 32 and the nanostructures 106, 107, 165, 168 may be patterned by any suitable method. For example, one or more photolithography processes, including double-patterning or multi-patterning processes, may be used to form the fins 32 and the nanostructures 106, 107, 165, 168. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing for pitches smaller than what is otherwise obtainable using a single, direct photolithography process. As an example of one multi-patterning process, a sacrificial layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 32.
In
The insulation material undergoes a removal process, such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like, to remove excess insulation material over the nanostructures 106, 107, 165, 167. Top surfaces of the nanostructures 106, 107, 165, 167 may be exposed and level with the insulation material after the removal process is complete.
The insulation material is then recessed to form the isolation regions 174. After recessing, the nanostructures 106, 107, 165, 167 and upper portions of the fins 32 may protrude from between neighboring isolation regions 174. The isolation regions 174 may have top surfaces that are flat, convex, concave, as illustrated, or a combination thereof. In some embodiments, the isolation regions 174 are recessed by an acceptable etching process, such as an oxide removal using, for example, dilute hydrofluoric acid (dHF), which is selective to the insulation material and leaves the fins 32 and the nanostructures 106, 107, 165, 167 substantially unaltered.
Further in
In
In
In
Next, an inner spacer layer is formed to fill the recesses in the nanostructures 165, 167 formed by the previous selective etching process. The inner spacer layer may be a suitable dielectric material, such as silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), or the like, formed by a suitable deposition method such as PVD, CVD, ALD, or the like. An etching process, such as an anisotropic etching process, is performed to remove portions of the inner spacer layers disposed outside the recesses in the nanostructures 165, 167. The remaining portions of the inner spacer layers (e.g., portions disposed inside the recesses in the nanostructures 165, 167) form the inner spacers 114. The resulting structure is shown in
In the illustrated embodiment, the lower source/drain regions 117 are epitaxially grown from epitaxial material(s). When the bottom isolation layer is present, the lower source/drain regions 117 may grow epitaxially outward from sidewalls of the channels 107, and may merge in the space laterally between the channels 107 in the S/D trenches. When the bottom isolation layer is not present, such as is shown in
The lower source/drain regions 117 may include any acceptable material, such as appropriate for n-type or p-type devices. For n-type devices, the lower source/drain regions 117 include materials exerting a tensile strain in the channel regions, such as silicon, SiC, SiCP, SiP, SiAs or the like, in some embodiments. When p-type devices are formed, the lower source/drain regions 117 include materials exerting a compressive strain in the channel regions, such as Si:B, SiGe:B, SiGeB, Ge, GeSn, or the like, in accordance with certain embodiments. The lower source/drain regions 117 may have surfaces raised from respective surfaces of the fins 32 and may have facets, as illustrated in
The lower source/drain regions 117 may be implanted with dopants followed by an anneal. The lower source/drain regions 117 may have an impurity concentration of between about 1019 cm−3 and about 1021 cm−3. N-type and/or p-type impurities for lower source/drain regions 117 may be any of the impurities previously discussed. In some embodiments, the lower source/drain regions 117 are in situ doped during growth.
In
In
The upper source/drain regions 116 may include any acceptable material, such as appropriate for n-type or p-type devices. For n-type devices, the upper source/drain regions 116 include materials exerting a tensile strain in the channel regions, such as silicon, SiC, SiCP, SiP, SiAs or the like, in some embodiments. When p-type devices are formed, the upper source/drain regions 116 include materials exerting a compressive strain in the channel regions, such as SiGe, SiGeB, Ge, GeSn, or the like, in accordance with certain embodiments. The upper source/drain regions 116 may be implanted with dopants followed by an anneal. The upper source/drain regions 116 may have an impurity concentration of between about 1019 cm−3 and about 1021 cm−3. N-type and/or p-type impurities for upper source/drain regions 116 may be any of the impurities previously discussed. In some embodiments, the upper source/drain regions 116 are in situ doped during growth.
The upper source/drain regions 116 may have facets, as illustrated in
The source/drain regions 116 include a semiconductor material. The semiconductor material can include a same semiconductor material as the semiconductor nanostructures 106. Alternatively, the semiconductor material of the source/drain regions 116 can be different than the semiconductor material of the semiconductor nanostructures 106.
In
Next, the dummy gate layer 45 is removed in an etching process, so that recesses are formed. In some embodiments, the dummy gate layer 45 is removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gate layer 45 without etching the spacer layer 131. The dummy gate dielectric, when present, may be used as an etch stop layer when the dummy gate layer 45 is etched. The dummy gate dielectric may then be removed after the removal of the dummy gate layer 45.
The nanostructures 165, 167 are removed to release the nanostructures 106, 107. After the nanostructures 165, 167 are removed, the nanostructures 106, 107 form a plurality of nanosheets that extend horizontally (e.g., parallel to a major upper surface of the substrate 110). The nanosheets may be collectively referred to as the channels 106, 107 of the nanostructure device 10 formed.
In some embodiments, the nanostructures 165, 167 are removed by a selective etching process using an etchant that is selective to the material of the nanostructures 165, 167, such that the nanostructures 165, 167 are removed without substantially attacking the nanostructures 106, 107. In some embodiments, the etching process is an isotropic etching process using an etching gas, and optionally, a carrier gas, where the etching gas comprises F2 and HF, and the carrier gas may be an inert gas such as Ar, He, N2, combinations thereof, or the like.
In some embodiments, the nanosheets 106, 107 of the nanostructure device 10 are reshaped (e.g. thinned) by a further etching process to improve gate fill window. The reshaping may be performed by an isotropic etching process selective to the nanosheets 106, 107. After reshaping, the nanosheets 106, 107 may exhibit a dog bone shape in which middle portions of the nanosheets 106, 107 are thinner than peripheral portions of the nanosheets 106, 107 along the X direction.
In
After deposition of the interfacial gate dielectric layer 108 and the high-K gate dielectric layer 110 around the semiconductor nanostructures 106, 107, a gate metal 112 is deposited. The gate metal 112 may be deposited by PVD, CVD, ALD, or other suitable processes. The material or materials of the gate metal 112 may be selected to provide a desired work function with respect to the semiconductor nanostructures 107 of the P-type transistor 105. In one example, the gate metal 112 includes titanium aluminum. However, other conductive materials can be utilized for the gate metal 112 without departing from the scope of the present disclosure. For example, the gate metal 112 may be or include one or more of W, TiN, Ti, TaN, Ta, Al, Ru, and the like.
When the gate metal 112 is initially deposited, the gate metal 112 surrounds or wraps around the semiconductor nanostructures 106 and the semiconductor nanostructures 107. In some embodiments, the gate metal 112 has a material that provides a desired work function for the lower transistor 105 and the gate metal 112 may not provide a desired work function for the upper transistor 104. Accordingly, an etch-back process may be performed that removes the gate metal 112 to a level well below the lowest semiconductor nanostructure 106. In some embodiments, the etch-back process removes the gate metal 112 to a level that is about the vertical middle of the lower ILD 128, and a second gate metal (not shown) may be formed to replace the gate metal 112 removed previously.
After deposition of the gate metal 112 or optionally after deposition of the second gate metal, an etch-back process is optionally performed to reduce the height of the gate metal 112 above the top semiconductor nanostructure 106. After the etch-back process of the gate metal 112, an optional gate cap metal may be deposited on the gate metal 112. The gate cap metal can include tungsten, fluorine-free tungsten, or other suitable conductive materials. The gate cap metal can be deposited by PVD, CVD, ALD, or other suitable deposition processes. The gate cap metal may have a vertical thickness between 1 nm and 10 nm. Other dimensions can be utilized without departing from the scope of the present disclosure.
In
In some embodiments, the gate isolation structures 99 extend in a first direction (e.g., the X-axis direction) and are arranged along a second direction (e.g., the Y-axis direction). Width of the gate isolation structures 99 (e.g., in the Y-axis direction) may be in a range of about 5 nm to about 40 nm.
In
Following formation of contact openings, the source/drain contacts 124A, 124B may be formed by one or more deposition operations. The source/drain contacts 124A, 124B may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. The source/drain contacts 124A, 124B may be laterally surrounded by barrier layers (not shown), such as SiN or TiN, which help prevent or reduce diffusion of materials from and into the source/drain contacts 124A, 124B.
Silicide layers 120A, 120B, 120C may also be formed between the source/drain regions 116, 117 and the source/drain contacts 124A, 124B, which is advantageous to reduce source/drain contact resistance. The silicide layers 120A, 120B, 120C may contain a metal silicide material, such as cobalt silicide in some embodiments, or TiSi in some other embodiments. The silicide layers 120A, 120B may be referred to as horizontal silicide layers, and have major surfaces on the XY plane. The silicide layers 120C may be referred to as vertical silicide layers, and have major surfaces on the XZ plane. The source/drain contact 124B, which extends through the upper source/drain region 116, is adjacent or laterally surrounded by the vertical silicide layer(s) 120C and is adjacent or directly on the horizontal silicide layer 120B, as shown in
In
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In
In
After exposing the lower source/drain regions 117, backside source/drain contacts 460 are formed in the backside contact openings, which may be performed using the same or similar materials and processes used to form the source/drain contacts 124 on the frontside. In some embodiments, the backside source/drain contacts 460 are laterally surrounded by one or more barrier layers, which may be similar or the same as the barrier layers described previously with reference to the source/drain contacts 124.
Following formation of the backside source/drain contacts 460, the backside interconnect structure 500 is formed. The backside interconnect structure 500 may also be referred to as a backside back-end-of-line (BEOL) interconnect structure 500. The backside interconnect structure 500 is similar in many respects to the frontside interconnect structure 400, and may include one or more interconnect layers. Each of the interconnect layers may include a CESL, an ILD, and one or more metal features in the CESL and ILD. The metal features may include vias, wires, traces, and the like. In some embodiments, the backside interconnect structure 500 may include electrical contacts, such as solder bumps, controlled collapse chip connection (C4) bumps, or the like. In some embodiments, the frontside of the IC device 100 is free of electrical contacts.
In
In
Following recessing of the gate metal 112, the dielectric layer 99A is formed in the opening (act 1600). As shown in
In
Following formation of the source/drain contacts 124, the L-shaped middle vias 360 are formed. The CESL 142 and the ILD 320 may be formed as described with reference to
As shown in
In
In the device shown in
In the embodiment shown in
In some embodiments, the pass gate transistors 186L, 186R shown in
Embodiments may provide advantages. The L-shaped or T-shaped middle vias 360, 360A reduce cell area by relaxing gate isolation structure overlay window and source/drain region isolation overlay window.
In accordance with at least one embodiment, a device includes: a first stack of first semiconductor nanostructures; a second stack of second semiconductor nanostructures on the first stack of semiconductor nanostructures; a third stack of first semiconductor nanostructures adjacent the first stack; a first gate structure wrapping around the first stack and the second stack; a second gate structure wrapping around the third stack; a gate isolation structure between the first gate structure and the second gate structure; a dielectric layer on the second gate structure and laterally abutting the gate isolation structure; and a via. The via includes: a first portion that extends in a first direction, the first portion being on the first gate structure, the gate isolation structure and the dielectric layer; and a second portion that extends in a second direction transverse the first direction.
In accordance with at least one embodiment, a method includes forming a first vertical stack of nanostructure channels, a second vertical stack of nanostructure channels, a third vertical stack of nanostructure channels and a fourth vertical stack of nanostructure channels over a substrate, the second vertical stack being on the first vertical stack, the fourth vertical stack being on the third vertical stack; forming a first source/drain region abutting the nanostructure channels of the first vertical stack, and forming a second source/drain region abutting the nanostructure channels of the second vertical stack; forming a gate structure that wraps around the nanostructure channels of the first, second, third and fourth vertical stacks; forming a first gate structure and a second gate structure by forming a gate isolation structure that extends through the gate structure; forming an opening by removing a portion of the second gate structure; forming a dielectric layer in the opening; and forming a via on the first gate structure and the dielectric layer.
In accordance with at least one embodiment, a memory circuit includes: a first pull-up transistor having a first stack of nanostructure channels; and a first pull-down transistor. The first pull-down transistor includes: a second stack of nanostructure channels on the first stack; and a drain electrode coupled to a drain electrode of the first pull-up transistor. The memory circuit further includes: a second pull-up transistor having a gate electrode; a first pass gate transistor including: a third stack of nanostructure channels laterally separated from the first and second stacks; a gate electrode; and a drain electrode coupled to the drain electrodes of the first pull-up transistor and the first pull-down transistor; and a via. The via includes: a first portion that extends in a first direction, the first portion being on the gate electrode; and a second portion that extends in a second direction transverse the first direction, the second portion being on the drain electrodes of the first pull-up transistor, the first pull-down transistor and the first pass gate transistor.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A device, comprising:
- a first stack of first semiconductor nanostructures;
- a second stack of second semiconductor nanostructures on the first stack of semiconductor nanostructures;
- a third stack of first semiconductor nanostructures adjacent the first stack;
- a first gate structure wrapping around the first stack and the second stack;
- a second gate structure wrapping around the third stack;
- a gate isolation structure between the first gate structure and the second gate structure;
- a dielectric layer on the second gate structure and laterally abutting the gate isolation structure; and
- a via that includes: a first portion that extends in a first direction, the first portion being on the first gate structure, the gate isolation structure and the dielectric layer; and a second portion that extends in a second direction transverse the first direction.
2. The device of claim 1, wherein the first portion partially overlaps the third stack along the first direction.
3. The device of claim 1, wherein the first portion extends past the third stack along the first direction.
4. The device of claim 1, wherein the via is electrically connected to a drain region of a first pull-up transistor and to a gate electrode of a second pull-up transistor, the gate electrode including the first gate structure.
5. The device of claim 4, wherein the first portion overlaps the gate electrode, and the second portion overlaps the drain region.
6. The device of claim 1, wherein the via has height in the first direction and width in the second direction, and a ratio of the height to the width is in a range of about 1 to about 2.
7. The device of claim 1, further comprising:
- a first source/drain region adjacent the first stack of nanostructures;
- a second source/drain region adjacent the second stack of nanostructure;
- a third source/drain region adjacent the third stack of nanostructures;
- a first source/drain contact on the second source/drain region; and
- a second source/drain contact under the first source/drain region.
8. The device of claim 7, further comprising:
- a fourth source/drain region adjacent the dielectric layer; and
- a third source/drain contact on the third source/drain region, the third source/drain contact extending through the fourth source/drain region.
9. A method, comprising:
- forming a first vertical stack of nanostructure channels, a second vertical stack of nanostructure channels, a third vertical stack of nanostructure channels and a fourth vertical stack of nanostructure channels over a substrate, the second vertical stack being on the first vertical stack, the fourth vertical stack being on the third vertical stack;
- forming a first source/drain region abutting the nanostructure channels of the first vertical stack, and forming a second source/drain region abutting the nanostructure channels of the second vertical stack;
- forming a gate structure that wraps around the nanostructure channels of the first, second, third and fourth vertical stacks;
- forming a first gate structure and a second gate structure by forming a gate isolation structure that extends through the gate structure;
- forming an opening by removing a portion of the second gate structure;
- forming a dielectric layer in the opening; and
- forming a via on the first gate structure and the dielectric layer.
10. The method of claim 9, further comprising:
- forming a source/drain contact on the second source/drain region.
11. The method of claim 10, wherein the opening is formed after the forming a source/drain contact.
12. The method of claim 9, further comprising:
- exposing an underside of the second gate structure by removing the substrate; and
- forming the opening by etching the underside of the second gate structure.
13. The method of claim 9, wherein the via includes:
- a first portion that extends in a first direction, the first portion being on the first gate structure, the gate isolation structure and the dielectric layer; and
- a second portion that extends in a second direction transverse the first direction.
14. A memory circuit, comprising:
- a first pull-up transistor having a first stack of nanostructure channels;
- a first pull-down transistor including: a second stack of nanostructure channels on the first stack; and a drain electrode coupled to a drain electrode of the first pull-up transistor;
- a second pull-up transistor having a gate electrode;
- a first pass gate transistor including: a third stack of nanostructure channels laterally separated from the first and second stacks; a gate electrode; and a drain electrode coupled to the drain electrodes of the first pull-up transistor and the first pull-down transistor; and
- a via that includes: a first portion that extends in a first direction, the first portion being on the gate electrode; and a second portion that extends in a second direction transverse the first direction, the second portion being on the drain electrodes of the first pull-up transistor, the first pull-down transistor and the first pass gate transistor.
15. The memory circuit of claim 14, further comprising:
- a second pull-down transistor having a gate electrode coupled to the gate electrode of the second pull-up transistor; and
- a second pass gate transistor having a drain electrode coupled to drain electrodes of the second pull-up transistor and the second pull-down transistor.
16. The memory circuit of claim 15, further comprising a second via, the second via including:
- a third portion that extends in the first direction, the third portion being on gate electrodes of the first pull-up transistor and the first pull-down transistor; and
- a fourth portion that extends in the second direction transverse the first direction, the second portion being on the drain electrodes of the second pull-up transistor, the second pull-down transistor and the second pass gate transistor.
17. The memory circuit of claim 16, wherein the via and the second via are disposed on a backside of the memory circuit.
18. The memory circuit of claim 15, further comprising:
- a dielectric layer on the third stack.
19. The memory circuit of claim 18, wherein the dielectric layer extends vertically from the gate electrode of the first pass gate transistor to a bottom side of the via.
20. The memory circuit of claim 14, further comprising:
- a backside via that is electrically connected to the gate electrode of the first pass gate transistor and to a word line.
Type: Application
Filed: Feb 21, 2023
Publication Date: Apr 11, 2024
Inventors: Yi-Bo LIAO (Hsinchu), Jin CAI (Hsinchu)
Application Number: 18/172,246