Method and apparatus of a multi-code code division multiple access receiver having a shared accumulator circuits

Abstract

A Multi-Code (MC) Code Division Multiple Access (CDMA) receiver receives N (where N.gtoreq.1) encoded signal channels over multiple air signal paths. The N signal channels are encoded using a properly chosen subset of Walsh codes based on a Walsh-Matrix, W.sup.M, where M is a power of two. In the disclosed MC-CDMA receiver, a timing correlator means recovers the timing and control signal for the N signal channels received over any particular signal path; a FWHT circuit together with a second correlator means decodes all of the N signal channels.

Claims

1. A multicode (MC) code division multiple access (CDMA) receiver comprising

rake receiver means for receiving a MC-CDMA signal including N (where N>1) signal channels with linearly modulated data being spread using binary spreading code sequences of N.sub.c chips,

wherein each of the binary spreading code sequences of N.sub.c chips includes a plurality of N subcode sequences, where N.ltoreq.N.sub.c and wherein the nth subcode sequence, n=1, 2,..., N, of each of the N signal channels are encoded using subcode sequence H.sub.n or its binary inverse H.sub.n.sup.',

a first complex correlator means for tracking and acquiring timing information for a preselected channel of the MC-CDMA signal, and

a second correlator means, including a FWHT means, and utilizing the acquired timing information and the N subcode sequences for simultaneously decoding the N signal channels by correlating the corresponding intervals of the received signal by the subcodes H.sub.1, H.sub.2, H.sub.3,..., H.sub.N, and using these outputs as inputs to the FWHT.

2. The MC-CDMA receiver of claim 1 wherein said second correlator means includes

a) a Base-Walsh-Code despreader for producing N.sub.c signal samples per symbol,

b) an accumulator for accumulating the N.sub.c signal samples outputted from the Walsh despreader, wherein the accumulator is reset for every N.sub.c /N input samples, to produce N complex intermediate results,

c) means for storing the N complex intermediate results, and

d) a complex FWHT circuit, with N.sub.c -N log.sub.2 N complex additions where N is<or=to N.sub.c and where N=M=2.sup.i and i is>or=to 1 for processing the stored N complex intermediate results to form N correlator outputs.

3. The MC-CDMA receiver of claim 1 wherein said second correlator means includes

a) a Base-Walsh-Code despreader for producing N.sub.c signal samples per symbol,

b) an accumulator for accumulating the N signal samples outputted from the Walsh despreader, wherein the accumulator is reset for every N.sub.c /N input samples, to produce N complex intermediate results,

c) multiplier for multiplying each of the N complex intermediate results by a channel weighting factor signal to form N real intermediate results,

d) means for storing the N real intermediate results, and

e) a real FWHT circuit, with N.sub.c +N log.sub.2 N complex additions, where N is<or=to N.sub.c and where N+M+2.sup.i and i is>or to 1, for processing the stored N real intermediate results to form N correlator outputs.

4. The MC-CDMA receiver of claim 1 wherein said first correlator means operates in a coherent mode.

5. The MC-CDMA receiver of claim 1 wherein said first correlator means operates in a non-coherent mode.

6. The MC-CDMA receiver of claim 1 wherein at least one of the N signal channels includes a Q and an I signal channels and the second correlator means decodes the Q and I signal channels.

7. The MC-CDMA receiver of claim 6 wherein the Q and I signal channels carry independent data signals.

8. The MC-CDMA receiver of claim 6 wherein the Q and I signal channels are combined to form a single data signal.

9. The MC-CDMA receiver of claim 1 being part of a user station of a MC-CDMA system including at least one base station and a plurality of user stations.

10. The MC-CDMA receiver of claim 1 being part of a base station of a MC-CDMA system including at least one base station and a plurality of user stations.

11. The MC-CDMA receiver of claim 1 wherein the spreading codes are orthogonal Walsh codes.

12. The MC-CDMA receiver of claim 1 wherein the binary spreading codes ate Walsh codes based on a Walsh-Matrix, W.sup.M, where M is a power of two.

13. The MC-CDMA receiver of claim 1 wherein the second correlator means includes a FWHT means, and includes at least N.sub.c +N/2 log.sub.2 N complex additions, and utilizes the acquired timing information and the N subcode sequences for simultaneously decoding the N signal channels bv correlating the corresponding intervals of the received signal by the subcodes H.sub.1, H.sub.2, H.sub.3,..., H.sub.N, and using these outputs as inputs to the FWHT.

14. The MC-CMDA receiver of claim 1 further comprising a common logic circuit for time-sharing an accumulator among said first and second correlator means.

15. A multicode (MC) code division multiple access (CDMA) receiver comprising

rake receiver means for receiving a MC-CDMA signal including N (where N>1) encoded signal channels, the N signal channels being encoded using Walsh codes based on a Walsh-Matrix, W.sup.M. where M is a power of two,

a first complex correlator means for tracking and acquiring timing information for a preselected channel of the MC-CDMA signal,

a second correlator means, utilizing the acquired timing information and including a FWHT means for decoding the N signal channels, and

wherein said second correlator means includes N.sub.c +N/2 log.sub.2 N complex additions, where N is<or=to N.sub.c and where N.sub.c =M=2.sup.i and i is>or=to 1.

16. A multicode (MC) code division multiple access (CDMA) receiver comprising rake receiver means for receiving a MC-CDMA signal including N (where N>1) encoded signal channels, the N signal channels being encoded using Walsh codes based on a Walsh-Matrix, W.sup.M, where M is a power of two,

first complex correlator means for tracking and acquiring timing information for a preselected channel of the MC-CDMA signal,

a second correlator means, utilizing the acquired timing information and including a FWHT means for decoding the N signal channels, wherein the spreading codes are Walsh codes based on a Walsh-Matrix, W.sup.M, where M is a power of two, and

a common logic circuit for time-sharing an accumulator, for accumulating the timing information and the N signal samples, among said first and second correlator means.

17. A method of operating a multicode (MC) code division multiple access (CDMA) receiver comprising the steps of:

receiving a MC-CDMA signal including N (where N>1) encoded signal channels, the N signal channels being encoded using binary spreading codes of N.sub.c chips, where N.sub.c is an integer.gtoreq.N,

wherein each of the binary spreading code sequences of N.sub.c chips includes a plurality of N subcode sequences, where the nth subcode sequence n=1, 2,..., N of each of the N signal channels are encoded using subcode sequence H.sub.n or its binary inverse H.sub.n.sup.',

tracking and acquiring timing information for a preselected channel of the MC-CDMA signal, and

utilizing the acquired timing information and the N subcode sequences for simultaneously decoding the N signal channels by correlating the corresponding intervals of the received signal by the subcodes H.sub.1, H.sub.2,H.sub.3,..., H.sub.N, and using these outputs as inputs to the FWHT.

18. A method of operating a multicode (MC) code division multiple access (CDMA) receiver comprising the steps of:

receiving a MC-CDMA signal including N (where N>1) encoded signal channels, the N signal channels being encoded using Walsh codes based on a Walsh-Matrix, W.sup.M, where M is a power of two, and,

tracking and acguiring timing information for a preselected channel of the MC-CDMA signal,

utilizing the acquired timing information and decoding the N signal channels using at least N.sub.c +N/2 log.sub.2 N complex additions, where N is<or=to N.sub.c and where N.sub.c =M=2.sup.i and i is>or=to 1.