Switching multi-context processor and method overcoming pipeline vacancies

Abstract

An instruction executing section supplies an instruction of a certain context to a pipeline and executes the context. When a vacancy of the pipeline is judged, the instruction executing section switches the context to another context which is being executed, thereby simultaneously executing a plurality of contexts. An ID setting section sets a peculiar context ID to each of the plurality of contexts which are simultaneously executed by the instruction executing section. A register renaming section executes a multi-renaming such that a register name which is used when the plurality of contexts are simultaneously executed by the instruction executing section is renamed to a register name CIDi-Rj obtained by adding a designation register name Rj (j=1, 2, 3, . . . , m) of an execution instruction to CIDi as a context ID which was set by an ID setting section and whose context is being executed and the physical register is allocated.

Claims

1. A processor for simultaneously supplying a plurality of contexts to a pipeline and executing said contexts, comprising:

a plurality of context storing sections, in each of which is stored one of the plurality of contexts as an execution unit for performing a function of a certain meaning, each of said contexts includes an instruction train having an attribute information field for storing not only a program code but also various information to assist the execution of said program code although a meaning of said program code is not changed, and instruction execution information necessary to execute a subsequent instruction serving as a timing for switching the context corresponding to the instruction train to another context which is being executed is provided in said attribute information field;

an instruction executing section for supplying the instruction train of each of said contexts to the pipeline and executing said instruction train and, when a vacancy of said pipeline is judged, for switching said context corresponding to the instruction train to another context which is being executed and for simultaneously executing said plurality of contexts;

an ID setting section for setting a context ID which is peculiar to each of said plurality of contexts which are simultaneously being executed by said instruction executing section; and

a register renaming section for renaming a name of a register which is used when said plurality of contexts are simultaneously executed by said instruction executing section to a register name obtained by adding a designation register name of an execution instruction to a context ID which was set by said ID setting section and whose context is being executed, and for allocating a physical register,

wherein said instruction executing section has:

at least two instruction storage buffers;

a first router for switching a prefetch route during an instruction prefetch to prefetch the instruction train for one of said plurality of contexts to one of said instruction storage buffers;

a second router for switching a fetch route during an instruction fetch to fetch the instruction train from one of said instruction storage buffers to said pipeline; and

a context switching section which, when the instruction execution information is decoded from the attribute information of the instruction train corresponding to the context which is being supplied to the pipeline, said first router switches said prefetch route from a context on a switching destination side to one of the instruction buffers which is not being used for the instruction fetch, thereby allowing the instruction prefetch to be executed, and subsequently, when the execution of said subsequent instruction serving as the timing for switching to another context is judged, said second router switches said fetch route to the one of the instruction buffers to which the prefetch route was switched by said first router, thereby allowing the instruction of another context which has been prefetched to be fetched to the pipeline.

2. A processor according to claim 1, wherein said subsequent instruction for allowing said context switching is a load instruction, and attribute information to indicate an instruction fetch of another context which is being executed simultaneously with the execution of said instruction is provided for said attribute information field of a precedent instruction code having an interval of a latency which is caused until data reaches from a memory by an execution of said load instruction.

3. A processor according to claim 1, wherein said subsequent instruction for allowing said context switching is a branch instruction, and attribute information to indicate an instruction fetch of another context which is being executed simultaneously with the execution of said instruction is provided for said attribute information field of a precedent instruction code having an interval of a latency which is caused until data reaches from a memory by an execution of said branch instruction.

4. A processor according to claim 1, wherein said instruction executing section recognizes said subsequent instruction serving as a timing for switching to another context which is being executed from a signal of a hardware in association with the execution of said subsequent instruction and switches the contexts.

5. A processor according to claim 4, wherein in the case where said subsequent instruction is a load instruction, said instruction executing section recognizes said context switching from a signal indicative of a mishit of a cache in the execution of said load instruction.

6. A processor according to claim 4, wherein in the case where said subsequent instruction is a branch instruction, said instruction executing section recognizes said context switching from an output of a branch target buffer indicative of a state in which a branch condition is satisfied (taken) in the execution of said branch instruction.

7. A processor according to claim 1, wherein said register renaming section comprises:

an ID register for storing the context ID of the context which is being executed;

an instruction register to fetch the instruction of the context which is being executed;

a renaming register file in which a plurality of physical registers each having a valid flag field, a register key field, and a data field have been mapped on a memory;

a register allocating section for forming a register key obtained by adding a register name of a register designation field of said instruction register to the context ID of said ID register and for allocating a corresponding physical register of said register file as a renaming register;

a register saving section, provided for every context which is being executed, for saving data of said renaming register which overflowed from said register file;

a save processing section for saving the data of said renaming register from said register file to said register saving section; and

a load processing section for loading the data of the corresponding register key from said register saving section into said register file in the case where the register corresponding to said register key doesn't exist with reference to said register file by said register allocating section.

8. A processor according to claim 7, wherein said renaming register file has physical registers of the number which can be designated by the register designation field of said instruction register.

9. A processor according to claim 7, wherein said renaming register file shows a using state by turning on said valid flag by allocating the renaming register by said register allocating section and shows a vacant state by turning off the valid flag by saving the register data by said save processing section.

10. A processor according to claim 7, wherein said register saving section has a valid flag field in addition to a data field to store saving data, shows a data saving state by turning on a valid flag by saving the register data by said save processing section, and shows the existence in said renaming register file by turning off said valid flag by loading the saving data by said load processing section.

11. A processor according to claim 7, wherein when an overflow occurs in said renaming register file, said save processing section saves the data of all of said physical registers having the context ID of either one of the other contexts in an execution waiting state to the register saving section of the corresponding context.

12. A processor according to claim 7, wherein prior to loading the register data of the context which is being executed from said register saving section to said renaming register file, said load processing section allows said save processing section to save the data of said physical register having the context ID of either one of the other contexts in the execution waiting state into the register saving section of the corresponding context.

13. A processor according to claim 7, wherein said save processing section and said load processing section execute a saving operation and a loading operation of the register data on a renaming register unit basis.

14. A processor according to claim 1, wherein said plurality of contexts are a plurality of processes which are executed in different address spaces.

15. A processor according to claim 1, wherein said plurality of contexts are a plurality of threads which are executed in the same address space.

16. A processor according to claim 15, wherein said thread is a loop of a numerical value calculating program.

17. A processing method for a processor for simultaneously supplying a plurality of contexts to a pipeline and for executing said contexts, comprising:

a forming step of forming a plurality of contexts as execution units each for performing a function of a certain meaning, each of said contexts includes an instruction train having an attribute information field for storing not only a program code but also various information to assist the execution of said program code although a meaning of said program code is not changed, and instruction execution information necessary to execute a subsequent instruction serving as a timing for switching the context corresponding to the instruction train to another context which is being executed is provided in said attribute information field;

an instruction executing step of supplying the instruction train of each of the contexts to the pipeline and executing said instruction train and, when a vacancy of said pipeline is judged, switching the context corresponding to the instruction train to another context which is being executed and simultaneously executing said plurality of contexts;

an ID setting step of setting a context ID which is peculiar to each of said plurality of contexts which are simultaneously being executed; and

a register renaming step of renaming a register name which is used by the execution of said context to a register name obtained by adding a designation register name of an execution instruction to said context ID, thereby allocating a physical register,

wherein said instruction executing step further includes the steps of:

after prefetching the instruction train of the context being executed to an instruction buffer, fetching the instruction train to the pipeline and executing the instruction train;

after decoding the instruction execution information from the attribute information of the instruction train of the context being executed, switching a prefetch route to prefetch the context on the switching destination side to an instruction buffer which is not being used for an instruction fetch, and

subsequently, after judging the execution of said subsequent instruction serving as a timing for switching to another context, fetching to the pipeline the instruction of another context which was prefetched to the instruction buffer.

18. A method according to claim 17, wherein said subsequent instruction for allowing said context switching is a load instruction, and attribute information to indicate an instruction fetch of another context which is being executed simultaneously with the execution of said instruction is provided for the attribute information field of a precedent instruction code having an interval of a latency which is caused until data reaches from a memory by the execution of said load instruction.

19. A method according to claim 17, wherein said subsequent instruction for allowing said context switching is a branch instruction, and attribute information to indicate an instruction fetch of another context which is being executed simultaneously with the execution of said instruction is provided for the attribute information field of a precedent instruction code having an interval of a latency which is caused until data reaches from a memory by the execution of said branch instruction.

20. A method according to claim 17, wherein in said instruction executing step, a subsequent instruction serving as a timing for switching to another context which is being executed is recognized from a signal of a hardware in association with said subsequent instruction, and the context is switched.

21. A method according to claim 20, wherein in said instruction executing step, in the case where said subsequent instruction is a load instruction, said context switching is recognized from a signal indicative of a mishit of a cache in the execution of said load instruction.

22. A method according to claim 20, wherein in said instruction executing step, in the case where said subsequent instruction is a branch instruction, said context switching is recognized from an output of a branch target buffer indicative of a state in which a branch condition is satisfied (taken) in the execution of said branch instruction.

23. A method according to claim 17, wherein in said renaming step,

the context ID of the context which is being executed is stored into an ID register,

the instruction of the context which is being executed is fetched to the instruction register;

a register key obtained by adding a register name of a register designation field in the instruction fetched to said instruction register to the context ID of the context which is being executed is formed,

a corresponding physical register of a renaming register file having a plurality of physical registers each having a valid flag field, a register key field, and a data field is retrieved by said register key and is allocated as renaming register,

when an overflow of said register file occurs, the data of said renaming register is saved to a register saving section provided for every context which is being executed, and

in the case where the register corresponding to said register key doesn't exist with reference to said register file, the data of the register key is loaded from said register saving section to said register file.

24. A method according to claim 23, wherein said renaming register file has the physical registers of the number which can be designated by a register designation field of said instruction register.

25. A method according to claim 23, wherein when the renaming registers are allocated to said physical registers, said valid flag is turned on, thereby showing a using state, and said valid flag is turned off by the saving of said register data, thereby showing a vacant state.

26. A method according to claim 23, wherein said register saving section has a valid flag field in addition to a data field to store the saving data, a valid flag is turned on by saving the register data from said renaming register file, thereby showing a data saving state, and said valid flag is turned off by loading the saving data to said renaming register file, thereby showing the existence in said renaming register file.

27. A method according to claim 23, wherein when an overflow occurs in said renaming register file, the data of all of said physical registers having the context ID of either one of the other contexts in an execution waiting state is saved to the register saving section of the corresponding context.

28. A method according to claim 23, wherein prior to loading the register data of the context which is being executed from said register saving section to said renaming register file, the data of said physical register having the context ID of either one of the other contexts in an execution waiting state is saved to the register saving section of the corresponding context.

29. A method according to claim 23, wherein the saving operation and the loading operation of the register data are executed on a renaming register unit basis.

30. A method according to claim 17, wherein said plurality of contexts are a plurality of processes which are executed in different address spaces.

31. A method according to claim 17, wherein said plurality of contexts are a plurality of threads which are executed in a same address space.

32. A method according to claim 31, wherein said thread is a loop of a numerical value calculating program.

33. A processor for simultaneously supplying a plurality of contexts to a pipeline and executing said contexts, comprising:

a plurality of context storing sections, in each of which is stored one of the plurality of contexts as an execution unit for performing a function of a certain meaning, each of said contexts includes an instruction train having an attribute information field for storing not only a program code but also various information to assist the execution of said program code although a meaning of said program code is not changed, and instruction execution information necessary to execute a subsequent instruction serving as a timing for switching the context corresponding to the instruction train to another context which is being executed is provided in said attribute information field; and

an instruction executing section for supplying the instruction train of each of said contexts to the pipeline and executing said instruction train and, when a vacancy of said pipeline is judged, for switching said context corresponding to the instruction train to another context which is being executed and for simultaneously executing said plurality of contexts, said instruction executing section including:

at least two instruction storage buffers;

a first router for switching a prefetch route during an instruction prefetch to prefetch the instruction train for one of said plurality of contexts to one of said instruction storage buffers;

a second router for switching a fetch route during an instruction fetch to fetch the instruction train from one of said instruction storage buffers to said pipeline; and

a context switching section which, when the instruction execution information is decoded from the attribute information of the instruction train corresponding to the context which is being supplied to the pipeline, said first router switches said prefetch route from a context on a switching destination side to one of the instruction buffers which is not being used for the instruction fetch, thereby allowing the instruction prefetch to be executed, and subsequently, when the execution of said subsequent instruction serving as the timing for switching to another context is judged, said second router switches said fetch route to the one of the instruction buffers to which the prefetch route was switched by said first router, thereby allowing the instruction of another context which has been prefetched to be fetched to the pipeline.

34. A processing method for a processor for simultaneously supplying a plurality of contexts to a pipeline and for executing said contexts, comprising:

a forming step of forming a plurality of contexts as execution units each for performing a function of a certain meaning, each of said contexts includes an instruction train having an attribute information field for storing not only a program code but also various information to assist the execution of said program code although a meaning of said program code is not changed, and instruction execution information necessary to execute a subsequent instruction serving as a timing for switching the context corresponding to the instruction train to another context which is being executed is provided in said attribute information field; and

an instruction executing step of supplying the instruction train of each of the contexts to the pipeline and executing said instruction train and, when a vacancy of said pipeline is judged, switching the context corresponding to the instruction train to another context which is being executed and simultaneously executing said plurality of contexts, said instruction executing step further includes the steps of:

after prefetching the instruction train of the context being executed to an instruction buffer, fetching the instruction train to the pipeline and executing the instruction train;

after decoding the instruction execution information from the attribute information of the instruction train of the context being executed, switching a prefetch route to prefetch the context on the switching destination side to an instruction buffer which is not being used for an instruction fetch; and

subsequently, when the execution of said subsequent instruction serving as a timing for switching to another context is judged, fetching to the pipeline the instruction of another context which was prefetched to the instruction buffer.