Abstract: A thin film magnetic head which includes a magnetoresistive layer selectively formed; a magnetic bias layer sandwiching said magnetoresistive layer; a pair of leads for detecting magnetic resistance; and a cap layer formed under the lead between the magnetoresistive layer. This configuration enables to accurately specify a magnetic response region by both ends of the cap layers, concentrating the current from the lead onto the magnetic response region through a tip of the cap layer for improving a S/N ratio.

Abstract: The present invention provides a thin film magnetic head having a recording track width of 1 &mgr;m or less, and a method for manufacturing the thin film magnetic head having a recording track width of 1 &mgr;m or less. In the thin film magnetic head, an upper core layer and a lower core layer extend from a back region toward a magnetic pole tip region, and are exposed at a medium opposing surface, and a gap layer is provided, in the magnetic pole tip region, between the upper core layer and the lower core layer. An insulation layer is deposited on the lower core layer, and a groove that extends from the medium opposing surface toward the back region is provided in the magnetic pole tip region of the insulation layer. A lower magnetic pole layer, the gap layer, and an upper magnetic pole layer are deposited in the groove. The lower magnetic pole layer is joined to the lower core layer, while the upper magnetic pole layer is joined to the upper core layer.

Abstract: An application specific signal processor (ASSP) performs vectorized and nonvectorized operations. Nonvectorized operations may be performed using a saturated multiplication and accumulation operation. The ASSP includes a serial interface, a buffer memory, a core processor for performing digital signal processing which includes a reduced instruction set computer (RISC) processor and four signal processing units. The four signal processing units execute the digital signal processing algorithms in parallel including the execution of the saturated multiplication and accumulation operation. The ASSP is utilized in telecommunication interface devices such as a gateway. The ASSP is well suited to handling voice and data compression/decompression in telecommunication systems where a packetized network is used to transceive packetized data and voice.

Abstract: An apparatus and method are provided for concurrently loading single-precision operands into registers in a microprocessor floating point register file. The apparatus includes translation logic, data logic, and write back logic. The translation logic receives a load macro instruction prescribing an address, and decodes the load macro instruction into a double load micro instruction. The double load micro instruction directs the microprocessor to retrieve the two single-precision operands from the address and to load the two single-precision operands into the two floating point registers. The data logic, coupled to the translation logic, executes the double load micro instruction and retrieves the two single-precision operands from the address. The write back logic, coupled to the data logic, loads the two single-precision operands into the two floating point registers during a single write cycle.

Abstract: A programmable logic device having redundant sets of logic blocks which are capable of being enabled or disabled. The programmable logic device includes a plurality of sets of logic blocks, a plurality of routing resources and a programming circuit. Good logic blocks are enabled and fully operational when programmed. Nonfunctional logic blocks are disabled, powered off and invisible to the programming software. Each set of logic blocks has a corresponding routing resource. The routing resource corresponding to an enabled set of logic blocks is capable of being configured to provide input and output data paths for the enabled set of logic blocks. The routing resource corresponding to a disabled set of logic blocks is capable of being configured to bypass the disabled set of the logic blocks. The programming circuit stores the configuration data for the routing resources and is capable of providing the configuration data to a routing resource that corresponds to an enabled set of logic blocks.

Abstract: Each execution unit within a superscalar processor has an associated completion table that contains a copy of the status of all instructions dispatched but not completed. A central completion table maintains the status of every dispatched instruction as reported by the dispatch unit and the individual execution units. Execution units send finish signals to the completion table responsible for retiring a particular type of instruction. The central completion table retires instructions that may cause an interrupt and instructions whose results may target the same register. The execution units' associated completion tables retire the balance of the instructions and the execution units send instruction status to the central completion table and to each execution unit. This reduces the number of instructions that are retired by the central completion table, increasing the number of instructions retired per clock cycle.

Abstract: An improved field programmable gate array (FPGA) is provided which includes tab network connectors for interfacing groups of configurable function generators with lower levels of interconnect and for interfacing lower levels of interconnect with higher levels of interconnect. Furthermore, an innovative cluster architecture is utilized which provides fine granularity without a significant increase in configurable function generators. The tab connector network can also be used to route a lower level routing line to a higher level routing line. This is particularly desirable in order to meet the needs for driving a signal along longer routing lines without requiring all signal drivers be sufficiently large to drive a signal along the longest routing line. The connector networks described enable a flexible routing scheme to be implemented in which the routing lines at each level are divided into sets.

Abstract: The data processing device according to the invention comprises an instruction providing unit having an input and an output, a pipeline unit for processing data having input and output stages, a loop pipeline unit for processing a loop instruction having input and output stages, said input stages of said pipeline units being coupled to said output of said instruction providing unit, said instruction providing unit providing data for said pipelines, and said pipeline units processing said data independently.

Abstract: One aspect of the invention relates to a method for operating a processor. In one version of the invention, the method includes the steps of dispatching an instruction; determining a presently architected RMAP entry for the architectural register targeted by the dispatched instruction; selecting the RMAP entries which are associated with physical registers that contain operands for the dispatched instruction; updating a use indicator in the selected RMAP entries; determining whether the dispatched instruction is interruptible; and updating an architectural indicator and a historical indicator in the presently architected RMAP entry if the dispatched instruction is uninterruptible.

Abstract: Disclosed is a system and method for implementing a distributed network system, such as the World Wide Web, in which distributed location services are utilized and include a collection of server processes that map from resource identifiers to a resource's controlling server. In addition, distributed location services provide an architecture for assigning resource identifiers and set of protocols for accessing server processes. The server processes are logically defined to provide a more flexible system. Each of these logical server processes are an abstraction which provides the external view of the server. The logical server processes may be implemented by different numbers of physical processes running on different machines at different points in time.

Abstract: An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the pipeline units processing a plurality of instructions including branch instructions. The instruction pipeline further includes a plurality of storage device which store a respective branch information data. Each of the storage devices are associated with at least one of pipeline units. Each respective branch information data is determined as a function of at least one of the branch instructions processed. Two of the pipeline units include branch prediction circuitry for predicting branch direction as a function of the stored branch information data.

Abstract: A memory request protocol allows a memory request to be withdrawn or "cancelled" without penalty so no memory resource is wasted in doing so during an assigned "cancel window". When the memory card starts to process a command from the memory controller, for a predefined number of cycles a period of time is available where the memory card can't accept another command due to a resource conflict. This provides an opportunity to re-balance requests to the memory controller in this period of time or "cancel window".

Abstract: A single-instruction multiple-data (SIMD) processor (10) that incorporates features for horizontal scaling of video data. The processor (10) has a data input register (11) that is operable to store input data word in sequential locations in the data input register (11) and transfer the input data words to an array of processing elements. The processor (10) also has an output data register (16) operable to receive data output words from the array of processing elements and to output said data output words from sequential locations of said output data array. An input skip signal input to the processor causes a sequential data write operation to skip a location of the input data register while an output skip signal to the processor causes a sequential data read operation to skip a location of the output data register.

Abstract: An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.

Abstract: A data processing circuit adapted for use in pattern matching between two sets of multi-dimensional signal data. The data processing circuit performs integration-based conversion on data aw calculated by multiplying first multi-dimensional signal data a by a window function w, second multi-dimensional signal data b, data b.sup.2 calculated by squaring the data b, and the window function w, calculates a correlation between the first and second multi-dimensional signal data items a and b on the basis of the data aw and data b subjected to integration-based conversion, calculates a means of deviations from the square of the second multi-dimensional signal data b on the basis of the data b.sup.2 and window function subjected to integration-based conversion, and calculates a portion of the second multi-dimensional signal data b most consistent with the first multi-dimensional signal data a multiplied by the window function w.

Abstract: A superscalar microprocessor implements a repeated string instruction by putting the microcode unit in a continuous loop. The microcode sequence that implements the repeated string operation includes a conditional-exit instruction rather than a conditional branch and decrement microcode instruction. A conditional-exit instruction decrements a loop count value and conveys a termination signal to a microcode unit when a termination condition is detected. Because several iterations of the instructions that implement the string instruction may be dispatched before the conditional-exit instruction is evaluated, the additional iterations of the microcode loop are canceled. By eliminating the conditional branch and decrement microcode instruction, a loop iteration may be executed in a single clock cycle by three functional units.

Abstract: At least one peripheral processing apparatus and at least one information processing apparatus, interconnected through a network, include a storage means for storing control information by which the information processing apparatus controls the peripheral apparatus through the network. The control information stored in the storage means is transferred through the network to the information processing apparatus, which receives it, the control data being generated by the information processing apparatus based upon the control information transferred to the information processing apparatus control means executes control process according to the data control received.

Abstract: A program driver means is disclosed that allows for the exchange of inforion between a NTDS device and a device having a bus topology, especially a VMEbus. The program driver utilizes chain commands which are fully programmable at the user level. The processor itself is programmed at the register level to assure the fastest data rate possible (32 bit access) across the VMEbus. The processor driver is invisible to the user.

Abstract: The mapping of playing objects from one game to another. In one embodiment, generic attributes of an object may be mapped to game-specific attributes. The mapping may either change or maintain the look and feel of an object. For example, a fast but lightly-armed starship in one game may be mapped to a quick but weak warrior in another game.

Abstract: An intermediate result signal arising from a manipulation of data signals is checked and reduced without using conditional branches, thereby improving instruction processing. Data signals are represented as signed 8-bit binary values in a two's compliment format. This requires that the intermediate result signal be stored in a register that is greater than 8-bits wide to allow for the proper checking of an overflow condition. A processor operating under program control with the program has the following operations. The program determines whether the intermediate result signal is in a positive overflow state or a negative overflow state. A first mask signal is set to have 8 lower bits in an OFF position when the intermediate result signal is inside the range of a signed 8 bit integer. Otherwise, the first mask signal is set to have 8 lower bits in an ON position.