Method of producing cache optimized code from a circuit compiler
Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's response to a large number of independent sets of circuit stimulus. The code is broken into separate modules which each simulate the circuit's operation during a particular clock phase. Loops within the code are limited in size to make efficient use of the computer's instruction cache and the data cache. Known constant nodes are propagated through the circuit before code is generated to eliminate the generation of unnecessary code. Code is only generated to simulate gates which may switch on a particular phase. Code which does not need to be evaluated during a particular phase is dropped. The circuit is broken into acyclic sets of gates and code is generated to iterate over each acyclic set of gates until stability is reached. A scoring function is used to prioritize which logic gate and which nodes are to be selected for code generation. Tri-state buffers are simulated using boolean operations. Drive-fight checking is also accomplished using boolean operations.
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Claims
1. A computer operable method for increasing the efficiency of computer code generated by a circuit compiler for simulating digital logic circuits on a computer, comprising the steps of:
- (a) generating computer code for execution on a computer with an instruction cache which simulates the operation of a digital logic circuit;
- (b) dividing said computer code into a plurality of segments comprised of a plurality of computer instructions wherein said plurality of computer instructions may be completely stored in said instruction cache; and
- (c) generating computer code which causes each of said segments to be executed a plurality of times, wherein each of said plurality of times said segment operates on a plurality of bits of a variable.
2. The method of claim 1, wherein step (a) further comprises generating computer code which operates on plurality of bits of said variable simultaneously.
3. The method of claim 2, wherein each of said plurality of bits of said variable represents a different simulation job.
4. The method of claim 3, wherein said variable is comprised of VS bits and said plurality of bits of a variable is WS bits, where WS is the number of bits in a general register of said computer and VS is an integer multiple of WS.
5. The method of claim 4, wherein step (b) further comprises maintaining a count of computer code statements and dividing said computer code into segments where said count exceeds a predetermined value.
6. The method of claim 5, wherein said computer code statements are computer instructions.
7. The method of claim 5, wherein said computer code statements are lines in a high level computer language.
8. The method of claim 1, wherein said computer further comprises a data cache, and wherein said computer code within each of said plurality of segments does not cause a data cache conflict with data referenced within that segment.
9. The method of claim 2, wherein said computer further comprises a data cache, and wherein said computer code within each of said plurality of segments does not cause a data cache conflict with data referenced within that segment.
10. The method of claim 3, wherein said computer further comprises a data cache, and wherein said computer code within each of said plurality of segments does not cause a data cache conflict with data referenced within that segment.
11. The method of claim 4, wherein said computer further comprises a data cache, and wherein said computer code within each of said plurality of segments does not cause a data cache conflict with data referenced within that segment.
12. The method of claim 8, further comprising the step of:
- (d) modelling said data cache with a model which indicates which data cache lines have been referenced.
13. The method of claim 12, wherein step (b) further comprises dividing said computer code into segments where said model indicates a data cache conflict will occur.
14. The method of claim 13, wherein said model is cleared after step (b).
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Type: Grant
Filed: Dec 5, 1996
Date of Patent: Jun 8, 1999
Assignee: Hewlett-Packard, Co. (Palo Alto, CA)
Inventor: Steven T. Mangelsdorf (Fort Collins, CO)
Primary Examiner: Vincent N. Trans
Attorney: Alexander J. Neudeck
Application Number: 8/759,585
International Classification: G06F 1750;
