Patents Examined by Vincent N. Trans
  • Patent number: 6470482
    Abstract: A system for interactive design, synthesis and simulation of an electronic system allowing a user to design a system either by specification of a behavioral model in a high level language such as VHDL or by graphical entry. The user can view full or partial simulation and design results simultaneously, on a single display window. The synthesis process uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is generally a series of transformations operating upon various levels of design representations. At each level, the design can be simulated and reviewed in schematic diagram form. The simulation results can be displayed immediately adjacent to signal lines on the diagram to which they correspond. In one embodiment, design rule violations are processed by an expert system to suggest possible corrections or alterations to the design which will eliminate the design rule violations.
    Type: Grant
    Filed: August 5, 1996
    Date of Patent: October 22, 2002
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Carlos Dangelo, Daniel R. Watkins
  • Patent number: 6324678
    Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: November 27, 2001
    Assignee: LSI Logic Corporation
    Inventors: Carlos Dangelo, Richard Deeley, Vijay Nagasamy, Manoucher Vafai
  • Patent number: 6212470
    Abstract: A vehicle route guidance system considers driver preferences, vehicle parameters such as speed and performance capabilities in a navigation computer, and outputs flexible guidance instructions based on these considerations. The system monitors vehicle parameters such as current location and speed with sensors such as an odometer (109), a compass (115), and a GPS receiver (113). The system also determines the location of a vehicle maneuver and then, considering the former attributes with a model free mechanism, in this case a navigation computer with fuzzy inferencing (101), communicates to the driver instructing him how to manoeuver.
    Type: Grant
    Filed: June 7, 1994
    Date of Patent: April 3, 2001
    Assignee: Motorola, Inc.
    Inventors: Leslie G. Seymour, Michael Barnea, Allan Kirson
  • Patent number: 6061506
    Abstract: A user definable closed computerized smart system to emulate the day-to-day continuous operation of business environments with minimal human intervention. A simple and efficient mechanism for defining and updating recurring business cyclical activities is provided. A system is provided for tracking all predefined pending activities and events, storing and retrieving appropriate information in a relational knowledge base. A delay-pending feature is taught that modifies pending activities and events, relative chronologically to other business activities and events. An expert feature for effectuating certain predictable logical and intuitive behavior based upon rules stored in a knowledge base is also provided. An update fields methodology is also provided for maintaining and changing data in individual knowledge base records on the basis of dynamically changing circumstances.
    Type: Grant
    Filed: August 29, 1995
    Date of Patent: May 9, 2000
    Assignee: Omega Software Technologies, Inc.
    Inventors: Graham Wollaston, Ray Farmer
  • Patent number: 6019496
    Abstract: A method for deriving a two-dimensional first-range data model at a distance, d, from a two-dimensional second-range data model at a distance, d.sub.0. The method (10) comprises the steps of first smoothing the second-range data model, I, by masking the second-range data model by a masking matrix (step 24) and next undersampling the smoothed second-range data model (step 26) to yield a first-range data model. Both steps for smoothing (step 24) and undersampling (step 26) use operators depending on the ratio of the first-range distance, d, to the second-range distance, d.sub.0. One aspect of the invention includes a distance relating system (80) that performs the smoothing step (step 24) and undersampling step (step 26) to generate first-range data models from second-range data models in an intelligent sensor system.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: February 1, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Kashipati G. Rao, Bruce E. Flinchbaugh
  • Patent number: 5993049
    Abstract: A method and system for determining a mass and energy balance for a glass furnace proceeds through a furnace model and calculates a number of parameters for the flows within each segment of the furnace. The mass flow rate, enthalpy, and enthalpy flow rate of each mass flow entering a segment is found and then the enthalpy and temperature of the unreacted mixture is determined. Based on an assumption that the flows entering a segment combust completely and instantaneously, the enthalpy, enthalpy flow rate, mass flow, composition, and temperature of a reacted flow exiting the segment is determined. If the furnace implements reburning, then the mass flows for the furnace are adjusted. Also, the mass and energy for each flow can be determined if the furnace has a regenerator, a recuperator, or a reburning system. Further, the mass and energy for each flow can be determined for a wide range of furnace types.
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: November 30, 1999
    Assignee: Gas Research Institute
    Inventor: Mark S. Sheldon
  • Patent number: 5993050
    Abstract: A model parameter extracting apparatus comprises a range designation unit, a combination designation unit, a simulator, a calibrator, a determination unit and a range update unit. The range update unit comprises a detection unit, a new range designation unit 28 and a range shift unit. The detection unit detects a model parameter capable of providing the slightest difference between a target characteristic value and an actual value, as a quasi-optimum value. The new range designation unit designates a numerical range having a half length of that of the previous adjustment range with the quasi-optimum value set at a center, as a new adjustment range. If the quasi-optimum value is a value at one end of the adjustment range, the range shift unit shifts the adjustment range such that the quasi-optimum value is at the other end of the adjustment range while maintaining the length of the adjustment range. The apparatus realizes automation of the re-setting of a model parameter.
    Type: Grant
    Filed: September 18, 1997
    Date of Patent: November 30, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Noriyuki Miura
  • Patent number: 5983202
    Abstract: An office-supplies management system includes: an office-supplies managing apparatus disposed together with office supplies in an office-supplies supplying area in which entrance and exit of members are controlled by an entering/exiting member control apparatus which is unlocked when a specific member identification code is inputted; and a plurality of terminals for members connected to the office-supplies managing apparatus through a network, wherein the office-supplies managing apparatus includes a stock-information storage unit for storing stock-related information such as information on a stock of office supplies which are supplied to the members, a function of updating the stock at the time of stocking-in and supplying for ascertaining codes of office supplies and updating stock information when the office supplies are replenished and stocked into the office-supplies supplying area, and when the office supplies are supplied, and a function of outputting stock information for outputting the stock-related
    Type: Grant
    Filed: April 3, 1996
    Date of Patent: November 9, 1999
    Assignee: Kokuyo Co., Ltd.
    Inventors: Tooru Yabe, Yoku Hoshino
  • Patent number: 5974248
    Abstract: A method for comparing intermediate test files having different file formats used to test integrated circuitry is provided. The method initially receives intermediate test files from an ATPG tool or a manually run simulation. The ATPG tool or manually run simulation provides data in a .wgl format for testing, and is a non-simulatable format, and the ATPG tool also provides a second intermediate file comprising a file or files in a simulatable format. All files contain event data used for testing. The intermediate test files are converted to files having a common format. The invention then compares the converted files to determine mismatches between the converted files. This comparison comprises evaluating the common format files and generating a pass/fail flag based on the results of the evaluation. Mismatches between the common format are corrected if the flag indicates that the files are not identical.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: October 26, 1999
    Assignee: LSI Logic Corporation
    Inventor: Stefan Graef
  • Patent number: 5970236
    Abstract: A circuit for selectively performing big-endian/little-endian data format conversion based on whether instructions or data are being transferred. The data and instructions are allocated to different regions in memory so that the big-endian/little-endian conversion is based on the source or destination address of the requested operation. Registers are provided to define a lower bound address and an upper bound address. In addition, a separate register is provided which indicates whether the data is stored between the lower bound and upper bound addresses or outside the lower bound and upper bound addresses. The registers are write addressable through the PCI configuration space, the memory space, and the I/O space, which allows the values in the registers to be changed dynamically during computer system operation.
    Type: Grant
    Filed: November 14, 1995
    Date of Patent: October 19, 1999
    Assignee: Compaq Computer Corporation
    Inventors: William C. Galloway, Ryan A. Callison
  • Patent number: 5963459
    Abstract: In an improvement over conventional finite element techniques, an ellipsoidal infinite element is used for the modeling of acoustic fields in exterior, fluid-filled domains surrounding a structure. This ellipsoidal infinite element is based on a multipole expansion that describes, to arbitrary accuracy, any scattered and/or radiated field exterior to an ellipsoid. Significantly, the respective eccentricities of the three elliptical cross sections of the ellipsoid can take values that are arbitrary and mutually independent. The ellipsoidal infinite element is readily incorporated in any structural or acoustic finite element code.
    Type: Grant
    Filed: March 6, 1997
    Date of Patent: October 5, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: David Storer Burnett, Richard Lovell Holford
  • Patent number: 5959871
    Abstract: There is disclosed a programmable analog or mixed analog/digital circuit. More particularly, this invention provides a circuit architecture that is flexible for a programmable electronic hardware device or for an analog circuit whose input and output signals are analog or multi-valued in nature, and primarily continuous in time. There is further disclosed a design for a current-mode integrator and sample-and-hold circuit, based upon Miller effect.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: September 28, 1999
    Assignee: Analogix/Portland State University
    Inventors: Edmund Pierzchala, Marek A. Perkowski
  • Patent number: 5949691
    Abstract: A logic circuit verification device comprising a data input section to read the circuit data and the circuit information of the logic circuits to be verified and converts them into the intermediate format, a corresponding point detection section to extract and output the information about the corresponding points using the corresponding point detection algorithm, a circuit partitioning section to read the intermediate format data and partition the logic circuits according to the corresponding point information obtained by the corresponding point detection section so as to prepare circuit data of the subcircuits and a equivalence checking section to read the circuit data of the subcircuits, determine the subcircuits to be compared with referring to the corresponding point information obtained by the corresponding point detection section and comparatively compares the circuit data of the subcircuits.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: September 7, 1999
    Assignee: NEC Corporation
    Inventors: Hitoshi Kurosaka, Hideyuki Emura, Naotaka Maeda
  • Patent number: 5933620
    Abstract: A method and apparatus for providing a microprocessor serial number. A small, nonvolatile random access memory is packaged with the CPU die to provide a storage space for a CPU serial number which can be programmed before leaving the factory. Both the CPU die and the nonvolatile RAM die reside within the cavity of the package. Connection between the two die is provided by conventional wire bonding.
    Type: Grant
    Filed: March 28, 1996
    Date of Patent: August 3, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sherman Lee, James R. MacDonald, Michael T. Wisor
  • Patent number: 5933356
    Abstract: A system and method are provided herein for creating and validating an electronic design structural description of a circuit or device from a VHDL description of the circuit or device which includes a compiler for compiling the VHDL description of the circuit or device; a device for locating problems within the compiled description and measuring the effectiveness of solving the problems; a device for passing information including the compiled description to a physical design level; a physical design tool for receiving the information and creating a physical design therefrom; and a device for back annotating the information from the physical design tool to the compiler.
    Type: Grant
    Filed: November 5, 1996
    Date of Patent: August 3, 1999
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Carlos Dangelo, Owen S. Bair
  • Patent number: 5930151
    Abstract: In an optimum placement method of circuit blocks in a semiconductor integrated circuit, from a given initial placement of circuit blocks, a new initial placement is prepared on the basis of connection information of the circuit blocks, by placing circuit blocks as many as possible, in the form of a single stream of circuit blocks in which each circuit block is connected to only an adjacent circuit block but is not connected to a not-adjacent circuit block. From the circuit blocks included in the new initial placement, there is found out a connection destination circuit block of a not-yet-placed circuit block which is not included in the new initial placement, and then, the not-yet-placed circuit block is inserted to a best position adjacent to the connection destination circuit block, thereby to temporarily determine the placement of all circuit blocks. Thereafter, only the circuit blocks in the proximity of the inserted circuit blocks is replaced to finally determine the best placement of all circuit blocks.
    Type: Grant
    Filed: June 4, 1997
    Date of Patent: July 27, 1999
    Assignee: NEC Corporation
    Inventor: Masaki Uyama
  • Patent number: 5923565
    Abstract: The present invention provides a computer implemented method and apparatus for determining the total capacitance of a primary interconnect line positioned between top and bottom ground planes. The primary interconnect line is positioned at a distance, H1, from the bottom ground plane and at a distance, H2, from the top ground plane. Preferred embodiments of the present invention include computer implemented processes for empirically determining the total capacitance of the primary interconnect line both with and without neighboring interconnect lines present. Core steps of the present invention include partitioning of a parameter representing fringe capacitance which is due to fringe electric fields induced between sidewalls of the primary interconnect line and the top and bottom ground planes. In the present invention, the fringing capacitance is partitioned into a top fringe capacitance, C.sub.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: July 13, 1999
    Assignee: VLSI Technology, Inc.
    Inventors: Morgan Paul Smith, Paul Raj Findley
  • Patent number: 5920492
    Abstract: A method of using a computer to provide display data representing a fire. The data is derived from fire model data, so that the fire is realistically displayed with the dynamics of a real fire. Particles are generated from the model data and given location values and other parameters. Each particle becomes a display data element by virtue of being assigned a graphics primitive. The data elements are culled according to a field of view and sorted, so that they may be used for real time display rendering.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: July 6, 1999
    Assignee: Southwest Research Institute
    Inventors: Bruce C. Montag, Stephen D. Huffman, Denise C. Varner
  • Patent number: 5920490
    Abstract: A logic simulation monitoring system to verify a test stimulus set and generate a test vector set for use on an Automatic Test Equipment (ATE) device during manufacturing tests. The simulation monitor executes unobtrusively as part of the logic simulation to monitor the logic simulation's real time signal activity including contention checks, output strobe margins, and ATE compatibility checks, in addition to extracting the appropriate signal response or vector resulting from a given stimulus. The simulation monitor comprises at least one simulation monitor code block generated from a combination of values from an integrated circuit parameter file and at least one code block template. Output from the simulation monitor includes a report of the contention errors and input signal errors, and a test vector set comprised of the input test stimulus set used with the logic simulation and the stimulus responses resulting from the logic simulation all in an ATE compatible and ready to use format.
    Type: Grant
    Filed: December 26, 1996
    Date of Patent: July 6, 1999
    Assignee: Adaptec, Inc.
    Inventor: Michael J. Peters
  • Patent number: 5917730
    Abstract: A computer architecture for executing a simulation model which describes characteristics of a physical system. The computer architecture includes an editor processor that prompts a user to define a graphical object (GO) representing static properties of the physical system, and that prompts the user to define dynamic variables of the physical system. The computer architecture also includes a compiler for binding the dynamic variables of the physical system to a physical data source. The physical data source provides dynamic properties of the physical system over time as values for the dynamic variables. The computer architecture also includes a run time processor that executes the simulation model and displays the graphical object with the dynamic properties of the physical system.
    Type: Grant
    Filed: August 16, 1996
    Date of Patent: June 29, 1999
    Assignee: GSE Process Solutions, Inc.
    Inventors: Kevin J. Rittie, Michael Chmilewski, Jeff Walsh, Alan MacAnespie