Power supply device for plasma processing

- Solvix GmbH

A power supply device for plasma processing, wherein electric arcs may occur, comprises a power supply circuit for generating a voltage across output terminals, and a first switch connected between the power supply circuit and one of the output terminals. According to a first aspect the power supply device comprises a recovery energy circuit connected to the output terminals and to the power supply circuit. According to a second aspect the power supply device comprises an inductance circuit including an inductor and a second switch connected parallel to the inductor. According to a third aspect the power supply device comprises a controller for causing the power supply circuit and the first switch to be switched on and off. The controller is configured to determine a quenching time interval by means of a self-adaptive process. The quenching time interval defines the time interval during which, in an event of an arc, no voltage is generated across the output terminals.

Skip to: Description  ·  Claims  ·  References Cited  · Patent History  ·  Patent History
Description
CROSS REFERENCE TO RELATED APPLICATIONS

This is a division of U.S. patent application Ser. No. 12/701,813, filed Feb. 8, 2010, which claims the foreign priority of European Patent Application No. 09405031.7, filed Feb. 17, 2009 in the names of Albert BULLIARD, Benoit FRAGNIERE, Joel OEHEN, and Olivier CARDOU and entitled A POWER SUPPLY DEVICE FOR PLASMA PROCESSING, the disclosures of which are incorporated by reference herein.

FIELD OF THE INVENTION

The invention concerns a power supply device for plasma processing.

BACKGROUND OF THE INVENTION

There are variety of processes in which a plasma is generated to deposit and/or to remove material. Examples are the process of sputtering, where material is removed from a target and deposited on a substrate in order to produce e.g. a thin film, or the process of etching, where atoms are removed in order to create e.g. a very clean surface.

To produce the plasma, a high voltage is generated between electrodes by means of a suitable power supply device. However, the processing conditions may be such that there is a sudden electrical discharge for instance between the electrodes which causes the occurrence of one or more arcs. Normally, such arc events are to be prevented since they may lead e.g. to damages in the target or to a poor quality of the surface to be processed.

It is widely known to use a switch for interrupting the power supply to the electrodes when an arc event occurs (see e.g. U.S. Pat. Nos. 5,192,894 or 6,621,674 B1). However, interruption of the power supply gives rise to the problem that the energy which is stored e.g. in the cables at the time of interruption is supplied to the plasma, which may impede a quick quenching of the arc. Eventually, the duration until the plasma processing is in an arc-free condition and operates normally may be prolonged.

The patent application US 2004/124077 A1 refers to a power supply which is suitable in the field of so-called HiPIMS (“High Power Impulse Magnetron Sputtering”). The power supply, which produces very short pulses of extremely high power, is provided with a capacitor that is repetitively charged and then discharged through an inductor. When an arc is detected, the capacitor is first disconnected from the inductor by actuating a first switch and then connected to the inductor again by actuating two other switches such that the energy contained in the inductor is recycled to the capacitor. Compared to this recycled energy, the energy contained in any cables connecting the output terminals of the power supply with the plasma processing chamber is negligible. Thus, no measures are provided to recover this energy in the cables.

In the patent application US 2008/309402 A1, it is proposed to use a pre-charging/discharging cicuit for pre-charging a capacitor under normal operating conditions. When an arc is detected, an amount of the residual energy which is stored in the cables leading to the plasma processing chamber is transferred into the capacitor and finally eliminated by means of the pre-charging/discharging circuit before the power is applied again to the plasma processing chamber. Thus, the energy is finally lost, which makes the operation inefficient.

Apart from the problem of the energy in the cables, another problem impeding an efficient handling of arcs may arise when the time of interruption of the power supply is not optimal, e.g. the time is too short to quench an arc.

In the patent U.S. Pat. No. 6,621,674 B1, it is proposed to adjust the time interval during which the voltage is applied to the electrodes in an adaptive manner, whereas the time interval during which the voltage is disconnected is kept constant.

SUMMARY OF THE INVENTION

One object of the present invention is to provide a power supply device for plasma processing which allows the handling of arc events in a more efficient way.

According to a first aspect of the invention this object is achieved with a power supply device comprising a recovery energy circuit for feeding at least partially the energy back which is stored in the conductors when the power supply to the plasma processing chamber is interrupted. The power supply circuit is configured to reuse the energy fed back at least partially for the power supplied to the plasma processing chamber.

According to a second aspect of the invention there is provided a power supply device comprising a first switch and an inductance circuit that comprises an inductor and a second switch. The first switch is arranged outside of the inductance circuit and the second switch is connected parallel to the inductor.

According to a third aspect of the invention there is provided a power supply device comprising a controller being configured to determine a quenching time interval by means of a self-adaptive process. The quenching time interval defines the time interval during which, in an event of an arc, no voltage is generated across the output terminals of the power supply device.

Each of the three aspects has the advantage that arcs which occur in the plasma processing chamber can be handled in a more efficient way.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject invention will now be described in terms of its preferred embodiments. These embodiments are set forth to aid the understanding of the invention, but are not to be construed as limiting.

FIG. 1 shows an embodiment of a plasma processing installation including a power supply device according to the invention,

FIG. 2 to 5 show various embodiments of the inductance circuit of the power supply device of FIG. 1,

FIG. 6 shows an alternative embodiment of the energy recovery circuit of the power supply device of FIG. 1,

FIG. 7 shows the temporal development of U, I and I22, where U is the voltage between the electrodes, I the current passing through the electrodes, and I22 the current passing through the branch parallel to the inductor of the power supply device of FIG. 1,

FIG. 8 shows schematically the state of the installation of FIG. 1 in a first time interval t0-t2,

FIG. 9 shows schematically the state of the installation of FIG. 1 in a second time interval t2-t4,

FIG. 10 shows schematically the state of the installation of FIG. 1 in a third time interval t4-t5,

FIG. 11 shows schematically the state of the installation of FIG. 1 in a fourth time interval t7-t9,

FIG. 12 shows a first example of the temporal development of |U| (absolute value of the voltage between the electrodes) and of I (current passing through the electrodes) for the case that the plasma recovers after one arc event only,

FIG. 13 shows a second example of the temporal development of |U| and of I, and

FIG. 14 shows a third example of the temporal development of |U| and of I as well as the corresponding switching states of the power supply circuit and the serial switch of the power supply device of FIG. 1.

 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a plasma processing installation including a power supply device having output terminals 1 and 2, which are connected to a plasma processing chamber 7 by means of a pair of wires 3, 4 forming e.g. a cable. The output terminals 1, 2 are normally located outside of the housing of the power supply. The processing chamber 7 is designed to produce a plasma therein for accomplishing the desired process such as deposition or etching of a material. Electrodes 5 and 6 are located at the end of the wires 3, 4. The negative electrode 5 (“cathode”) is connected to a target 8 located inside the processing chamber 7. The positive electrode 6 (“anode”) is connected e.g. to the housing of the processing chamber 7 or to an internal electrode. During the processing operation a voltage U is developed across the electrodes 5 and 6. As the case may be, there is also a substrate (not shown) located inside the processing chamber 7.

The power supply device comprises a power supply circuit 10 to produce a DC voltage across the terminals 16 and 17. In the embodiment shown in FIG. 1 the power supply circuit 10 comprises an AC input 11, which is e.g. connected to the power supply network, a first rectifier 12, a switching circuit 13, a transformer 14 and a second rectifier 15. The switching circuit 13 includes e.g. a H-bridge with switches which are controlled by a controller 60.

The first terminal 16 of the power supply circuit 10 is connected via an inductor 21 and a serial switch 25 to the negative output terminal 1. The switch 25 is e.g. a transistor such as an IGBT and is controlled by the controller 60.

The second terminal 17 is connected to the positive output terminal 2 and via a capacitor 27 to the first terminal 16. The inductor 21 limits the temporal variation of the current, dI/dt, during an arc event (see the moderate slope of curve 71 in FIG. 7 in the time interval t1-t2). The capacitor 27 serves for storing energy.

A switch 22 is arranged parallel to the inductor 21. The switch 22 is e.g. a transistor, such as an IGBT or a power MOSFET and is controlled by the controller 60.

FIG. 2 shows an example of a switch 22 being composed of a power MOSFET 22′ having a serial diode 23, which serves as a freewheeling diode.

In case that the switch 22 is an IGBT 22″ as shown in FIG. 3 to 5, there is preferably provided an overvoltage protection in form of a component which is connected parallel to the switch 22. This component may be e.g. a voltage suppressor, such as a Zener diode 24 as shown in FIG. 3 or a TVSS (Transient Voltage Surge Suppressor) 24′ as shown in FIG. 4, a power resistor 24″ as shown in FIG. 5, or any other suitable means for protecting the switch 22 against an overvoltage.

In case that the switch 22 is an avalanche rated power MOSFET, it has an inherent overvoltage protection.

An overvoltage may e.g. occur in the case that the plasma does not re-ignite after the switch 25 has been closed again and the switch 22 is opening after an arc event, so that the voltage across the inductor 21 is increased, or in the case that—due to a malfunction—the switch 25 is opening when the switch 22 is opened.

In the embodiment shown in FIG. 1, the components 21, 22 form an inductance circuit 20 which is arranged between the terminals 16 and 1 and is thus integrated in the negative branch of the circuit. Alternatively, the inductance circuit 20 can be integrated in the positive branch by arranging it between the terminals 17 and 2 or it is conceivable to provide each branch with an inductance circuit 20.

The power supply device shown in FIG. 1 further comprises a plasma floating potential neutralizing circuit 30 (in the following denoted by “PFPN circuit”) connected to the negative terminal 1 and the positive terminal 2 and an energy recovery circuit 40 arranged between the output terminals 1, 2 and the power supply circuit 10.

The PFPN circuit 30 comprises a diode 31 and a switch 32. The switch 32 is e.g. a transistor such as an IGBT and is controlled by the controller 60.

The energy recovery circuit 40 comprises a first line 41 which connects the negative output terminal 1 via a diode 45 to the primary winding 46a of a transformer 46, a second line 42 which connects the positive output terminal 2 to the primary winding 46a of the transformer 46, a third line 43 which connects the secondary winding 46b of the transformer 46 via a diode 47 to a first input terminal 18 of the power supply circuit 10, and a fourth line 44 which connects the secondary winding 46b of the transformer 46 to a second input terminal 19 of the power supply circuit 10.

The power supply circuit 10 comprises a capacitor 9, which is connected to the first input terminal 18 and the second input terminal 19. Thus, the power supply circuit 10 is suitable to reuse the energy which is fed back via the energy recovery circuit 40 at least partially for the power supplied to the plasma processing chamber 7.

In an alternative embodiment the energy recovery circuit 40′ is designed as shown in FIG. 6 by providing a DC-DC converter 48 whose input is connected to the lines 41, 42 and whose output is connected to the lines 43, 44, and a capacitor 49 which is connected to the input of the DC-DC converter 48.

The power supply device shown in FIG. 1 further comprises an arc detection circuit 61 for detecting the occurrence of an arc condition and for generating an arc detection signal which is processed by the controller 60. The arc detection circuit 61 measures e.g. the current through the negative or positive branch and the voltage across the two output terminals 1, 2.

In the following the operation of the power device is explained in more detail. In the event that an arc occurs, the controller 60 controls the switches 22, 25, and 32 to activate the circuits 20, 30, and 40 such that the arc is suppressed and/or quenched and the normal operation mode is recovered in an efficient way.

In the following, successive instances of time t are referred to as t0, t1, t2, etc. The following table summarizes the successive states of the switches 22, 25, and 32, where “OFF” means that the switch is open and “ON” means that the switch is closed. For some of time intervals the switches 22 and 32 may be either ON or OFF (denoted in the table by “or”). In case of transistors, a switch 22, 25, or 32 is “ON”, when it is in the conducting state, and “OFF”, when it is in the non-conducting state.

switch 22 of serial switch 32 of time interval circuit 20 switch 25 circuit 30 t0-t1 ON or OFF ON OFF t1-t2 ON or OFF ON OFF t2-t3 ON OFF OFF t3-t4 ON OFF OFF or ON t4-t5 ON OFF ON t5-t6 ON OFF OFF t6-t7 ON ON OFF t7-t8 OFF ON OFF t8-t9 OFF ON OFF t9-t10 ON or OFF ON OFF

By actuating the switches 22, 25, 32, the voltage U between the target 8 and the positive electrode 6 and the current I passing through the electrodes 5 and 6 change in time.

FIG. 7 shows an example of the temporal development of the voltage U (solid curve 70) and the temporal development of the current I (solid curve 71), when an arc event occurs. The dotted line 72 indicates the temporal development of the current I22 flowing through the parallel branch 22 of the inductance circuit 20.

At time t0 the plasma processing is in the normal operation mode, where material in the processing chamber 7 is deposited or etched according to the setup of the plasma processing installation. The voltage U has a value which is in the present example negative. The switch 22 is open or closed, the switch 32 is open, and the switch 25 is closed. Thus, there is a current flowing from the terminal 17 through the wire 4 and the plasma in the processing chamber 7 back to the terminal 16 via the wire 3. This is schematically shown in FIG. 8, where the direction of this current is indicated by the arrows 80.

At time t1 an electric arc occurs in the processing chamber 7, which has the effect that the voltage U tends to zero, whereas the current I increases (see the curves 70 and 71 between the two instants of time t1 and t2 in FIG. 7). The inductor 21 limits the temporal variation of I, so that the slope dI/dt is moderate. The change of voltage, U0, may be e.g. in the range of several tens V to several hundreds V.

At time t2 the arc detection circuit 61 detects the arc occurrence in the processing chamber 7 and produces an arc detection signal causing the controller 60 to close the switch 22 and to open the switch 25. The energy in the wires 3, 4 at the time t2 is approximately given by Lc·I2/2, where Lc is the inductance of the wires 3, 4. The current originating from the energy in the wires 3, 4 begins to flow via the energy recovery circuit 40 to the power supply circuit 10, where it is stored in the capacitor 9. This is schematically shown in FIG. 9, where the direction of this current is indicated by the arrows 81. At the same time the current stored in the inductor 21 flows through the switch 22 as indicated by arrows 82 in FIG. 9.

Referring back to FIG. 7, it can be seen that at time t2 the voltage U changes its polarity and reaches a certain level ULc due to the energy in the wires 3, 4. The level ULc corresponds to the voltage between the lines 41 and 42 and defines the decay time τ of the current I, which is given by τ=Lc·I/ULc.

As can be seen from FIG. 7, the voltage U remains substantially at the level ULc in the time interval t2-t4, whereas the current I tends to zero. t3 indicates the instant of time, when the switch 32 is closed. t4 indicates the instant of time, when the recovery of the energy from the wires 3,4 is finished. It is conceivable to predefine t3 such that the switch 32 is closed before or after t4.

In FIG. 7 the dashed line 71′ in the time interval t4-t5 indicates the situation, where there is still plasma surrounding the target 8. By closing the switch 32 at time t3 the PFPN circuit 30 becomes active to shorten the time in which the arc is burning. Any electrons near the target 8 are caught, causing a current flowing through the PFPN circuit 30 as indicated by arrows 83 in FIG. 10. Thereby, the plasma floating potential (potential to which the target 8 is charged due to the plasma alone) decreases and the arc cannot be self-sustained anymore. The diodes 31 and 45 act as selective switches: Since the currents 81 and 83 are in opposite directions, the current 83 will flow through the closed switch 32, as soon as the energy in the wires 3, 4 causing the current 81 is fed back to the power supply circuit 10.

At time t5 the switch 32 is opened. t5 is chosen such that the arc is unlikely to reoccur.

At time t6, which may be shortly after t5, the switch 25 is closed which has the effect that the power of the power supply circuit 10 is supplied again to the electrodes 5 and 6. At the same time, the current 82 circulating in the switch 22 will pass progressively through the plasma. The voltage U across the electrodes 5 and 6 goes back to a negative value, whereas the current I increases again (see time interval t6-t7 of curves 70 and 71 in FIG. 7).

At time t7, the switch 22 is opened, such that the remaining current 82 flowing through the switch 22 is forced to flow into the plasma, which accelerates the process of recovering the plasma. The voltage U changes further by an amount of U22, which is the voltage across the switch 22 at time t7, whereas the current I increases further. If the switch 22 is a transistor which is apt to operated in the avalanche mode, it is possible to dissipate the energy of this residual current 82, such that not all of this energy has to be absorbed by the plasma. (See FIG. 11, in which the switch 22 is indicated by the inherent avalanche diode of the MOSFET.) The provision of switch 22 has the advantage that a runaway current can be prevented, i.e. a current which is accumulated during successive actuations of the switch 25 and which may have the effect that the arcs get more and more energy. The switch 22 is actuated such that it is closed when the switch 25 is open, and open during a time interval which is long enough such that the current 82 flowing through the freewheeling diode 23 of the switch 22 has vanished.

At time t8, the arc detection circuit 61 checks whether the conditions for an arc are still met. (This is not the case in the example shown in FIG. 7.)

At time t9, the current flowing through the inductor 21 corresponds to the current I passing through the plasma and the switch 22 may be closed again.

At time t9, the plasma processing is in the normal operation mode as it was at time t0.

In the following an example of detecting and quenching an arc and its timing are discussed. The arc detection circuit 61 is designed such that it generates an arc detection signal when at least one of the following conditions is met (in the following denoted by “arc conditions”):

1. The current I in the plasma exceeds a certain value I1,

2. the absolute value of the voltage between the electrodes 5 and 6 (denoted by |U|) drops by a certain amount U0 while at the same time the current I in the plasma is above a certain minimum value I2,

3. the absolute value of the voltage |U| falls below a threshold U1 while at the same time the current I is above a certain minimum value I3.

In the present embodiment the minimum values I2 and I3 are set to be equal.

The controller 60 is adapted to receive various parameters for operating the power supply device which may be set by the user. Optionally, the controller 60 may be designed such that the operating parameters are variable in time by using a self-adaptive process to set one or more of the operating parameters during operation. The operating parameters comprises e.g. the voltage change U0 or the thresholds U1, I1 and I2 for arc detection, which are used by the arc detection circuit 61, and the various time intervals (delays) for controlling the switches 22, 25, 32 and the bridge circuit 13. Examples of such delay parameters are:

D1: time interval during which the power supply device tries to quench an arc before the bridge circuit 13 is switched off. Thus, D1 defines the number of times the switch 25 is, in an event of an arc, actuated before the power supply circuit 10 is switched off.

D2: time interval during which the bridge circuit 13 is switched off.

D3: time interval when the switch 25 is open. D3 corresponds to the interval t2-t6 in the example of FIG. 7.

D4: time interval during which the arc conditions are to be met before the switch 25 is opened. D4 corresponds to the interval t1-t2 in the example of FIG. 7.

D5: time interval between the closing of switch 25 and the checking step whether the plasma condition is met, i.e. whether the arc event is over. D5 corresponds to the interval t6-t8 in the example of FIG. 7.

As already mentioned above, the parameters may be variably set by a self-adaptive process. For example, the threshold U1 can be given by the average plasma voltage |U| plus a predefined valued. The delays D2 and D3 define the quenching time interval during which, in an event of an arc, no voltage is generated across the output terminals 1, 2.

The delay D3 may be set by means of the self-adaptive process such that D3 is increased if the plasma does not recover after one cycle of actuating the switches 22, 25, 32 to quench the arc.

FIG. 12 shows a first example of the temporal development of |U| (solid curve) and I (dash-dotted curve). The example is similar to the example shown in FIG. 7. At time t8, i.e. after one cycle of actuating the switches 22, 25, 32, the voltage |U| is greater than U1 and the current I is less than I1. The arc conditions are not met anymore. Thus, the plasma processing is in the normal operation mode again.

FIG. 13 shows a second example of the temporal development of |U| (solid curve) and I (dash-dotted curve). In this example the delay D3 is set by means of a self-adaptive process. At time t8, i.e. after one cycle of actuating the switches 22, 25, 32, the voltage |U| is still less than U1 and the current I is greater than I2. The arc conditions are still met. The delay D3 is increased. At time t11, i.e. after the second cycle of actuating the switches 22, 25, 32, the arc conditions are not met anymore and the plasma processing changes to the normal operation mode.

FIG. 14 shows a third example of the temporal development of |U| (solid curve) and I (dash-dotted curve). In this example the arc conditions are still met at time t11, i.e. after two cycles of actuating the switches 22, 25, 32. In this example the time interval D1 has expired, which means that there is no other try to quench the arc. The power supply circuit 10 is switched off by switching off the bridge circuit 13, such that no power is supplied to the terminals 16, 17 for the time delay D2. At time t12 another cycle of actuating the switches 22, 25, 32 and the circuit 10 is started to re-ignite the plasma. The successive switching off and on of the power supply circuit 10 and the switch 25 is indicated in the lower diagram in FIG. 14.

The power supply device according to the invention is suitable for any plasma processing operation, such as sputtering, PECVD (Plasma Enhanced Chemical Vapour Deposition), etching, etc. The plasma processing operation may include usual materials as well as materials which are difficult to be processed such as zinc oxide (ZnO) or aluminum-doped zinc oxide (AZO).

The power supply device according to the invention has the advantage that when the power to the processing chamber is interrupted, less energy is involved in the arc occurrence. Thereby, the arc can be quenched quickly and the risk of damaging the target (and/or substrate when present) is reduced. In addition, it has been found that possible consecutive arcs are suppressed in an efficient way, such that the number of arc events is reduced.

Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.

Claims

1. A power supply device for plasma processing, wherein electric arcs may occur, the power supply device comprising:

a power supply circuit for generating a voltage across output terminals;
said output terminals for connection via conductors to a plasma processing chamber;
a first switch connected between said power supply circuit and one of said output terminals for interrupting the power supply to said plasma processing chamber in case of an occurrence of an arc; and
an inductance circuit arranged between said power supply circuit and one of said output terminals, and the inductance circuit comprises an inductor and a second switch,
wherein said first switch is arranged outside of said inductance circuit, and said second switch is connected parallel to said inductor.

2. The power supply device according to claim 1, wherein at least one of said first switch and said second switch is an IGBT, a power MOSFET or another kind of transistor.

3. The power supply device according to claim 1, wherein said second switch is a transistor being apt to be operated in the avalanche mode.

4. The power supply device according to claim 1, wherein said inductance circuit further comprises an overvoltage protection module for protecting said second switch from overvoltage.

5. The power supply device according to claim 1, further comprising:

a second inductance circuit arranged between said power supply circuit and one of said output terminals,
wherein said second inductance circuit comprises a second inductor and a third switch connected parallel to said second inductor.

6. The power supply device according to claim 1, further comprising:

an arc detection circuit for detecting arc events in said plasma processing chamber, said arc detection circuit being configured to determine at least one of the following criteria defining an arc event:
a current I through electrodes, between which the plasma is generated, exceeds a given value I1;
an absolute value of the voltage, |U|, across said electrodes drops by a given amount U0, while said current I is above a given minimum value I2; and
|U| falls below a threshold U1 while said current I is above a given minimum value I3.

7. The power supply device according to claim 1, further comprising a floating potential neutralizing circuit connected to said output terminals for reducing the floating potential which is produced on at least one of a target and a substrate located in said plasma processing chamber after said first switch is actuated to interrupt the power supply to said plasma processing chamber.

8. The power supply device according to claim 7, wherein said floating potential neutralizing circuit comprises a third switch with a serial diode connected to said output terminals.

9. The power supply device according to claim 1, wherein said power supply circuit is designed to generate a continuous DC voltage or a pulsed DC voltage across said output terminals.

Referenced Cited
U.S. Patent Documents
3867669 February 1975 Krasik et al.
4271369 June 2, 1981 Stillwagon
4276507 June 30, 1981 Stillwagon
4299678 November 10, 1981 Meckel
4428023 January 24, 1984 Maier
4459629 July 10, 1984 Titus
4484243 November 20, 1984 Herbst et al.
4540607 September 10, 1985 Tsao
4557819 December 10, 1985 Meacham et al.
4585986 April 29, 1986 Dyer
4589123 May 13, 1986 Pearlman et al.
4740858 April 26, 1988 Yamaguchi et al.
4792730 December 20, 1988 Mintchev et al.
4870529 September 26, 1989 Powell et al.
4871421 October 3, 1989 Ogle et al.
4901621 February 20, 1990 Tidman
4936960 June 26, 1990 Siefkes et al.
4999760 March 12, 1991 Tietema
5192894 March 9, 1993 Teschner
5241152 August 31, 1993 Anderson et al.
5275083 January 4, 1994 Hawke et al.
5281321 January 25, 1994 Sturmer et al.
5286360 February 15, 1994 Szczyrbowski
5303139 April 12, 1994 Mark
5307004 April 26, 1994 Carsten
5377218 December 27, 1994 Guenther
5415757 May 16, 1995 Szczyrbowski et al.
5418707 May 23, 1995 Shimer et al.
5427669 June 27, 1995 Drummond
5488535 January 30, 1996 Masghati et al.
5517085 May 14, 1996 Engemann et al.
5535906 July 16, 1996 Drummond
5573596 November 12, 1996 Yin
5576939 November 19, 1996 Drummond
5584972 December 17, 1996 Lantsman
5584974 December 17, 1996 Sellers
5611899 March 18, 1997 Maass
5616224 April 1, 1997 Boling
5645698 July 8, 1997 Okano
5651865 July 29, 1997 Sellers
5682067 October 28, 1997 Manley et al.
5698082 December 16, 1997 Teschner et al.
5708250 January 13, 1998 Benjamin et al.
5718813 February 17, 1998 Drummond et al.
5725675 March 10, 1998 Fong et al.
5731565 March 24, 1998 Gates
5750971 May 12, 1998 Taylor
5814195 September 29, 1998 Lehan et al.
5815388 September 29, 1998 Manley et al.
5851365 December 22, 1998 Scobey
5855745 January 5, 1999 Manley
5864471 January 26, 1999 Kammiller
5882492 March 16, 1999 Manley et al.
5889391 March 30, 1999 Coleman
5917286 June 29, 1999 Scholl et al.
6001224 December 14, 1999 Drummond
6005218 December 21, 1999 Walde et al.
6024844 February 15, 2000 Drummond et al.
6046641 April 4, 2000 Chawla
6080292 June 27, 2000 Matsuzawa et al.
6135998 October 24, 2000 Palanker
6161332 December 19, 2000 Avot
6162332 December 19, 2000 Chiu
6174450 January 16, 2001 Patrick et al.
6176979 January 23, 2001 Signer et al.
6217717 April 17, 2001 Drummond et al.
6222321 April 24, 2001 Scholl et al.
6238513 May 29, 2001 Arnold et al.
6258219 July 10, 2001 Mueller
6321531 November 27, 2001 Caren et al.
6332961 December 25, 2001 Johnson et al.
6365009 April 2, 2002 Ishibashi
6416638 July 9, 2002 Kuriyama et al.
6433987 August 13, 2002 Liptak
6440281 August 27, 2002 Sturmer
6447655 September 10, 2002 Lantsman
6447719 September 10, 2002 Agoamohamadi et al.
6472822 October 29, 2002 Chen et al.
6484707 November 26, 2002 Frus et al.
6507155 January 14, 2003 Barnes et al.
6521099 February 18, 2003 Drummond et al.
6522076 February 18, 2003 Goedicke et al.
6524455 February 25, 2003 Sellers
6552295 April 22, 2003 Markunas et al.
6577479 June 10, 2003 Springer et al.
6621674 September 16, 2003 Zahringer et al.
6636545 October 21, 2003 Krasnov
6708645 March 23, 2004 Choquette
6736944 May 18, 2004 Buda
6740207 May 25, 2004 Kloeppel et al.
6753499 June 22, 2004 Yasaka et al.
6808607 October 26, 2004 Christie
6817388 November 16, 2004 Tsangaris
6876205 April 5, 2005 Walde et al.
6878248 April 12, 2005 Signer et al.
6879870 April 12, 2005 Shannon et al.
6894245 May 17, 2005 Hoffman et al.
6943317 September 13, 2005 Ilic et al.
6967305 November 22, 2005 Sellers
6974550 December 13, 2005 Benjamin et al.
7015703 March 21, 2006 Hopkins et al.
7026174 April 11, 2006 Fischer
7030335 April 18, 2006 Hoffman et al.
7081598 July 25, 2006 Ilic et al.
7086347 August 8, 2006 Howald et al.
7095179 August 22, 2006 Chistyakov
7132618 November 7, 2006 Hoffman et al.
7169256 January 30, 2007 Dhindsa et al.
7179987 February 20, 2007 Farth et al.
7247218 July 24, 2007 Hoffman
7247221 July 24, 2007 Stowell, Jr.
7261797 August 28, 2007 Sellers
7265619 September 4, 2007 Tayrani
7292045 November 6, 2007 Anwar et al.
7305311 December 4, 2007 van Zyl
7471047 December 30, 2008 Ogawa
7498908 March 3, 2009 Gurov
7503996 March 17, 2009 Chen et al.
7514377 April 7, 2009 Sato et al.
7514935 April 7, 2009 Pankratz
7531070 May 12, 2009 Kuriyama et al.
7553679 June 30, 2009 Hoffman
7567037 July 28, 2009 Setsuhara et al.
7651492 January 26, 2010 Wham
7761247 July 20, 2010 van Zyl
8044594 October 25, 2011 Morgan et al.
8217299 July 10, 2012 Ilic et al.
8395078 March 12, 2013 Ilic
20010047933 December 6, 2001 Lantsman
20020104753 August 8, 2002 Kloeppel et al.
20020108933 August 15, 2002 Hoffman et al.
20020170678 November 21, 2002 Hayashi et al.
20030136766 July 24, 2003 Hoffman et al.
20030146083 August 7, 2003 Sellers
20030192475 October 16, 2003 Shannon et al.
20030205460 November 6, 2003 Buda
20030205557 November 6, 2003 Benjamin et al.
20040026235 February 12, 2004 Stowell, Jr.
20040027209 February 12, 2004 Chen et al.
20040055881 March 25, 2004 Christie
20040124077 July 1, 2004 Christie
20040149699 August 5, 2004 Hofman et al.
20040182696 September 23, 2004 Kuriyama
20040182697 September 23, 2004 Buda
20040191950 September 30, 2004 Nakamura et al.
20040226657 November 18, 2004 Hoffman
20040245999 December 9, 2004 Walde et al.
20040252527 December 16, 2004 Serge
20050035770 February 17, 2005 Hopkins et al.
20050040144 February 24, 2005 Sellers
20050092596 May 5, 2005 Kouznetsov
20050167262 August 4, 2005 Sellers
20050236377 October 27, 2005 Hoffman et al.
20050258148 November 24, 2005 Condrashoff
20050264218 December 1, 2005 Dhindsa et al.
20060011591 January 19, 2006 Sellers
20060049831 March 9, 2006 Anwar et al.
20060054601 March 16, 2006 Ilic et al.
20060057854 March 16, 2006 Setsuhara et al.
20060066248 March 30, 2006 Chistyakov
20060189168 August 24, 2006 Sato et al.
20060213761 September 28, 2006 Axenbeck et al.
20060214599 September 28, 2006 Ogawa
20060241879 October 26, 2006 van Zyl
20060252283 November 9, 2006 Takeda et al.
20060278608 December 14, 2006 Hoffman
20070008034 January 11, 2007 Tayrani
20070042131 February 22, 2007 Soo et al.
20070080903 April 12, 2007 Lee
20070139122 June 21, 2007 Nagarkatti et al.
20080007883 January 10, 2008 Arndt et al.
20080061794 March 13, 2008 Pankratz
20080122369 May 29, 2008 Nitschke
20080156632 July 3, 2008 Van Zyl
20080203070 August 28, 2008 Ilic et al.
20080309402 December 18, 2008 Ozimek et al.
20100026186 February 4, 2010 Forrest et al.
20100213903 August 26, 2010 Ozimek et al.
20120187844 July 26, 2012 Hoffman et al.
Foreign Patent Documents
0564789 February 1993 EP
1 434 336 June 2004 EP
1 995 818 November 2008 EP
11-323543 November 1999 JP
WO 01/13402 February 2001 WO
WO 2005/010228 February 2005 WO
WO2006014212 February 2006 WO
WO2006023847 March 2006 WO
WO2008033968 March 2008 WO
Other references
  • European Search Report dated Jul. 3, 2009, issued in corresponding European application No. EP 09 40 5031.
  • Massimo, “European Search Report re Application Matter EP 07 81 4831”, Oct. 17, 2012, Published in: EP.
  • Harriston, William, “Office Action re U.S. Appl. No. 12/631,735”, Jun. 26, 2012, p. 44, Published in: US.
  • Korean Intellectual Property Office, “Notice of Request for Submission of Argument; Office Action re Korean application No. 10-2009-7018460”, Feb. 15, 2012, p. 7, Published in: KR.
  • Korean Intellectual Property Office, “Notice of Request for Submission of Argument; Office Action re Korean application No. 10-2007-7024782”, Feb. 29, 2012, p. 7, Published in: KR.
  • Burke, Julie, “International Search report and Written Opinion re Application PCT/US07/78339”, Aug. 29, 2008, Published in: US.
  • Young, Lee W., “PCT International Search Report re Application No. PCT/US08/054056”, Jun. 25, 2008, Published in: PCT.
  • Kim, Ki Wan, “International Search Report and Written Opinion re Application PCT/US09/051174”, Feb. 24, 2010, Published in: KR.
  • Baharlou, Simin, “International Preliminary Report on Patentability re application No. PCT/US09/051174”, Feb. 10, 2011, Published in: WO.
  • Kolev, V., “International Search Report re Application PCT/US09/066899”, Feb. 19, 2010, Published in: AU.
  • Mulhausen, D., “International Preliminary Report on Patentability re Application PCT/US09/066899”, Jun. 16, 2011, Published in: CH.
  • Raj, M., “International Search Report and Written Opinion re Application No. PCT/US2011/047464”, Oct. 3, 2012, Published in: AU.
  • O'Dowd, Sean, “Response to Office Action re U.S. Appl. No. 12/631,735”, Sep. 26, 2012, p. 9, Published in: US.
  • Baharlou, Simin, “International Preliminary Report on Patentability re Application No. PCT/US2011/047464”, Mar. 7, 2013, p. 6, Published in: CH.
Patent History
Patent number: 8854781
Type: Grant
Filed: Mar 18, 2013
Date of Patent: Oct 7, 2014
Patent Publication Number: 20130271885
Assignee: Solvix GmbH
Inventors: Albert Bulliard (Marly), Benoit Fragniere (Bulle), Joel Oehen (Granges-Paccot)
Primary Examiner: Scott Bauer
Application Number: 13/846,430
Classifications
Current U.S. Class: Voltage And Current (361/79); Arc Suppression At Switching Point (i.e., Includes Solid-state Switch) (361/2)
International Classification: H02H 3/00 (20060101); H02H 7/00 (20060101); H01J 37/34 (20060101); H02H 1/06 (20060101); H02H 3/38 (20060101); H01J 37/32 (20060101);