High density connector

- Molex, LLC

A connector can be provided that allows for improved route-out including straight-back routing. Signal and ground terminal tails can be arranged in a single row to help facilitate such functionality. A commoning member can connect ground tails to ground terminals. Consequentially, a connector with two vertically stacked card slots can be provided that allows for straight back routing of the signal traces in four layers while still providing a compact connector design.

Skip to: Description  ·  Claims  ·  References Cited  · Patent History  ·  Patent History
Description
RELATED APPLICATIONS

This application is a continuation of U.S. Ser. No. 14/398,633, filed Nov. 3, 2014, now U.S. Pat. No. 9,246,251, which is incorporated herein by reference in its entirety and which is a national phase of and claims priority to PCT Application No. PCT/US2013/039459, filed May 3, 2013, which in turn claims priority to U.S. Provisional Application No. 61/642,005, filed May 3, 2012, which is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates to the field of connectors, more specifically to the field of connectors suitable for use in applications where the connector is supported by a circuit board.

DESCRIPTION OF RELATED ART

Connectors are widely used to provide an interface between a circuit board and another connector (such as a plug connector). Due to the continual improvement in computing power and the increased demand for high bandwidth communication channels on the end user side, there has been increased demand for connectors that can handle higher density of transmission channels while at the same time there has been an increased desire to provide connectors that take up less space on a supporting circuit board. Consequentially, connector designs have continued to attempt to increase performance while at the same time increasing density. One major complication with this effort is that more closely arranged communication channels create cross-talk on neighboring channels, thus it becomes more challenging to improve data rates while providing for an increase in density that can actually be mounted on a circuit board. Another major concern for system level developers is that the space required to mount a connector is often not representative of the space needed to route out the connector on a circuit board. In particular, ground vias (which are required to electrically connect to ground terminals) tend to be positioned in locations that interfere with ideal signal trace routing configurations. Accordingly, certain individuals would appreciate further improvements in connector design.

BRIEF SUMMARY

A connector is disclosed that allows for very compact routing on a minimal number of layers while providing for high performance. In an embodiment, the connector includes pair of signal wafers that are positioned side-by side, each wafer including a first terminal with a contact, a tail and a body extending between the tail and contact so that a pair of the first terminals can form a differential pair. The differential pair can be configured to provide a broad-side coupled configuration in the body of the terminals. The tails are configured to be positioned in a line and the line can be positioned between the body of the different pairs. At least one of the wafers that forms the pair of wafers includes a tail stub that is electrically isolated from the first terminal and includes a tail. A ground wafer is provided adjacent one of the pair of wafers and can include one or more terminals that are arranged such that the body is aligned with the body of the terminals that provide the differential pair. The ground terminal omits a tail and instead the ground terminal is coupled to the tail stub in one of the signal wafers. A conductive member can connect a junction in the ground terminal to a junction in the tail stub.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limited in the accompanying figures in which like reference numerals indicate similar elements and in which:

FIG. 1 illustrates a perspective view of an embodiment of a connector.

FIG. 2 illustrates another perspective view of the connector depicted in FIG. 1.

FIG. 3 illustrates a partially exploded perspective view of the connector depicted in FIG. 1.

FIG. 4 illustrates another perspective view of the embodiment depicted in FIG. 3.

FIG. 5 illustrates a partially exploded perspective view of an embodiment of a connector.

FIG. 6 illustrates a partially exploded perspective view of an embodiment of a wafer set.

FIG. 7 illustrates another perspective view of the embodiment depicted in FIG. 6.

FIG. 8A illustrates an elevated side view of an embodiment of a ground wafer.

FIG. 8B illustrates a perspective view of the ground wafer depicted in FIG. 8A.

FIG. 9A illustrates an elevated side view of a signal wafer.

FIG. 9B illustrates a perspective view of the signal wafer depicted in FIG. 9A.

FIG. 10A illustrates a bottom view of a wafer triplet with the frames removed.

FIG. 10B illustrates an elevated side view of the embodiment depicted in FIG. 10A.

FIG. 11 illustrates a simplified perspective view of an embodiment of a connector.

FIG. 12 illustrates another perspective view of the embodiment depicted in FIG. 11.

FIG. 13 illustrates a perspective view of another embodiment of a connector.

FIG. 14 illustrates a simplified perspective view of the embodiment in FIG. 13.

FIG. 15 illustrates a simplified perspective view of the embodiment depicted in FIG. 13.

FIG. 16 illustrates a perspective view of the embodiment depicted in FIG. 15 with the frames omitted for purposes of illustration.

FIG. 17 illustrates another perspective view of embodiment depicted in FIG. 16.

FIG. 18 illustrates a perspective view of the bottom of a plurality of wafers.

FIG. 19 illustrates a perspective view of two adjacent signal wafers, illustrating features that can coupled the signal wafers together.

FIG. 20 illustrates an embodiment of a pair of traces extending between two rows of vias.

 DETAILED DESCRIPTION

The detailed description that follows describes exemplary embodiments and is not intended to be limited to the expressly disclosed combination(s). Therefore, unless otherwise noted, features disclosed herein may be combined together to form additional combinations that were not otherwise shown for purposes of brevity.

FIGS. 1-10B illustrate features of a first embodiment. As can be appreciated, a connector system 10 includes a set of wafers 50 supported by a housing 20 that is positioned on a circuit board 30. While a partial housing 20 is disclosed, the housing can include sides, a top and rear wall in addition to front portion that supports card slots. Thus, any desirable housing may be provided. It should be further appreciated that while a stacked connector (e.g., two or more vertically arranged card slots) is depicted with a first card slot 21 and a second card slot 22, a single card slot could also be provided. The card slot 21 can have a first side 21a and a second side 21b and the second card slot can have a first side 22a and a second side 22b.

It should be noted that the depicted housing and wafers have lines indicating two or more piece construction. Such a construction was done for purposes of modeling and is not required in an actual part and it is expected that the various frames and housings can be formed in one piece using convention molding technology. Therefore, the depicted seam lines are not intended to be limiting.

As depicted, the set of wafers 50 includes a wafer triplet 55 that includes a ground wafer 60 with a frame 61, a first signal wafer 80 with a frame 81 and a second signal wafer 100 with a frame 101. The frame 61 of the ground wafer 60 supports a first ground terminal 62, a second ground terminal 63, a third ground contact 64 and a fourth ground terminal 65. Each of the ground terminals includes a contact 62a, 63a, 64a, 65a and a body 62b-65b and each ground terminal includes an end, such as end 62c. As depicted, the ground terminals do not have tails but do include junction 66.

The frame 81 of the first signal wafer 80 supports signal terminals 82-85 and each terminal includes a contact, a body and a tail. For example, terminal 82 includes a contact 82a and a body 82b and tails 82c. Similarly the frame 101 of the second signal wafer 100 supports terminals 102-105 and each terminal includes a contact, a body and a tail. For example, terminal 102 includes a contact 102a, a body 102b and a tail 102c. The terminals 62, 82, 102 are configured such that their respective contacts 62a, 82a, 102a are aligned side-by-side on the first side 21a of the first card slot 21 while the contacts 63a, 83a, 103a of terminals 63, 83, 103 are on the second side 21b. The same type of arrangement is also provided for the second card slot 22. Thus, the depicted embodiment also includes sufficient signal terminals such that wafers 80, 100 provide four signal pairs, each pair on an opposite side of one card slots 21, 22. Thus the depicted embodiment illustrates four terminals in each signal wafer so that the two signal wafers collectively provide four differential pairs.

As can be appreciated, the differential pairs are edge coupled in the contacts, broad-side coupled in the body and then edge coupled again at the tails. One benefit of the depicted design is that all the tails of the wafer triplet can be arranged in a single row 58a, 58b. This allows the circuit board to have its vias arranged in a corresponding single row 34a, 34b. In addition, the vias are configured so that a row has a G1 via, a S+, S− pair, a G2 via, a S+, S− pair, a G3 via, a G4 via, a S+, S− pair, a G5 via, a S+, S− pair, and a G6 via. In between the rows 34a, 34b are trace paths 35 that allows the signal traces in the board to be routed out in four layers while minimizing board space. In the depicted embodiment, for example, a first trace pair 33a can be routed out on a first layer, a second trace pair 33b can be routed out on a second layer, a third trace pair 33c can be routed out on a third layer and a fourth trace pair 33d can be routed out on a fourth layer, all while staying between a first via row 34a and a second via row 34b. Such a design is particularly helpful when the number of layers available is sufficient to support the multiple rows of traces and the horizontal board space needs to be conserved. Furthermore, such a design is well suited to ganged applications because connectors can be placed beside each other without the need to worry about traces needing to fan out in order to route out the connector on the circuit board, even if the connector is a stacked configuration. Thus the depicted connector allows for simple routing of the traces. In addition the simple routing configuration that is possible tends to improve the performance on the circuit board as there are reduced losses in the circuit board compared to existing designs that route around different ground vias (typically providing more of a fan-out routing in the circuit board).

As can be appreciated, the ground terminals include junctions that intended to be electrically connected to tail stubs 95. Thus, the ends of the ground terminals are electrically connected to the tail stubs 95 via conductive members 140 that connect to junctions 66 in the tail stubs 95 and the ground terminals. As depicted, there are three junctions 66, one on each side of the ends of ground terminals 62a and 62b, and the ends of the ground terminals are connected together with a bar 68a, 68b that includes the three junctions 66. Tail stubs 95 are supported by the signal wafers 80, 100 so as to provide grounds G′1, G′2, G′3, G′4, G′5, G′6 and the conductive member 140 ensures that there is a return to ground path for each ground terminal so that the ground terminals can be electrically connected to a ground via (such as ground vias G1, G2, G3, G4, G5, G6) with the grounds. As depicted, the majority of the tails stubs 95 can be configured to be the same design, which can help to keep the overall costs lower and may also provide more consistent performance.

It should be noted that while ground terminals are depicted as being substantially the same size as the signal terminals, in alternative embodiments the ground terminals could be provided as shields that are at least twice as wide as the signal terminals and in certain embodiments the ground terminal should be replaced with a shield that would extend between and overlap the ground terminals 62a, 62b. In addition, a wide shield that extends across substantially the entire ground wafer could also be provided. In each embodiment, the junctions 66 and conductive members 140 would allow the ground terminals/ground shield to electrically couple to tails stubs that are electrically coupled to ground (e.g., provide a return path for energy carried on the ground terminals).

As depicted, the signal wafers are configured so that signal wafer 80 includes three ground stubs 70 and signal wafer 100 includes three ground stubs 70. This allows, when looking at a row, a ground, signal, signal, ground, signal, signal, ground pattern that is repeated. Thus, signal pairs 57 are positioned between ground vias and two ground vias are positioned between the signals pairs in the first and second card slot. The additional ground via helps provide further electrical isolation between the top and bottom card slot and can help reduce cross-talk in a connector that is configured to be compactly designed such that there is limited space between vertical card slots.

As can be appreciated from FIGS. 11 and 12, which illustrate features that can be included in design illustrated in FIGS. 1-10B, the tails can be configured to be a press-fit style. Alternatively, the tails can be a simple through-hole style or any other desired tail configuration.

FIGS. 13-19 illustrate another embodiment of a connector that can be used to provide straight-back routing. It should be noted that the use of straight back routing is not required but it is expected to provide space saving benefits on the circuit board. Thus, unless otherwise noted, the style of routing on the circuit board is not intended to be limiting.

A connector 210 includes a housing 220 with a wafer set 250. The housing can include two card slots 221, 222 and each card slot can include a first side 221a, 222a and a second side 221b, 222b. As can be appreciated, the card slots 221, 222 are on a mating face of the connector 210 and the tails are on a mounting face of the connector 210. As in the above embodiment, triplets 41a, 41b, 41c, 41d are positioned on opposite sides of their respective card slots but are all configured to be connected to a supporting circuit board in the row 258a, thus row 258a includes four terminal pairs 257 and each terminal pair 257 is separated from another terminal pair in the row 258a by at least tail that is connected to a ground terminal by a conductive member 340. As in the above embodiments, the ground tails are formed by tail stubs that are also in the row 258a and the tail stubs are electrically isolated from the signal terminals.

Similar to the above embodiment, the connector includes rows 258a, 258b of tails and conductive members 340 are used to connect junctions 266 in the bars of the ground terminals to junctions 266 in tail stubs. The tail stubs provide grounds G″1, G″2, G″3, G″4, G″5, G″6. As in the above embodiment, signal pairs S+, S− are positioned so that a ground is on each side of the signal pair.

The conductive members 340 can be shaped like flat plates and the additional surface area can provide additional shielding between signal pairs within a row. The conductive members 340 can be pressed into channels 361 in the bottom of the wafers (e.g., inserted into the wafers on the mounting side) so that the conductive members 340 can engage the junctions 266 supported by the frames 261, 281, 301. As can be appreciated, the conductive member extends past the frames 281, 301 in the case of a channel 360. In an embodiment, each signal pair will have a conductive member 340 positioned on opposing sides.

As can be appreciated from FIG. 19, the signal wafers 280, 300 are configured so that their various features interweave with corresponding features in the other wafer. This allows the tails of the signal terminals to be offset toward the row center line. In addition, other features can help hold the wafers together. For example, projections 308 can be configured to engage notches 288. Such construction is not required but helps provide additional spacing control between the two signal wafers and is expected to help improve performance at higher signaling frequencies and associated data rates.

FIG. 20 illustrates an embodiment of a circuit board 430 in which the rows 458a, 458B have a slight meander in them rather than being a straight line. As can be appreciated, in the depicted embodiment an average center 439 of each row intersects each of the ground vias G and signal vias S+, S−. It should be noted that the average center 439 of FIG. 20 extends through the center of each ground via G but such an alignment, while beneficial to ensure good electrical performance, is not required. It is helpful to ensure that the spacing between like vias in adjacent rows can be kept at a constant distance D, or at least substantially similar distance. As can be appreciated, the meandering of the row causes the trace path 437 to meander. Traces extending along the trace path can meander to match the meander of the trace path 435 (such a configuration is expected to provide superior electrical performance) or can run straight and alternatively get closer to one row or the other (such a configuration is expected to be simpler to route). As in the above embodiment, two ground vias G are positioned between the top and bottom port. If further electrical enhancement is desired, the connector mating interface can be lengthened so that two ground vias are positioned between each differential pair DP. Thus, the depicted connector can readily be modified to provide additional performance enhancements. Naturally, an embodiment with a circuit board as depicted in FIG. 20 will have a connector where the signal terminals tails are offset a different amount than half a wafer thickness (typically less than half a wafer thickness), thus a connector is not limited to depicted embodiments that show the terminals offset by half a wafer thickness).

The disclosure provided herein describes features in terms of preferred and exemplary embodiments thereof. Numerous other embodiments, modifications and variations within the scope and spirit of the appended claims will occur to persons of ordinary skill in the art from a review of this disclosure.

Claims

1. A connector, comprising:

a housing with a mating face and a mounting face; and
a ground wafer with a first frame that supports a plurality of ground terminals, the ground wafer supported by the housing, each of the plurality of ground terminals including a contact aligned with the mating face, the plurality of ground terminals electrically connected to a first junction aligned with the mounting face;
a signal wafer positioned in the housing adjacent the ground wafer, the signal wafer including a second frame that supports a plurality of signal terminals, each of the plurality of signal terminals having a contact that is aligned with the mating face and a tail aligned with the mounting face, the signal wafer including a ground tail with a second junction, the second junction aligned with the mounting face; and
a flat plate positioned in the first and second junction.

2. The connector of claim 1, wherein the ground wafer and the signal wafer define a channel and the flat plate is positioned in the channel.

3. The connector of claim 1, wherein the flat plate is vertically aligned.

4. The connector of claim 3, wherein the flat plate extends to an edge of the supporting frames.

5. The connector of claim 1, wherein the signal terminals each include a body that extends from the tail to the contact, the body extending vertically past the flat plate and then extending transverse to the flat plate.

6. The connector of claim 1, wherein the plurality of ground terminals are connected to an end and the first junction is a plurality of first junctions, each of the plurality of first junctions positioned in the end.

7. The connector of claim 6, wherein the signal wafer supports a plurality of ground tails and each ground tail includes a second junction, wherein a plurality of flat plates connect the plurality of first junctions to the corresponding second junctions.

8. A method, comprising:

providing a connector with a mounting face and a mating face, the mating face including contacts for mating to another connector and the mounting face including tails for mating with a circuit board, the mounting face including a plurality of rows of channels, each of the plurality of rows of channels including a first junction and a second junction, the first junction connected to a ground tail and the second junction connected to a ground terminal; and
inserting a commoning member into each of the plurality of rows of channels, the commoning member electrically connecting the ground terminal to the ground tail.

9. The method of claim 8, wherein the commoning member is a flat plate.

10. The method of claim 9, wherein the first and second junctions are slots and the inserting step slides the flat plate into the corresponding slots.

11. The method of claim 8, further comprising the step of mounting the connector on a circuit board.

12. The method of claim 8, wherein the tails are press-fit tails and the step of mounting the connector on the circuit board include inserting the tails into vias on the circuit board.

Referenced Cited
U.S. Patent Documents
5474472 December 12, 1995 Niwa et al.
5664968 September 9, 1997 Mickievicz
7422483 September 9, 2008 Avery et al.
7775802 August 17, 2010 Defibaugh et al.
8668524 March 11, 2014 Lan
8734187 May 27, 2014 De Geest
8814595 August 26, 2014 Cohen
20030220019 November 27, 2003 Billman et al.
20110212633 September 1, 2011 Regnier et al.
20110300757 December 8, 2011 Regnier et al.
Patent History
Patent number: 9385455
Type: Grant
Filed: Oct 14, 2015
Date of Patent: Jul 5, 2016
Patent Publication Number: 20160036147
Assignee: Molex, LLC (Lisle, IL)
Inventors: Kent E. Regnier (Lombard, IL), Patrick R. Casher (North Aurora, IL), Michael Rowlands (Naperville, IL)
Primary Examiner: Khiem Nguyen
Application Number: 14/882,833
Classifications
Current U.S. Class: Grounding Of Coupling Part (439/108)
International Classification: H01R 13/648 (20060101); H01R 12/70 (20110101); H01R 9/24 (20060101); H01R 12/72 (20110101); H01R 12/71 (20110101); H01R 13/652 (20060101); H01R 43/20 (20060101);