Digital closed-loop control for DC/DC switch-mode power converters with multiple outputs
Apparatus and method for providing closed loop feedback control for switch-mode DC/DC power converter with multiple outputs using digital filter feedback, in contrast to analog error feedback. In the apparatus and method, multiple outputs for a switch-mode DC/DC power converter are regulated by digital means, including the allocating or partitioning of digital control resources among each of the multiple outputs. The partitioning of control resources may be in response to operating conditions.
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The present invention relates to regulated DC power supplies generally, and specifically, an improved system and method for providing closed loop digital filter feedback control for DC switch-mode multiple output DC power supplies.
BACKGROUNDEmbodiments of most existing switch-mode DC/DC power converters with analog feedback control take the form as shown in
However, as can be seen in the device 10 of
Provisions may be made to add a local series regulator 41 to the second output filter 40A, such as shown in the modified switch-mode DC/DC converter device 10′ having two outputs of
This design of
It would be highly desirable to provide an improved regulated DC/DC switch-mode power supply with multiple outputs.
SUMMARYThere is provided an improved switch-mode DC/DC power flyback converter with improved ability to regulate multiple outputs. and particularly, to perform multiple outputs regulation with digital means.
There is provided an improved switch-mode DC/DC power flyback converter with improved ability to regulate multiple outputs with minimized hardware weight, size, and cost.
There is further provided an improved switch-mode DC/DC power flyback converter with improved ability to allocate control resources among multiple outputs.
There is further provided an improved switch-mode DC/DC power flyback converter with an ability to ration control resources among multiple outputs in responding to an operating condition.
In one aspect, there is provided a switch-mode DC/DC power flyback converter and method of operating. The power converter comprises: a power transformer receiving a source of DC power, and providing a regulated power output to both a first output load and a second output load; a first feedback loop associated with the first output load for regulating the power supplied to the first output load, and a second feedback loop associated with the second output load for regulating the power supplied to the second output load; a first digital filter for processing a first feedback signal corresponding to the first output load in the first feedback loop and generating a first error signal; a second digital filter for processing a second feedback signal corresponding to the second output load in the second feedback loop and generating a second error signal; a switching device for conducting the first error signal generated from the first digital filter as an output at first time intervals, and conducting the second error signal generated from the second digital filter as an output at second time intervals; means responsive to the first output error signal for regulating the first output load at the first time intervals, and responsive to the second output error signal for regulating the second output load at the second time intervals.
In a further aspect, the switch-mode DC/DC power flyback converter comprises: a power transformer receiving a source of DC power, and providing a regulated power output to both a first output load and a second output load; a first feedback loop associated with the first output load for regulating the power supplied to the first output load, and a second feedback loop associated with the second output load for regulating the power supplied to the second output load; a first digital filter for processing a first feedback signal corresponding to the first output load in the first feedback loop and generating a first error signal; a second digital filter for processing a second feedback signal corresponding to the second output load in the second feedback loop and generating a second error signal; the single controller device being configurable as the first digital filter for the first feedback loop and the second digital filter for a second feedback loop, the single controller device receiving a first set of coefficients to configure a direct form implementation of a first discrete digital filter during a first time interval and successive first time intervals, and the single controller device receiving a second set of coefficients to configure a direct form implementation of a discrete second digital filter during the second time interval and successive second time intervals; the controller device generating a first error signal output when configured as the first digital filter at first time intervals, and generating a second error signal output when configured as the second digital filter at the second time intervals; and means responsive to the first output error signal for regulating the first output load at the first time intervals, and responsive to the second output error signal for regulating the second output load at the second time intervals.
Further, methods of operating the DC/DC power flyback converter are provided. In one aspect, a method for regulating a power supply output of a switch-mode DC/DC power converter comprises: receiving, at a power transformer of the switch-mode DC/DC power converter, a source of DC power, the power transformer converting the DC power source to a respective regulated power output at both a first output load and a second output load; receiving, at a first digital filter device in a first feedback loop associated with the first output load, a first feedback signal; and receiving, at a second digital filter device in a second feedback loop associated with the second output load, a second feedback signal; generating, at an output of the first digital filter, a first error signal based on the received first feedback signal; and generating, at an output of the second digital filter, a second error signal based on the received second feedback signal; conducting, using a switching device, the first error signal generated from the first digital filter as an output at first time intervals; and conducting, using the switching device, the second error signal generated from the second digital filter as an output at second time intervals; regulating, responsive to the first output error signal, the first output load at the first time intervals; and regulating, responsive to the second output error signal, the second output load at the second time intervals.
In a further aspect, a method for regulating a power supply output of a switch-mode DC/DC power converter comprises: receiving, at a power transformer of the switch-mode DC/DC power converter, a source of DC power, the power transformer converting the DC power source to a respective regulated power output at both a first output load and a second output load; configuring a controller device as a first digital filter in a first feedback loop in a first time interval and configuring the controller device as a second digital filter for a second feedback loop in a second time interval, receiving, at a controller device, a first set of coefficients to configure a direct form implementation of a first discrete digital filter during a first time interval and successive first time intervals, and receiving at the controller device a second set of coefficients to configure a direct form implementation of a discrete second digital filter during the second time interval and successive second time intervals; the controller device generating a first error signal output when configured as the first digital filter at first time intervals, and generating a second error signal output when configured as the second digital filter at the second time intervals; and regulating, responsive to the first output error signal, the first output load at the first time intervals, and regulating, responsive to the second output error signal, the second output load at the second time intervals.
Other aspects, features and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which similar elements are given similar reference numerals.
In the DC/DC converter of
Likewise, a second feedback loop 17B provides DC power through rectifier 35B and output filter 40B elements to a second output load 45B. A feedback signal 41B from the output filter 40B is input to feedback factor element 48B providing a scaled-down feedback signal 42B to a second digital filter 161. Scaling is necessary to bring down the output signal level for digital processing by the digital filter. In one embodiment, digital filter 161 comprises an analog/digital converter element, and a reference signal. This discrete digital filter is configured to have a different transfer function, e.g., H2(z). The discrete digital filter output, i.e., the error signal 61 from the digital filter 161, is coupled to a second input of the SPDT switch 63. Output of the switch 63 is coupled to the PWM element 65 the output of which controls switch drivers 25 and hence transformer/inductor control under digital control.
Thus,
Both the DC/DC power converter 100 of
In one embodiment, each digital filter 160, 161 is implemented as a respective individual programmable hardware device, such as a single microprocessor (having its own associated I/O, memory and registers), or a microcontroller, or a field-programmable gate array (FPGA), all referred to hereinafter as a “controller device”. In a further embodiment, a single controller device may be programmed to be configured as a respective digital filter 160, 161 in alternating time intervals.
Thus, in each of the digital filter embodiments, a controller device is programmed to respectively receive a set of values, including digital filter coefficients 97, 98 used to program each respective discrete digital filter 160, 161 for controlling digitally, the switching of the flyback converter outputs. The software representing each filter transfer function may be programmed or “burned” into each respective single controller device to configure the controller to concurrently run two separate processing threads, each thread configured by a separate set of programmed and stored filter coefficients 97, 98 corresponding to each digital filter 160, 161 respectively. Programmable sets of coefficients may be stored into a register or memory location associated with the programmable control device. Additionally, programmable sets of coefficients may be received from another device remotely, e.g., communicated over a network, and stored into the memory associated with the programmable control device. The set of filter coefficients 97, 98 may thus be communicated, received, stored and used to program the response of each digital filter in a user-defined way.
In each of the embodiments of the DC/DC flyback converter described herein, the alternation clock rate/frequency and dwell time of the SPDT switching (or alternately, of the switching of the sets of coefficients configuring each digital-feedback filter) is configurable. Given an embodiment of a DC/DC converter having a main power stage (power train) switched at 20 KHz, which is much higher than the closed-loop bandwidth of only 2 KHz, the SPDT toggling/alternating rate/frequency is set to 100 KHz; five times of the power stage switching. This alternation clock rate/frequency is one minimum required in one embodiment. In further embodiments, this rate may be extended up to 500 KHz.
Generally, the sampling frequency for a digital filter may be selected according to steps such as: examining and plot the corresponding analog error amplifier in frequency domain; picking a frequency that covers sufficiently the performance of the analog error amplifier and selecting a sampling frequency that is at least twice the frequency picked in the prior step.
With respect to the dwell time rationing, given an example operating conditions of input and load such as shown and described herein with respect to
As mentioned, each digital filter may be embodied as a separate, stand-alone processor or microcontroller (or FPGA) having its own associated memory, I/O and registers, or both discrete digital filters may be embodied as a single controller. Whether embodied as separate standalone controller device or not, as shown in
where polynomial coefficients an and bn, n=0, 1 or 2 are derived from a combination of analogue coefficients of a corresponding error analog amplifier function described in greater detail herein below. One set of coefficients for this filter need to be loaded and stored in the hardware microprocessor, microcontroller, or FPGA.
Similarly, in an example embodiment, as shown in
where polynomial coefficients an and bn, n=0, 1, 2 or 3, are derived from a combination of analogue coefficients of a corresponding error analog amplifier function described in greater detail herein below. One set of coefficients for this filter need to be loaded and stored in the hardware microprocessor, microcontroller, or FPGA.
In either embodiment, the digital filter transfer function H(z) may receive its own set of respective coefficients, Type-II or Type_III coefficients for regulating the outputs. While such a configuration may give better performance; use of two control devices however, is a more costly alternative.
Likewise,
With respect to
In one embodiment, a single digital filter may be configured to provide digital switching control for a flyback converter having two outputs and a single digital filter H1(z) for controlling one of the multiple outputs (two being shown).
In operation, the PWM block 365 conducts based on when the error signal Ve is greater in value (rises above) the voltage carrier at the inverting input. Otherwise, the PWM 365 will stop conducting when the error signal decreases (drops below) the carrier level. This provides the pulse width modulation used as an input signal 366 to the switch driver element 25 used to drive the power switch 20 for regulating the output voltage V1 via the feedback loop 317. Thus, in this embodiment, as only feedback V1 from one load is obtained, only one load is regulated by the loop and the 2nd load output voltage V2 may be unregulated.
In a further embodiment, a single digital filter may be configured to provide digital switching control for a flyback converter having two outputs and a single digital filter H2(z) for controlling one of the outputs.
In operation, the PWM block 365 conducts based on when the error signal Ve is greater in value (rises above) the voltage carrier at the inverting input. Otherwise, the PWM 365 will stop conducting when the error signal decreases (drops below) the carrier level. This provides the pulse width modulation used as an input signal 366 to the switch driver element 25 used to drive the power switch 20 for regulating the output voltage V2 via the feedback loop 318. Thus, in this embodiment, as only feedback V2 from one load is obtained, only one load is regulated by the loop and the 1st load output voltage V1 may be unregulated.
To identify and program each of the digital filters 160, 161, reference is now had too
As shown in
Within the Modulator 350 the PWM block 365 has, when slightly perturbed, a gain Fm, where Fm=δD/δve, that is, it is equal to the ratio between duty cycle change (δD) and error signal variation (δve). There is further derived the power stage gain Gvd(s)=δvo/δD, as function of the perturbation frequency. The feedback factor 348 has a simple gain Kf=δvf/δvo where δvf/δvo is a ratio between feedback changes and output changes. The Modulator has a gain equal to M(s)=KfGvd(s) Fm. Depending on converter topology, and the PWM mechanism 365, a gain of individual block changes both in mathematical form and in value.
Thus, given an example desired closed-loop unity-gain crossover frequency, for example, selected at 2 KHz,
or
a Type-III analogue error amplifier transfer function:
with each transfer function Ea1(s) and Ea2(s) having respective sets of polynomial coefficients, e.g., coefficients a, b, and c, in accordance with analog filter components used to attain a selected crossover frequency, modulator gain, modulator phase, and loop gain phase margins.
With the Type-II analog error amplifier's and/or Type-III analog error amplifier's transfer function identified and expressed in standard compact, close form, a bi-linear transform s=C(1−z−1)/(1+z−1), is applied to each in an additional mathematical transformation. The step relates the continuous analog error amplifier, symbolized by the Laplace operator s, to the discrete digital filter, symbolized by the sampling operator z, to obtain corresponding H1(z) and H2(z) forms having an and bn coefficients indicated. It shall be noted that the minus sign shown in the analog Ea(s) functions are omitted for the digital H(z) functions.
That is, in the embodiments described herein, the discrete digital filter H1(z) transfer function having a Type-II form is derived from the first error analog error amplifier transfer function Ea1(s), and the discrete digital filter H2(z) transfer function having a Type-III form is derived the second analogue error amplifier transfer function Ea2(s), where in each, digital filter coefficients an and bn values relate to combination of analog coefficients a, b, and c that are attributed to combinations of physical components: resistors and capacitors, corresponding to aforementioned Type-II and Type-III filter forms.
ExampleA flyback converter for an assembly used in the telecommunications market for powering less than 100 W applications implements digital control.
Here, in the digital control circuit simulation depicted
For the 3.3V loop, with feedback Rf3 and Rf4, the type-II digital filter identified as H3(Z) has a first set of coefficients:
and for the 12V loop, with feedback Rf1 and Rf2, the type-II digital filter identified as Hz12 has a different set of coefficients:
where a0≠a3, a1≠a4, and a2≠a5 and b1≠b3 and b2≠b4.
In the simulation of
The example results shown in
Furthermore, in one embodiment, a DC/DC converter device employing digital filter control in the manner as set forth herein, may be programmable remotely, e.g., over a wired or wireless communication link(s). For example, the above filter programming tasks may be performed remotely via a network, such as the Internet.
Thus, DC/DC converter 500 apparatus includes the controller 550, e.g., an FPGA or microprocessor, etc., having at least a memory storage device 520, e.g., registers 570, main memory and/or a cache 580, with the controller device 550 coupled to the memory, e.g., via conductors such as a data and address bus 56, wherein the processor device 550 is configured to access sets of coefficients from a staging memory or buffer registers 570 to configure itself as a digital filter 160, 161 or 162 according to the embodiments as described herein. In one aspect, the associated memory storage device 520 receives and stores program instructions including the functions and procedures that are accessed by the hardware processor device 550 for configuring the filters and partitioning the digital control dwell times thereof. The partitioning of control resources may be in response to operating conditions detected by the DC/DC converter device itself.
In such an embodiment, the DC/DC converter 500 is equipped with a communications transceiver providing an interface 540 configured to receive signals communicated over a communications link 18 for programming the DC/DC converter digital filter(s). For example, as shown in
In operation, microprocessor, microcontroller or field programmable gate array (FPGA) 550 coupled to the memory 520 accesses the stored values to program the converter to configure each discrete digital filter according to any of the embodiments described herein. Thus, from a remote location, such as a wireless or wired communication link, the polynomial coefficient values, e.g., two sets 97, 98 of coefficients (an and bn) for either of the Type-II or Type-III discrete digital filter transfer functions.
The present invention thus provides a simpler, lower cost circuit alternative for enhancing, by digital control, such switched DC/DC voltage power supplies.
The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing the controller device 550 of
While various embodiments are described herein, it will be appreciated from the specification that various combinations of elements, variations or improvements therein may be made by those skilled in the art, and are within the scope of the invention. In addition, many modifications may be made to adapt a particular combination of devices to the teachings of the invention without departing from essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims
1. A multi-loop switch-mode DC/DC power flyback converter for simultaneously regulating multiple outputs, in steady-state, with switched digital filters comprising:
- a time-shared, common power transformer and drive circuit receiving a source of DC power, and providing a regulated power output to both a first output load and a second output load;
- a first feedback loop associated with the first output load for regulating said power supplied to said first output load, and a second feedback loop associated with the second output load for regulating said power supplied to said second output load;
- a first digital filter for processing a first feedback signal corresponding to the first output load in said first feedback loop and generating a first error signal;
- a second digital filter for processing a second feedback signal corresponding to the second output load in said second feedback loop and generating a second error signal, said first and second digital filters being derived from a respective corresponding analog transfer gain function, wherein said first and second digital filters for the respective first and second feedback loop are a direct form implementation of a discrete digital filter transfer function having one of: a quadratic or cubic denominator;
- a switching device for distributing the first error signal generated from the first digital filter as an output at first time intervals, and distributing said second error signal generated from the second digital filter as an output at second time intervals;
- said time-shared, common power transformer and drive circuit responsive to said first output error signal for simultaneously regulating said first output load in steady-state at said first time intervals, and responsive to said second output error signal for simultaneously regulating said second output load in steady-state at said second time intervals, wherein each said first and second digital filter are individually configured to perform its own regulation, and each said first digital filter and second digital filter of the discrete digital filter transfer function having polynomial coefficients that are configured to be instantly switched among quadratic, cubic, or higher order polynomial forms.
2. The switch-mode DC/DC power flyback converter of claim 1, further comprising:
- a single switch driver circuit, said single switch driver circuit receiving said first output error signal during said first and successive first time intervals for controlling said time-shared, common power transformer at each said first and successive first time intervals, and said single switch driver circuit receiving said second error signal during said second and successive second time intervals for controlling said time-shared, common power transformer at each said second and successive second time intervals.
3. The switch-mode DC/DC power flyback converter of claim 2, further comprising:
- a pulse width modulator (PWM) device, said pulse width modulator device receiving said first error signal in a first time interval and comparing said received first error signal against a reference signal during said first time interval, said PWM generating a first signal responsive to said comparison for receipt by said single switch driver circuit for controlling said time-shared, common power transformer in the first time intervals;
- said pulse width modulator device further receiving said second error signal in a second time interval and comparing said received second error signal against a reference signal during said second time interval, said PWM generating a second signal responsive to said comparison for receipt by said single switch driver circuit for controlling said time-shared, common power transformer in the second time intervals.
4. The switch-mode DC/DC power flyback converter of claim 3, wherein said reference signal is a periodic ramped signal.
5. The switch-mode DC/DC power flyback converter of claim 1, further comprising:
- a pulse signal generator for generating a signal for input to said switching device for controlling said switching device to distribute said first digital filter output error signals and second digital filter output error signals at respective first time and second time intervals.
6. The switch-mode DC/DC power flyback converter of claim 5, wherein said signal generator comprises a clock device, said clock device configured at a duty cycle for setting a corresponding first time interval and second time interval.
7. The switch-mode DC/DC power flyback converter of claim 5, wherein said switching device comprises a single-pole double-throw (SPDT) switch responsive to said generated signal to either distribute the first error signal at said first time interval, or distribute the second error signal at said second time interval.
8. The switch-mode DC/DC power flyback converter of claim 1, wherein the digital filter transfer function having said quadratic polynomial denominator is of a form H(z) where: H ( z ) = a 0 + a 1 z - 1 + a 2 z - 2 1 + b 1 z - 1 + b 2 z - 2
- where an and bn n=0, 1 or 2 are polynomial coefficients, and z−1 represents a unit time delay.
9. The switch-mode DC/DC power flyback converter as claimed in claim 1, wherein the digital filter transfer function having said cubic polynomial denominator is of a form H(z) where: H ( z ) = a 0 + a 1 z - 1 + a 2 z - 2 + a 3 z - 3 1 + b 1 z - 1 + b 2 z - 2 + b 3 z - 3
- where an and bn, n=0, 1, 2 or 3 are polynomial coefficients.
10. A method for simultaneously regulating multiple outputs, in steady-state, of a multi-loop switch-mode DC/DC power converter with switched digital filters, said method comprising:
- receiving, at a time-shared, common power transformer and drive circuit a source of DC power, said time-shared, common power transformer converting said DC power source to a respective regulated power output at both a first output load and a second output load;
- receiving, at a first digital filter device in a first feedback loop associated with said first output load, a first feedback signal; and receiving, at a second digital filter device in a second feedback loop associated with said second output load, a second feedback signal, said first and second digital filter devices being derived from a respective corresponding analog transfer gain function, wherein first and second digital filters for the respective first and second feedback loop are a direct form implementation of a discrete digital filter transfer function having one of: a quadratic or cubic denominator;
- generating, at an output of said first digital filter, a first error signal based on said received first feedback signal, and generating, at an output of said second digital filter, a second error signal based on said received second feedback signal,
- distributing, using a switching device, the first error signal generated from the first digital filter as an output at first time intervals, and distributing, using the switching device, said second error signal generated from the second digital filter as an output at second time intervals;
- simultaneously regulating, responsive to said first output error signal, said first output load at said first time intervals, and regulating, responsive to said second output error signal, said second output load at said second time intervals, wherein each said first digital filter or second digital filter are individually configured to perform its own regulation, and each said first digital filter and second digital filter of the discrete digital filter transfer function having polynomial coefficients that are configured to be instantly switched among quadratic, cubic, or higher order polynomial forms.
11. The method of claim 10, wherein said regulating responsive to both said first and second output error signal comprises:
- receiving, at a single switch driver circuit, said first output error signal during said first and successive first time intervals for controlling said time-shared, common power transformer at each said first and successive first time intervals, and
- receiving, at said single switch driver circuit, said second error signal during said second and successive second time intervals for controlling said time-shared, common power transformer at each said second and successive second time intervals.
12. The method of claim 11, wherein said regulating responsive to both said first and second output error signal comprises:
- receiving, at a pulse width modulator (PWM) device, said first error signal in a first time interval and comparing said received first error signal against a periodic ramped signal at said first time interval, said PWM generating a first signal responsive to said comparison for receipt by a single switch driver circuit for controlling said time-shared, common power transformer in the first time intervals; and
- receiving, at the pulse width modulator device, said second error signal in a second time interval and comparing said received second error signal against a periodic ramped signal at said second time interval, said PWM generating a second signal responsive to said comparison for receipt by the single switch driver circuit for controlling said time-shared, common power transformer in the second time intervals.
13. The method of claim 10, further comprising:
- generating a signal, using a signal generator, for input to said switching device for controlling said switching device to distribute said first error signals and second error signals as outputs at respective first time and second time intervals, wherein said signal generator comprises a clock device configured at a duty cycle for setting a corresponding first time interval and second time interval.
14. The method of claim 13, wherein said switching device comprises a Single-pole Double-throw (SPDT) switch responsive to said generated signal to either distribute the first output error signal at said first time interval, or distribute the second output error signal at said second time interval.
15. The method of claim 10, wherein the digital filter transfer function having said quadratic polynomial denominator is of a form H(z) where: H ( z ) = a 0 + a 1 z - 1 + a 2 z - 2 1 + b 1 z - 1 + b 2 z - 2
- where an and bn n=0, 1 or 2 are polynomial coefficients, and z−1 stands for a unit time delay.
16. A multi-loop switch-mode DC/DC power flyback converter for simultaneously regulating multiple outputs, in steady-state, with switched digital filters comprising:
- a time-shared, common power transformer and drive circuit receiving a source of DC power, and providing a regulated power output to both a first output load and a second output load;
- a first feedback loop associated with the first output load for regulating said power supplied to said first output load, and a second feedback loop associated with the second output load for regulating said power supplied to said second output load;
- a first digital filter for processing a first feedback signal corresponding to the first output load in said first feedback loop and generating a first error signal;
- a second digital filter for processing a second feedback signal corresponding to the second output load in said second feedback loop and generating a second error signal, said first and second digital filters being derived from a respective corresponding analog transfer gain function, wherein first and second digital filters for the respective first and second feedback loop are a direct form implementation of a discrete digital filter transfer function having one of: a quadratic or cubic denominator;
- said single controller device being configurable as said first digital filter for the first feedback loop and said second digital filter for a second feedback loop, said single controller device receiving a first set of coefficients to configure a direct form implementation of a first discrete digital filter during a first time interval and successive time intervals, and said single controller device receiving a second set of coefficients to configure a direct form implementation of a discrete second digital filter during the second time interval and successive second time intervals;
- said controller device generating a first error signal output when configured as the first digital filter at first time intervals, and generating a second error signal output when configured as the second digital filter at said second time intervals; and
- said time-shared, common power transformer and drive circuit responsive to said first output error signal for regulating said first output load in steady-state at said first time intervals, and responsive to said second output error signal for simultaneously regulating said second output load in steady-state at said second time intervals, wherein each said first and second digital filter are individually configured to perform its own regulation, and each said first digital filter and second digital filter of the discrete digital filter transfer function having polynomial coefficients that are configured to be instantly switched among quadratic, cubic, or higher order polynomial forms.
17. The switch-mode DC/DC power flyback converter of claim 16, wherein the digital filter transfer function having said quadratic polynomial denominator is of a form H(z) where: H ( z ) = a 0 + a 1 z - 1 + a 2 z - 2 1 + b 1 z - 1 + b 2 z - 2
- where an and bn n=0, 1 or 2 are polynomial coefficients, and z−1 represents a unit time delay.
18. A method for simultaneously regulating multiple outputs, in steady-state, of a multi-loop switch-mode DC/DC power converter with switched digital filters, said method comprising:
- receiving, at a time-shared, common power transformer and drive circuit a source of DC power, said time-shared, common power transformer converting said DC power source to a respective regulated power output at both a first output load and a second output load;
- configuring a controller device as a first digital filter in a first feedback loop in a first time interval and configuring said controller device as a second digital filter for a second feedback loop in a second time interval, said first and second digital filter devices being derived from a respective corresponding analog transfer gain function, wherein first and second digital filters for the respective first and second feedback loop are a direct form implementation of a discrete digital filter transfer function having one of: a quadratic or cubic denominator;
- receiving, at a controller device, a first set of coefficients to configure a direct form implementation of a first discrete digital filter during a first time interval and successive time intervals, and
- receiving at said controller device a second set of coefficients to configure a direct form implementation of a discrete second digital filter during the second time interval and successive second time intervals;
- said controller device generating a first error signal output when configured as the first digital filter at first time intervals, and generating a second error signal output when configured as the second digital filter at said second time intervals; and
- simultaneously regulating, responsive to said first output error signal, said first output load at said first time intervals, and regulating, responsive to said second output error signal, said second output load at said second time intervals, wherein each said first digital filter or second digital filter are individually configured to perform its own regulation, and each said first digital filter and second digital filter of the discrete digital filter transfer function having polynomial coefficients that are configured to be instantly switched among quadratic, cubic, or higher order polynomial forms.
19. The method of claim 18, wherein the digital filter transfer function having said quadratic polynomial denominator is of a form H(z) where: H ( z ) = a 0 + a 1 z - 1 + a 2 z - 2 1 + b 1 z - 1 + b 2 z - 2
- where an and bn n=0, 1 or 2 are polynomial coefficients, and z−1 stands for a unit time delay.
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Type: Grant
Filed: May 6, 2015
Date of Patent: May 23, 2017
Patent Publication Number: 20160329813
Assignee: SWITCHING POWER, INC. (Ronkonkoma, NY)
Inventor: Keng C. Wu (Cranbury, NJ)
Primary Examiner: Gary L Laxton
Application Number: 14/705,544
International Classification: H02M 3/335 (20060101); H02M 3/157 (20060101);