With Control Of Equalizer And/or Delay Network Patents (Class 333/18)
  • Patent number: 10757408
    Abstract: Restoring a degraded tile of a degraded frame resulting from reconstruction is disclosed. A method includes, for a scaling factor of at least some scaling factors, recursively filtering the degraded tile using the scaling factor to generate a respective restored tile, and determining a respective error for the respective restored tile with respect to the source tile. The method also includes selecting an optimal scaling factor from the at least some scaling factors and encoding, in an encoded bitstream, a scaling parameter based on the optimal scaling factor. The optimal scaling factor corresponding to a smallest respective error. An apparatus includes a processor and non-transitory memory storing instructions. The instructions cause the processor to determine, from an encoded bitstream, a scaling factor, which determines how strongly edges in the degraded tile affect filtering operations, and recursively filter, resulting in a restored tile, the degraded tile using the scaling factor.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: August 25, 2020
    Assignee: GOOGLE LLC
    Inventors: Debargha Mukherjee, Yue Chen, Sarah Parker
  • Patent number: 10708002
    Abstract: A device, system and method for determining when to initiate certain operations associated with received data. The method is performed at a device connected to a network. The method includes estimating a first number of repetitions of a subframe which is associated with a likelihood that the device will successfully perform an operation based on the subframe. The method further includes delaying initiating the operation for the subframe until a received number of repetitions of the subframe is greater than or equal to the first number of repetitions.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 7, 2020
    Assignee: Apple Inc.
    Inventors: Zhu Ji, Yang Li, Johnson O. Sebeni, Junsung Lim
  • Patent number: 10685640
    Abstract: A noise-cancellation method, comprising the steps of: receiving a value from a noise sensor at a time step; storing the received value in a buffer, the buffer having a length, the buffer further storing a number of additional values, wherein an end value is removed from the buffer to accommodate the received value; providing a previously-computed result, wherein the previously-computed result represents the sum of the square of the values stored in the buffer at a previous time step; adding a square of the received value to the previously-computed result and subtracting a square of the end value from the sum of the received value and the previously computed value in order to yield a newly-computed result and updating a plurality of coefficients of an adaptive filter according to, in part, the value of the newly-computed result.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 16, 2020
    Assignee: Bose Corporation
    Inventors: Siamak Farahbakhsh, Wade Torres, Eric Bernstein
  • Patent number: 10649663
    Abstract: A method and system for accessing a memory for a data processing system. The method comprises sending a read request for a plurality of locations in the memory to read the plurality of locations in parallel based on an upper bound for reading the memory. The upper bound for a number of locations is based on a group of constraints for the memory. The method receives a summed value of a plurality of memory values in the plurality of locations in the memory.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: May 12, 2020
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Conrad D. James, Tu-Thach Quach, Sapan Agarwal, James Bradley Aimone
  • Patent number: 10615781
    Abstract: A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: April 7, 2020
    Assignee: SK hynix Inc.
    Inventor: Young Hoon Kim
  • Patent number: 10511387
    Abstract: An RF frequency converter with equalization may include a first E/O modulator configured to modulate an optical carrier signal based upon an RF input signal having a first frequency, and a SBS medium coupled to the first E/O modulator. The RF frequency converter may have a second E/O modulator configured to modulate the optical carrier signal based upon an equalizing function waveform, and a third E/O modulator coupled between the first E/O modulator and the SBS medium. The third E/O modulator may be configured to modulate the optical carrier signal with a reference signal. The RF frequency converter may include an optical circulator coupled to the SBS medium and the second E/O modulator, and a photodetector coupled to the optical circulator and configured to generate an equalized RF output signal having a replica of the RF input signal at a second frequency based upon the reference signal.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: December 17, 2019
    Assignee: EAGLE TECHNOLOGY, LLC
    Inventors: Charles F. Middleton, IV, John R. Desalvo, Elliott J. Grafer, Anthony C. Klee, Alexander D. Cramer, George W. Miles, IV
  • Patent number: 10483997
    Abstract: A method for frequency domain to time domain conversion includes receiving a set of frequency-domain samples. Based on the set of frequency-domain samples, a first sample subset comprising a predetermined fraction of the number of samples of the set of frequency-domain samples and a second sample subset comprising the predetermined fraction of the number of samples of the set of frequency-domain samples are generated. A linear phase rotation is applied to the first sample subset and the second sample subset to produce a phase rotated first sample subset and a phase rotated second sample subset. The phase rotated first sample set is post-processed to generate a first set of time-domain samples. The phase rotated second sample set is post-processed to generate a second set of time-domain samples. The first set of time-domain samples and the second set of time-domain samples are reordered to produce an output set of time-domain samples.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: November 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind Ganesan, Jaiganesh Balakrishnan, Sashidharan Venkatraman, Bragadeesh Suresh Babu
  • Patent number: 10476704
    Abstract: Disclosed is a mechanism for limiting Intersymbol Interference (ISI) when measuring uncorrelated jitter in a test and measurement system. A waveform is obtained that describes a signal. Such waveform may be obtained from memory. A processor then extracts a signal impulse response from the waveform. The processor selects a window function based on a shape of the signal impulse response. Further, the processor applies the window function to the signal impulse response to remove ISI outside a window of the window function while measuring waveform jitter. The window function may be applied by applying the window function to the signal impulse response to obtain a target impulse response. A linear equalizer is then generated that results in the target impulse response when convolved with the signal impulse response. The linear equalizer is then applied to the waveform to limit ISI for jitter measurement.
    Type: Grant
    Filed: September 8, 2018
    Date of Patent: November 12, 2019
    Assignee: Tektronix, Inc.
    Inventor: Kan Tan
  • Patent number: 10447508
    Abstract: A device includes a first bias level generator to generate a first bias level of a plurality of bias levels and transmit the bias level having a first voltage value, a second bias level generator to generate a second bias level of the plurality of bias levels and transmit the second bias level having a second voltage value. The device also includes a voltage divider that interpolates a subset of bias levels of the plurality of bias levels between the first bias level and the second bias level and supplies a selected bias level of the plurality of bias levels a control signal to an adjustment circuit of a decision feedback equalizer to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Raghukiran Sreeramaneni, Jennifer E. Taylor
  • Patent number: 10392930
    Abstract: Systems, methods, and computer-readable media for channel estimation in mud pulse telemetry based on a preamble waveform. A system located at a first location of a wellbore can receive, from a second device located at a second location of the wellbore, a signal including a Golay preamble waveform and data symbols. The Golay preamble waveform can be based on Golay complementary codes. Based on a measurement associated with the signal, the system can then detect the Golay preamble waveform in the signal. Next, the system can estimate a characteristic of a communication channel between the first location and the second location based on the detected Golay preamble waveform.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 27, 2019
    Assignee: HALLIBURTON ENERGY SERVICES, INC.
    Inventor: Wenbing Dang
  • Patent number: 10389555
    Abstract: A technique includes determining a first phase delay associated with communication of a bit pattern having a first bit transition frequency over a communication channel; and determining a second phase delay associated with communication of a bit pattern having a second bit transition frequency greater than the first bit transition frequency over the communication channel. The technique includes regulating a compensation applied to a signal received from the communication channel based at least in part on a difference of the first and second phase delays.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: August 20, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Dacheng Zhou, Daniel Alan Berkram, Peter David Maroni
  • Patent number: 10372573
    Abstract: A method for generating one or more test patterns and selecting optimized test patterns among the test patterns to verify an integrity of convolution operations is provided for fault tolerance, fluctuation robustness in extreme situations, functional safety of the convolution operations, and annotation cost reduction. The method includes: a computing device (a) instructing a pattern generating unit to generate the test patterns by using a certain function such that saturation does not occur while at least one original CNN applies the convolution operations to the test patterns; (b) instructing a pattern evaluation unit to generate each of evaluation scores of each of the test patterns by referring to each of the test patterns and one or more parameters of the original CNN; and (c) instructing a pattern selection unit to select the optimized test patterns among the test patterns by referring to the evaluation scores.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: August 6, 2019
    Assignee: Stradvision, INC.
    Inventors: Kye-Hyeon Kim, Yongjoong Kim, Insu Kim, Hak-Kyoung Kim, Woonhyun Nam, SukHoon Boo, Myungchul Sung, Donghun Yeo, Wooju Ryu, Taewoong Jang, Kyungjoong Jeong, Hongmo Je, Hojin Cho
  • Patent number: 10326422
    Abstract: A parameter processing method, an audio signal playing method and device of an audio equalizer, and an audio equalizer are provided. The parameter processing method includes: acquiring a current parameter preset set and a predetermined target parameter preset set of the audio equalizer, linearly processing at least a part of parameters in the current parameter preset set, to enable the parameters processed linearly to be identical to target parameters in the target parameter preset set.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: June 18, 2019
    Assignee: CHINA ACADEMY OF TELECOMMUNICATIONS TECHNOLOGY
    Inventor: Min Liang
  • Patent number: 10263663
    Abstract: Some embodiments include apparatus and methods using an input node, an analog to digital converter (ADC) including an input coupled to the input node, a first feedforward equalizer (FFE) including an input coupled to an output of the ADC, a second FFE including an input coupled to the output of the ADC, and a decision feedback equalizer (DFE) including a first input, a second input, and an output, the first input coupled to an output of the first FFE, and the second input coupled to an output of the second FFE.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Shiva Kiran, Tzu-Chien Hsueh, James E. Jaussi
  • Patent number: 10235987
    Abstract: A method and apparatus that cancel component noise are provided. The method includes: detecting a trigger to activate component noise cancellation, in response to detecting the trigger, receiving feedforward information from a component, generating noise cancellation information based on the feedforward information, and outputting a noise cancellation sound according to the noise cancellation information.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: March 19, 2019
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Frank C. Valeri, Michael E. McGuire, Amy K. Luebke, Christopher A. Stirlen, Timothy J. Roggenkamp
  • Patent number: 10212006
    Abstract: A filtering device includes a low-pass filter (LPF), a noise estimation circuit and a first combining circuit. The LPF receives and filters a pre-filtering signal to generate an output signal of the filtering device. The noise estimation circuit estimates an estimated noise signal according to the output signal and the pre-filtering signal. The first combining circuit subtracts the estimated noise signal from an input signal of the filtering device to generate the pre-filtering signal.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: February 19, 2019
    Assignee: MEDIATEK INC.
    Inventor: Tai-You Lu
  • Patent number: 10205445
    Abstract: A duty cycle correction (DCC) circuit includes first and second pluralities of logic gates, a low pass filter, an error amplifier, and a differential amplifier. The DCC circuit receives first and second clock signals from the VCO. The first and second pluralities of logic gates receive first and second superimposed clock signals and generate first and second output clock signals, respectively. The error amplifier rectifies a common error of the first and second output clock signals, and generates a common mode error voltage signal. The differential amplifier generates first and second error signals based on the common mode error voltage signal. The first and second error signals converge the duty cycles of the first and second output clock signals to a 50% duty cycle.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: February 12, 2019
    Assignee: Synopsys, Inc.
    Inventors: Shourya Kansal, Biman Chattopadhyay, Ravi Mehta, Jayesh Wadekar
  • Patent number: 10171177
    Abstract: It is difficult to obtain a demodulated signal with high signal quality in a digital optical receiver because it is difficult to compensate for each of different types of waveform distortion by a high-performance equalization process; therefore, a digital signal processor according to an exemplary aspect of the present invention includes a fixed equalization means for performing a distortion compensation process based on a fixed equalization coefficient on an input digital signal; an adaptive equalization means for performing an adaptive distortion compensation process based on an adaptive equalization coefficient on an equalized digital signal output by the fixed equalization means; a low-speed signal generation means for generating a low-speed digital signal by intermittently extracting one of the input digital signal and the equalized digital signal; a low-speed equalization coefficient calculation means for calculating a low-speed equalization coefficient to be used for a distortion compensation process o
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: January 1, 2019
    Assignee: NEC CORPORATION
    Inventors: Wakako Yasuda, Hidemi Noguchi
  • Patent number: 10135647
    Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: November 20, 2018
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Fariborz Assaderaghi, Brian S. Leibowitz, Hae-Chang Lee, Jihong Ren, Qi Lin
  • Patent number: 10097384
    Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: October 9, 2018
    Assignee: SK hynix Inc.
    Inventors: Kwan Su Shon, Yo Han Jeong
  • Patent number: 10063253
    Abstract: Some embodiments include apparatuses having a first circuit portion, a second circuit portion, and a third circuit portion. The first circuit portion includes a first transistor to receive a first signal of a differential signal pair and a second transistor to receive a second signal of the differential signal pair. The second circuit portion is coupled to the first and second transistors and a first supply node, the second circuit portion including a first output node and a second output node to provide an output signal pair based on the differential signal pair. The third circuit portion includes a first diode-connected transistor coupled between the first output node and a second supply node and a second diode-connected transistor coupled between the second output node and the second supply node.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: August 28, 2018
    Assignee: Intel Corporation
    Inventors: Xiaoqing Wang, Shenggao Li
  • Patent number: 9948334
    Abstract: Systems and methods for canceling cross-coupled satellite signals in a LNB IC include receiving a first satellite signal at a first input of the LNB IC and filtering the first satellite signal using a first adaptive filter, the first adaptive filter having first filter coefficients; combining the adjusted first satellite signal with a second satellite signal received at a second input of the LNB IC to generate a first combined satellite signal; measuring the total output power of the combined satellite signal; changing the filter coefficients of the first adaptive filter; remeasuring the total output power of the first combined satellite signal after the changing of the first filter coefficients to determine whether the total power of the first combined satellite signal has decreased.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: April 17, 2018
    Assignee: Entropic Communications, LLC.
    Inventors: Branislav Petrovic, Tommy Yu, Troy Brandon, Ralph Duncan
  • Patent number: 9935795
    Abstract: A driver circuit device using driver equalization in power and ground terminated transmission line channels. The driver circuit device can include a weaker pull-up driver, which is needed to pre-emphasize the pull-up signal for driver equalization in power terminated transmission line channels. The driver circuit device can also include a weaker pull-down driver, which is needed to pre-emphasize the pull-down signal for driver equalization in ground terminated transmission line channels. In the transmission line channels with power terminations, a weaker pull-up Ron is implemented. In the transmission line channels with ground terminations, a weaker pull-down Ron is implemented. Drivers implemented in power and/or ground terminated transmission line channels can be used to improve device performance, such as in signal eye opening.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: April 3, 2018
    Assignee: INPHI CORPORATION
    Inventors: Liang Leon Zhang, Friedel Gerfers, Carl Pobanz, Myoung Joon Choi, Vivek Gurumoorthy, Chienhsin Lee
  • Patent number: 9928212
    Abstract: A method is explained for any adaptive processor processing digital signals by adjusting signal weights on digital signal(s) it handles, to optimize adaptation criteria responsive to a functional purpose or externalities (transient, temporary, situational, and even permanent) of that processor. Adaptation criteria for the adaptive algorithm may be any combination of a signal or parameter estimation, and measured quality(ies). This method performs a linear transformation adapting parameters from M to (M1+L) dimensions in each adaptation event, such that M1 weights are updated without constraints and M0=M?M1 weights are forced by soft constraints into an L-dimensional subspace they spanned at the beginning of the adaptation period. The same dimensionality reduction, using the same linear transformation, is applied to the input data.
    Type: Grant
    Filed: November 1, 2014
    Date of Patent: March 27, 2018
    Inventor: Brian G. Agee
  • Patent number: 9912499
    Abstract: An electronic device for a wireless communication system is described. The electronic device comprises: a receiver configured to receive a modulated signal on a communication channel; and a processor, coupled to the receiver and configured to: process the received modulated signal; identify a communication channel characteristic based on the processed received modulated signal; select an equalizer having a first set of equalization coefficients based on the identified communication channel characteristic, wherein the first set of equalization coefficients is selected from a plurality of equalization coefficients, each of the plurality of equalization coefficients being associated with different communication channel characteristics; equalize the processed received modulated signal on the communication channel using the selected equalizer; and detect the equalized received modulated signal.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: March 6, 2018
    Assignee: MediaTek, Inc.
    Inventors: Balachander Narasimhan, Charles Chien, Qiang Zhou, Chih-Yuan Lin, Cheng-Chou Zhan, Bao-Chi Peng
  • Patent number: 9906309
    Abstract: A processor circuit is provided in a coherent optical receiver module. The processor receives a series of electrical signals over a time period, representative of a series of optical signals received at instants of time within the time period. Each of the electrical signals is indicative of a respective one of a plurality of points on an IQ plane, each of the points being spaced from one of a plurality of predetermined points in the IQ plane by a corresponding one of a plurality of distortion values. In addition, the processor circuit calculates one or more perturbative coefficients based on one or more of the distortion values and determines data from the series of electrical signals based on the perturbative coefficient.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: February 27, 2018
    Assignee: Infinera Corporation
    Inventors: Pierre Hervé Mertz, Abdullah Karar, Ahmed Awadalla
  • Patent number: 9892631
    Abstract: An audio and ultrasound signal processing circuit (412), comprising: an audio input terminal (414) for receiving an input signal comprising an audio input signal; an amplitude detector (430), configured to determine an amplitude of the input signal and provide an amplitude level signal (432); a gain calculator (434) configured to determine an ultrasound amplification factor (436) in accordance with the amplitude level signal (432) and a target amplitude signal (418); a variable ultrasound amplifier (438) configured to receive an ultrasound input signal and modulate an amplitude of the ultrasound input signal in accordance with the ultrasound amplification factor (436) in order to provide an amplified ultrasound signal; and an output terminal (416) for providing an enhanced output signal comprising frequency components that correspond to the audio input signal and frequency components that correspond to the amplified ultrasound signal.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: February 13, 2018
    Assignee: NXP B.V.
    Inventor: Christophe Marc Macours
  • Patent number: 9853599
    Abstract: An antenna array includes a plurality of power amplifiers, each having a signal input, a signal output coupled to a cell of the antenna array, and a power input. The antenna array includes a plurality of power supplies, each power supply individually and separately coupled to a corresponding one of the plurality of power amplifiers at a respective power input. The antenna array further includes single a pre-distortion linearizer with a linearizer input that receives a signal and a linearizer output that is coupled to each signal input of each of the plurality of power amplifiers. Each power amplifier is operated in gain compression by setting its operating voltage according to a power output of the power amplifier.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: December 26, 2017
    Assignee: The Boeing Company
    Inventors: Rodney K. Bonebright, Brian K. Kormanyos, Thomas H. Friddell
  • Patent number: 9853609
    Abstract: A semiconductor apparatus includes a receiver configured to generate an output signal by amplifying an input signal received through a channel, and compensate distortion of the input signal based on a control signal preset according to a voltage level of the input signal, and an internal circuit configured to operate in response to the output signal.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: December 26, 2017
    Assignee: SK hynix Inc.
    Inventor: Jin Ha Hwang
  • Patent number: 9847766
    Abstract: Systems, devices, and methods for determining and establishing frequency-dependent gain compensation in wide bandwidth communication systems are disclosed. Variable frequency-dependent gain compensation circuits, or variable equalizers, have settings that configure them to establish discrete frequency-dependent gain compensation. The frequency-dependent gain compensation can include various types and levels of gain slope and/or ripple. The settings of the variable equalizers can be set by control signals established a control circuit in response to signals from an external computer. The variable equalizers are coupled to other circuits or devices and the frequency-dependent gain of the combined circuit are measured. The settings of the variable equalizer are then changed to establish an optimal frequency-dependent gain profile or frequency-dependent gain that is closest to a predetermined frequency-dependent target gain profile. The settings can then be saved in a memory or register.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: December 19, 2017
    Assignee: VIASAT, INC.
    Inventors: Kenneth V Buer, Michael R Lyons
  • Patent number: 9838777
    Abstract: [Object] To make it possible to further improve acoustic characteristics. [Solution] There is provided a headphone including: a driver unit including a vibration plate; a housing configured to house the driver unit, to form an air-tightened front air chamber of which a part except for an opening for sound output is spatially blocked from the outside on a front side on which the vibration plate of the driver unit is provided, and to form a rear air chamber that has a predetermined capacity on a rear side that is the opposite side to the front side; and an acoustic tube provided in a partial region of a partition wall of the housing that constitutes the rear air chamber and configured to spatially connect the rear air chamber and the outside of the housing through a tube.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: December 5, 2017
    Assignee: SONY CORPORATION
    Inventors: Eiji Kuwahara, Takahiro Suzuki
  • Patent number: 9780979
    Abstract: A analog equalizer includes: an adjusting circuit, generating an adjustment signal and a selection signal; a cascaded equalization circuit, receiving the adjustment signal, and adjusting at least one of a tunable resistor, a tunable capacitor and a tunable current source in the multi-stage equalization circuit according to the adjustment signal to perform an equalization process on a signal to be equalized; and an analog multiplexer, coupled to the cascaded equalization circuit and the adjusting circuit, selecting and outputting an equalized signal outputted from one stage of the multi-stage equalization circuit according to the selection signal. Wherein, the adjusting circuit adjusts the adjustment signal and the selection signal according to the equalized signal outputted from the analog multiplexer and a target equalization value.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: October 3, 2017
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Kai Sun, Jiunn-Yih Lee, Wen-Cai Lu
  • Patent number: 9768993
    Abstract: A plurality of high-frequency components 12 that are provided in parallel between an input-side transmission circuit 10 and an output-side transmission circuit 11 and have pass characteristics different from each other are included, each high-frequency component 12 includes a power supply terminal 17 to which a driving power supply signal is selectively input, a signal transmitted through the input-side transmission circuit 10 is transmitted to the output-side transmission circuit 11 via a transmission path including only the high-frequency component in which the driving power supply signal is input to the power supply terminal 17 among the plurality of high-frequency components 12, and at least one of the plurality of high-frequency components 12 function as an equalizer that changes a frequency characteristic of the signal input to the input-side transmission circuit 10 due to the driving power supply signal being input to the power supply terminal 17.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: September 19, 2017
    Assignee: ANRITSU CORPORATION
    Inventors: Takanari Minami, Sumio Saito
  • Patent number: 9768783
    Abstract: Integrated circuits such as application specific circuits or programmable logic devices may include specialized blocks such as configurable storage blocks and configurable processing blocks. Such specialized blocks may be controlled by clock signals and operated at single data rate or at double data rate. For instance, configurable storage blocks may be configured to use a double data rate communications scheme or a single data rate communication scheme to communicate data with other blocks. Configurable processing blocks may be configured to process data at a double data rate or a single data rate. Furthermore, configurable processing blocks that include accumulator circuitry may be configured to perform one accumulation at a single data rate or at a double data rate. Such configurable processing blocks may also be configured to perform two accumulations at a single data rate.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: September 19, 2017
    Assignee: Altera Corporation
    Inventors: Herman Schmit, Jiefan Zhang
  • Patent number: 9762376
    Abstract: A method, an apparatus, and a transceiver for cancelling multi-carrier transmission interference are provided. The method includes: collecting a high order intermodulation signal in radio frequency signals output by a transmitter; processing the high order intermodulation signal so as to generate a first digital signal; establishing a high order intermodulation model by using the first digital signal and a first baseband signal output by the transmitter; generating a second digital signal by using a coefficient of the high order intermodulation model and a second baseband signal output by the transmitter; and counteracting interference in a digital signal output by a receiver with the second digital signal. By using the embodiments of the embodiments of the invention, high order intermodulation interference of a multi-carrier transmitter on a receiver can be effectively canceled, and therefore, difficulty in duplexer design and requirements on a suppression degree are reduced.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: September 12, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mengda Mao, Siqing Ye, Qian Yin, Tao Pu
  • Patent number: 9762417
    Abstract: The present invention pertains to systems and methods for equalizing a digitally modulated input signal for transmission as an optical signal over an optical fiber. In detail, this equalization is accomplished prior to the signal's conversion to an optical signal, and prior to the signal being filtered by a vestigial sideband (VSB) filter. In particular, equalization is accomplished by giving weights to the taps of a tapped delay equalizer, wherein weights for respective taps are derived from the output signal after its conversion to a digital signal at the downstream end of the optical fiber.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: September 12, 2017
    Assignee: Integra Research and Development, LLC
    Inventors: Chen-Kuo Sun, Paul N. Huntley, Charlie Chen, Dingbo Chen
  • Patent number: 9749746
    Abstract: A noise-suppression device includes an input buffer, a spatial filter, a delay buffer, and a controller. The input buffer stores sound data. The spatial filter generates processed data by using an internal adaptive control according to a control signal. The delay buffer stores the processed data. The controller operates in either one of a training stage, a flushing stage, or a normal stage and generates the control signal. When the controller operates in the training stage, the spatial filter receives the sound data from the input buffer to generate the processed data which is continuously processed by the spatial filter and then stored in the delay buffer over and over again until the internal adaptive control is converged.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: August 29, 2017
    Assignee: FORTEMEDIA, INC.
    Inventor: Yan-Chen Lu
  • Patent number: 9722822
    Abstract: A driver circuit device using driver equalization in power and ground terminated transmission line channels. The driver circuit device can include a weaker pull-up driver, which is needed to pre-emphasize the pull-up signal for driver equalization in power terminated transmission line channels. The driver circuit device can also include a weaker pull-down driver, which is needed to pre-emphasize the pull-down signal for driver equalization in ground terminated transmission line channels. In the transmission line channels with power terminations, a weaker pull-up Ron is implemented. In the transmission line channels with ground terminations, a weaker pull-down Ron is implemented. Drivers implemented in power and/or ground terminated transmission line channels can be used to improve device performance, such as in signal eye opening.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: August 1, 2017
    Assignee: INPHI CORPORATION
    Inventors: Liang Leon Zhang, Friedel Gerfers, Carl Pobanz, Myoung Joon Choi, Vivek Gurumoorthy, Chienhsin Lee
  • Patent number: 9722828
    Abstract: In one embodiment, a receiver comprises a latch configured to receive a data signal and to latch symbols of the received data signal, and a decision feedback equalizer. The decision feedback equalizer comprises a first feedback capacitor having first and second terminals, the first terminal being coupled to a first internal node of the latch. The decision feedback equalizer also comprises a first plurality of switches configured to alternatively couple the second terminal of the first feedback capacitor to a first feedback signal and a ground, the first feedback signal having a first voltage that is a function of a bit decision corresponding to a first previous symbol in the data signal preceding a current symbol in the data signal.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: August 1, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Li Sun, Xiaohua Kong, Zhi Zhu, Miao Li, Dong Ren
  • Patent number: 9660841
    Abstract: Receiver circuitry is disclosed that can take circuit branches offline to possibly adapt an offset value. In one embodiment, a circuit in a receiver has at least two branches. Each branch includes an adjustor to adjust the branch signal by an offset value. Selection circuitry takes one of the branches offline by selecting the output of that branch as an offline value, and by selecting the output of one or more of the other branches as a data decision value. The selection circuitry changes which branch is taken offline during the operation of the circuit. When a branch is taken offline, an offset value associated with that branch may be updated, if necessary.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: May 23, 2017
    Assignee: INPHI CORPORATION
    Inventors: Stephane Dallaire, Benjamin P. Smith, Travis William Lovitt, Arash Farhoodfar
  • Patent number: 9661248
    Abstract: The present invention relates to an integrated circuit having a flexible reference. In an example, the integrated circuit includes a reference generator, and the reference generator can generate a flexible reference signal in response to a control signal. The flexible reference signal can be changed freely by adjusting the control signal. By providing the flexible reference, the present invention can enhance the capability of verification and characterization for an integrated circuit design and reduce the physical layout area of the integrated circuit design. The present invention also relates to a method of operating the integrated circuit with a flexible reference signal.
    Type: Grant
    Filed: December 7, 2014
    Date of Patent: May 23, 2017
    Assignee: CISTA SYSTEM CORP.
    Inventors: Dennis Tunglin Lee, Guangbin Zhang
  • Patent number: 9660538
    Abstract: Apparatus and method for providing closed loop feedback control for switch-mode DC/DC power converter with multiple outputs using digital filter feedback, in contrast to analog error feedback. In the apparatus and method, multiple outputs for a switch-mode DC/DC power converter are regulated by digital means, including the allocating or partitioning of digital control resources among each of the multiple outputs. The partitioning of control resources may be in response to operating conditions.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: May 23, 2017
    Assignee: SWITCHING POWER, INC.
    Inventor: Keng C. Wu
  • Patent number: 9647857
    Abstract: An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: May 9, 2017
    Assignee: Massachusetts Institute of Technology
    Inventor: William J. Dally
  • Patent number: 9628220
    Abstract: A device for transmit (TX) training a remote link partner (LP) includes a TX retimer module adjacent to a TX port of the device, and a receive (RX) retimer module adjacent to the TX retimer module. The RX retimer module copies first control and status data to the TX retimer module, and the TX retimer module provides second control and status data for TX training of the remote LP.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: April 18, 2017
    Assignee: Broadcom Corporation
    Inventor: Magesh Valliappan
  • Patent number: 9590731
    Abstract: A signal equalizer for compensating impairments of an optical signal received through a link of a high speed optical communications network. At least one set of compensation vectors are computed for compensating at least two distinct types of impairments. A frequency domain processor is coupled to receive respective raw multi-bit in-phase (I) and quadrature (Q) sample streams of each received polarization of the optical signal. The frequency domain processor operates to digitally process the multi-bit sample streams, using the compensation vectors, to generate multi-bit estimates of symbols modulated onto each transmitted polarization of the optical signal. The frequency domain processor exhibits respective different responses to each one of the at least two distinct types of impairments.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: March 7, 2017
    Assignee: Ciena Corporation
    Inventors: Kim B. Roberts, Han Sun
  • Patent number: 9577690
    Abstract: A processor, comprising a first data input configured to receive a stream of samples of a first signal having a spectral space, the stream having a data rate of at least 4 GHz; a second data input configured to receive a stream of samples of a second signal; a multitap correlator, configured to receive the first stream of samples and the second stream of samples, and producing at least one correlation output for each respective sequential sample of the first signal received; and a programmable control configured to alter a relationship of the stream of samples of the first signal and the stream of samples of the second signal, to thereby select, under program control, an alterable correlation output.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: February 21, 2017
    Assignee: Hypres, Inc.
    Inventor: Deepnarayan Gupta
  • Patent number: 9509530
    Abstract: A transmitting circuit is connected to a communication line and configured to transmit a primary signal, being a current signal, to the communication line by changing a current flowing from a transmission unit via the communication line. A receiving circuit is configured to receive a secondary signal which is generated by converting the primary signal transmitted from the transmitting circuit to a voltage signal by a current/voltage converter provided between the transmission unit and the communication line. Specifically, the primary signal, being a current signal transmitted from a communication terminal, is converted to the secondary signal being a voltage signal by the current/voltage converter. As a result, communication can be performed even when the impedance of the communication line is reduced, facilitating introduction of a communication system.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: November 29, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tadashi Matsumoto, Shoji Koise
  • Patent number: 9503061
    Abstract: A system and method is disclosed for adaptively adjusting a duty cycle of a signal between a first and second chip in a 3D architecture/stack for adaptively calibrating a chip in a 3D architecture/stack. In one embodiment, the system includes a first chip and a second chip located within the 3D chip stack, wherein the first chip generates a calibration signal, the second chip receives the calibration signal and compares it to a reference signal to generate a comparison signal that further compared to a reference duty signal to generate a reference duty comparison signal, that is then provided to the first chip to generate a drive signal that adjusts a duty cycle of the calibration signal.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Yu Hsu, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 9484974
    Abstract: The various embodiments include methods and apparatuses for canceling nonlinear interference during concurrent communication of multi-technology wireless communication devices. Nonlinear interference may be estimated using a multilayer perceptron neural network with Hammerstein structure by dividing an aggressor signal into real and imaginary components, augmenting the components by weight factors, executing a linear combination of the augmented components, and executing a nonlinear sigmoid function for the combined components at a hidden layer of multilayer perceptron neural network to produce a hidden layer output signal. At an output layer, hidden layer output signals may be augmented by weight factors, and the augmented hidden layer output signals may be linearly combined to produce real and imaginary components of an estimated jammer signal.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: November 1, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Sheng-Yuan Tu, Farrokh Abrishamkar, Parisa Cheraghi, Insung Kang, Reza Shahidi
  • Patent number: 9467315
    Abstract: Receiver circuitry is disclosed that can take circuit branches offline to possibly adapt an offset value. In one embodiment, a circuit in a receiver has at least two branches. Each branch includes an adjustor to adjust the branch signal by an offset value. Selection circuitry takes one of the branches offline by selecting the output of that branch as an offline value, and by selecting the output of one or more of the other branches as a data decision value. The selection circuitry changes which branch is taken offline during the operation of the circuit. When a branch is taken offline, an offset value associated with that branch may be updated, if necessary.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: October 11, 2016
    Assignee: Inphi Corporation
    Inventors: Stephane Dallaire, Benjamin P. Smith, Travis William Lovitt, Arash Farhoodfar