Latching/ejecting levers for electronic circuit board
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FIG. 1 is a front perspective view of a first embodiment of a latching ejecting lever for an electronic circuit board showing our new design, the circuit board being fragmentarily shown in broken lines for illustrative purposes only;
FIG. 2 is a bottom plan view thereof on an enlarged scale;
FIG. 3 is a top plan view thereof on an enlarged scale;
FIG. 4 is a right side elevational view thereof on an enlarged scale;
FIG. 5 is a front elevational view thereof on an enlarged scale;
FIG. 6 is a left side elevational view thereof on an enlarged scale;
FIG. 7 is a rear elevational view thereof on an enlarged scale;
FIG. 8 is a front perspective view of a second embodiment of our new design, the circuit board being fragmentarily shown in broken lines for illustrative purposes only;
FIG. 9 is a top plan view thereof on an enlarged scale;
FIG. 10 is a bottom plan view thereof on an enlarged scale;
FIG. 11 is an inverted left side elevational view thereof on an enlarged scale;
FIG. 12 is an inverted front elevational view thereof on an enlarged scale;
FIG. 13 is an inverted right side elevational view thereof on an enlarged scale;
FIG. 14 is an inverted rear elevational view thereof on an enlarges scale.
Type: Grant
Filed: Feb 7, 1985
Date of Patent: Apr 26, 1988
Assignee: Northern Telecom Limited (Montreal)
Inventors: Michael H. Fitzpatrick (Sunnyvale, CA), Michael Brown (Nepean)
Primary Examiner: Susan J. Lucas
Assistant Examiner: Clare E. Heflin
Law Firm: Schwartz, Jeffery, Schwaab, Mack, Blumenthal & Evans
Application Number: 6/699,308