In-line semiconductor package

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Description

FIG. 1 is a top, front and left side perspective view of an in-line semiconductor package showing my new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a front elevational view thereof;

FIG. 4 is a bottom plan view thereof;

FIG. 5 is a rear elevational view thereof;

FIG. 6 is a left side elevational view thereof;

FIG. 7 is a right side elevational view thereof;

FIG. 8 is a top, front and left side perspective view of an in-line semiconductor package showing a second embodiment of my new design;

FIG. 9 is a top plan view thereof;

FIG. 10 is a front elevational view thereof;

FIG. 11 is a bottom plan view thereof;

FIG. 12 is a rear elevational view thereof;

FIG. 13 is a right side elevational view thereof, the left side being a mirror image;

FIG. 14 is a top, front and left side perspective view of an in-line semiconductor package showing a third embodiment of my new design;

FIG. 15 is a bottom, left and rear perspective view thereof;

FIG. 16 is a top, front and left side perspective view of an in-line semiconductor package showing a fourth embodiment of my new design;

FIG. 17 is a bottom, left and rear perspective view thereof;

FIG. 18 is a top, front and left side perspective view of an in-line semiconductor package showing a fifth embodiment of my new design;

FIG. 19 is a bottom, left and rear perspective view thereof;

FIG. 20 is a right side elevational view of the third, fourth and fifth embodiments of my new design.

Referenced Cited
U.S. Patent Documents
D247032 January 24, 1978 Hollingsworth et al.
D288922 March 24, 1987 Olla
3249827 May 1966 Benda et al.
4032706 June 28, 1977 Paletto
4275279 June 23, 1981 Wagatsuma et al.
4807087 February 21, 1989 Sawaya
Other references
  • Fujitsu Limited, Data Book-Memories, 1986-87 (pp. 1-28, 1-30, 1-129 and 1-147). Hitachi, IC Memory Data Book, Mar., 1988 (p. 7). Mitsubishi Electric Corp., Mitsubishi Semiconductors-IC Memories, 1987 (pp. 1-35, 1-38 and 1-40). NEC Electrics, Inc., Memory Products Data Book, 1989 (pp. 10-9 and 10-10). Samsung Semiconductor, MOS Memory Data Book, 1988 (pp. 46, 58, 72, 88 and 103). Toshiba America, Inc., MOS Memory, 1988 (pp. A-34, A-49, A-90 and A-111).
Patent History
Patent number: D316251
Type: Grant
Filed: Dec 19, 1988
Date of Patent: Apr 16, 1991
Assignee: Mosaic Semiconductor, Inc. (San Diego, CA)
Inventor: David Y. Armstrong (San Diego, CA)
Primary Examiner: Susan J. Lucas
Assistant Examiner: Joel Sincavage
Law Firm: Knobbe, Martens, Olson & Bear
Application Number: 7/287,982