Semi-conductor mounting substrate

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Description

FIG. 1 is a top perspective view of a semi-conductor mounting substrate showing our new design;

FIG. 2 is a bottom perspective view thereof;

FIG. 3 is a right side elevational view thereof;

FIG. 4 is a left side elevational view thereof;

FIG. 5 is a rear elevational view thereof; and

FIG. 6 is a front elevational view thereof.

Referenced Cited
U.S. Patent Documents
4288841 September 8, 1981 Gogal
4338621 July 6, 1982 Braun
4437141 March 13, 1984 Prokop
4458291 July 3, 1984 Yanagisawa et al.
4513355 April 23, 1985 Shroeder et al.
4677526 June 30, 1987 Muehling et al.
4698663 October 6, 1987 Sugimoto et al.
Foreign Patent Documents
0048945 March 1983 JPX
0150353 July 1986 JPX
0271863 December 1986 JPX
0035653 February 1987 JPX
Other references
  • Disc Controller Pictured on p. 190, Electronic Design, 10-16-86. NCR IC Package Pictured on p. 7, Electronic Design, 10-16-86. CMOS Chip Pictured on p. 131, Electronics, 8-7-86. Fujitsu Substrate Pictured on p. 7, Electronics, 2-24-86.
Patent History
Patent number: D317300
Type: Grant
Filed: Jan 4, 1988
Date of Patent: Jun 4, 1991
Inventors: Terutomi Hasegawa (Ogaki-City, Gifu pref.), Nobumichi Goto (Seki City Gifu Pref)
Primary Examiner: Susan J. Lucas
Assistant Examiner: Joel Sincavage
Law Firm: Lorusso & Loud
Application Number: 7/140,433